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Searched defs:XCHAL_HAVE_PREFETCH_L1 (Results 1 – 5 of 5) sorted by relevance

/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h192 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h220 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h229 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h243 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h294 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */ macro