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Searched defs:XCHAL_HAVE_MIMIC_CACHEATTR (Results 1 – 10 of 10) sorted by relevance

/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h344 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h406 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h436 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h455 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h456 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h457 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h557 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h593 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h614 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h696 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro