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Searched defs:XCHAL_DCACHE_LINEWIDTH (Results 1 – 10 of 10) sorted by relevance

/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h119 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h123 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h159 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h152 #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h183 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h162 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h211 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h220 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h234 #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ macro
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h283 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro