1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _WX_TYPE_H_ 5 #define _WX_TYPE_H_ 6 7 #include <linux/ptp_clock_kernel.h> 8 #include <linux/timecounter.h> 9 #include <linux/bitfield.h> 10 #include <linux/netdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/phylink.h> 13 #include <linux/dim.h> 14 #include <net/ip.h> 15 16 #define WX_NCSI_SUP 0x8000 17 #define WX_NCSI_MASK 0x8000 18 #define WX_WOL_SUP 0x4000 19 #define WX_WOL_MASK 0x4000 20 21 /* MSI-X capability fields masks */ 22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF 23 #define WX_PCI_LINK_STATUS 0xB2 24 #define WX_MAX_PF_MACVLANS 15 25 #define WX_MAX_VF_MC_ENTRIES 30 26 27 /**************** Global Registers ****************************/ 28 #define WX_VF_REG_OFFSET(_v) FIELD_GET(GENMASK(15, 5), (_v)) 29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v)) 30 31 /* chip control Registers */ 32 #define WX_MIS_PWR 0x10000 33 #define WX_MIS_RST 0x1000C 34 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1) 35 #define WX_MIS_RST_SW_RST BIT(0) 36 #define WX_MIS_ST 0x10028 37 #define WX_MIS_ST_MNG_INIT_DN BIT(0) 38 #define WX_MIS_SWSM 0x1002C 39 #define WX_MIS_SWSM_SMBI BIT(0) 40 #define WX_MIS_RST_ST 0x10030 41 #define WX_MIS_RST_ST_RST_INI_SHIFT 8 42 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT) 43 44 /* FMGR Registers */ 45 #define WX_SPI_CMD 0x10104 46 #define WX_SPI_CMD_READ_DWORD 0x1 47 #define WX_SPI_CLK_DIV 0x3 48 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v) 49 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v) 50 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v) 51 #define WX_SPI_DATA 0x10108 52 #define WX_SPI_DATA_BYPASS BIT(31) 53 #define WX_SPI_DATA_OP_DONE BIT(0) 54 #define WX_SPI_STATUS 0x1010C 55 #define WX_SPI_STATUS_OPDONE BIT(0) 56 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31) 57 #define WX_SPI_ILDR_STATUS 0x10120 58 59 /* Sensors for PVT(Process Voltage Temperature) */ 60 #define WX_TS_EN 0x10304 61 #define WX_TS_EN_ENA BIT(0) 62 #define WX_TS_ALARM_THRE 0x1030C 63 #define WX_TS_DALARM_THRE 0x10310 64 #define WX_TS_INT_EN 0x10314 65 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1) 66 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0) 67 #define WX_TS_ALARM_ST 0x10318 68 #define WX_TS_ALARM_ST_DALARM BIT(1) 69 #define WX_TS_ALARM_ST_ALARM BIT(0) 70 71 /* statistic */ 72 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C 73 #define WX_TX_BC_FRAMES_GOOD_L 0x11824 74 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C 75 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900 76 #define WX_RX_BC_FRAMES_GOOD_L 0x11918 77 #define WX_RX_MC_FRAMES_GOOD_L 0x11920 78 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928 79 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978 80 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938 81 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C 82 #define WX_MAC_LXOFFRXC 0x11988 83 #define WX_MAC_LXONRXC 0x11E0C 84 #define WX_MAC_LXOFFRXC_AML 0x11F80 85 #define WX_MAC_LXONRXC_AML 0x11F84 86 87 /*********************** Receive DMA registers **************************/ 88 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4)) 89 #define WX_RDM_RSC_CTL 0x1200C 90 #define WX_RDM_RSC_CTL_FREE_CNT_DIS BIT(8) 91 #define WX_RDM_RSC_CTL_FREE_CTL BIT(7) 92 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4)) 93 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4)) 94 #define WX_RDM_DCACHE_CTL 0x120A8 95 #define WX_RDM_DCACHE_CTL_EN BIT(0) 96 #define WX_RDM_DRP_PKT 0x12500 97 #define WX_RDM_PKT_CNT 0x12504 98 #define WX_RDM_BYTE_CNT_LSB 0x12508 99 #define WX_RDM_BMC2OS_CNT 0x12510 100 101 /************************* Port Registers ************************************/ 102 /* port cfg Registers */ 103 #define WX_CFG_PORT_CTL 0x14400 104 #define WX_CFG_PORT_CTL_PFRSTD BIT(14) 105 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3) 106 #define WX_CFG_PORT_CTL_QINQ BIT(2) 107 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/ 108 #define WX_CFG_PORT_ST 0x14404 109 #define WX_CFG_PORT_ST_LANID GENMASK(9, 8) 110 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4)) 111 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */ 112 113 #define WX_CFG_PORT_CTL_NUM_VT_NONE 0 114 #define WX_CFG_PORT_CTL_NUM_VT_8 FIELD_PREP(GENMASK(13, 12), 1) 115 #define WX_CFG_PORT_CTL_NUM_VT_32 FIELD_PREP(GENMASK(13, 12), 2) 116 #define WX_CFG_PORT_CTL_NUM_VT_64 FIELD_PREP(GENMASK(13, 12), 3) 117 118 /* GPIO Registers */ 119 #define WX_GPIO_DR 0x14800 120 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */ 121 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */ 122 #define WX_GPIO_DDR 0x14804 123 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */ 124 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */ 125 #define WX_GPIO_CTL 0x14808 126 #define WX_GPIO_INTEN 0x14830 127 #define WX_GPIO_INTEN_0 BIT(0) 128 #define WX_GPIO_INTEN_1 BIT(1) 129 #define WX_GPIO_INTMASK 0x14834 130 #define WX_GPIO_INTTYPE_LEVEL 0x14838 131 #define WX_GPIO_POLARITY 0x1483C 132 #define WX_GPIO_INTSTATUS 0x14844 133 #define WX_GPIO_EOI 0x1484C 134 #define WX_GPIO_EXT 0x14850 135 136 /*********************** Transmit DMA registers **************************/ 137 /* transmit global control */ 138 #define WX_TDM_CTL 0x18000 139 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4)) 140 #define WX_TDM_MAC_AS(_i) (0x18060 + ((_i) * 4)) 141 #define WX_TDM_VLAN_AS(_i) (0x18070 + ((_i) * 4)) 142 #define WX_TDM_VFTE_CLR(_i) (0x180A0 + ((_i) * 4)) 143 144 /* TDM CTL BIT */ 145 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */ 146 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4)) 147 #define WX_TDM_RP_IDX 0x1820C 148 #define WX_TDM_PKT_CNT 0x18308 149 #define WX_TDM_BYTE_CNT_LSB 0x1830C 150 #define WX_TDM_OS2BMC_CNT 0x18314 151 #define WX_TDM_RP_RATE 0x18404 152 153 /***************************** RDB registers *********************************/ 154 /* receive packet buffer */ 155 #define WX_RDB_PB_CTL 0x19000 156 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */ 157 #define WX_RDB_PB_CTL_DISABLED BIT(0) 158 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4)) 159 #define WX_RDB_PB_SZ_SHIFT 10 160 /* statistic */ 161 #define WX_RDB_PFCMACDAL 0x19210 162 #define WX_RDB_PFCMACDAH 0x19214 163 #define WX_RDB_LXOFFTXC 0x19218 164 #define WX_RDB_LXONTXC 0x1921C 165 /* Flow Control Registers */ 166 #define WX_RDB_RFCV 0x19200 167 #define WX_RDB_RFCL 0x19220 168 #define WX_RDB_RFCL_XONE BIT(31) 169 #define WX_RDB_RFCH 0x19260 170 #define WX_RDB_RFCH_XOFFE BIT(31) 171 #define WX_RDB_RFCRT 0x192A0 172 #define WX_RDB_RFCC 0x192A4 173 #define WX_RDB_RFCC_RFCE_802_3X BIT(3) 174 /* ring assignment */ 175 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4)) 176 #define WX_RDB_PL_CFG_L4HDR BIT(1) 177 #define WX_RDB_PL_CFG_L3HDR BIT(2) 178 #define WX_RDB_PL_CFG_L2HDR BIT(3) 179 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4) 180 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5) 181 #define WX_RDB_PL_CFG_RSS_EN BIT(24) 182 #define WX_RDB_PL_CFG_RSS_MASK GENMASK(23, 16) 183 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4)) 184 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4)) 185 #define WX_RDB_RA_CTL 0x194F4 186 #define WX_RDB_RA_CTL_MULTI_RSS BIT(0) 187 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */ 188 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16) 189 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17) 190 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20) 191 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21) 192 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22) 193 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23) 194 #define WX_RDB_RA_CTL_RSS_MASK GENMASK(23, 16) 195 #define WX_RDB_FDIR_MATCH 0x19558 196 #define WX_RDB_FDIR_MISS 0x1955C 197 /* VM RSS */ 198 #define WX_RDB_VMRSSRK(_i, _p) (0x1A000 + ((_i) * 4) + ((_p) * 0x40)) 199 #define WX_RDB_VMRSSTBL(_i, _p) (0x1B000 + ((_i) * 4) + ((_p) * 0x40)) 200 201 /******************************* PSR Registers *******************************/ 202 /* psr control */ 203 #define WX_PSR_CTL 0x15000 204 #define WX_PSR_VM_CTL 0x151B0 205 /* Header split receive */ 206 #define WX_PSR_CTL_SW_EN BIT(18) 207 #define WX_PSR_CTL_RSC_ACK BIT(17) 208 #define WX_PSR_CTL_RSC_DIS BIT(16) 209 #define WX_PSR_CTL_PCSD BIT(13) 210 #define WX_PSR_CTL_IPPCSE BIT(12) 211 #define WX_PSR_CTL_BAM BIT(10) 212 #define WX_PSR_CTL_UPE BIT(9) 213 #define WX_PSR_CTL_MPE BIT(8) 214 #define WX_PSR_CTL_MFE BIT(7) 215 #define WX_PSR_CTL_MO_SHIFT 5 216 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT) 217 #define WX_PSR_CTL_TPE BIT(4) 218 #define WX_PSR_MAX_SZ 0x15020 219 #define WX_PSR_VLAN_CTL 0x15088 220 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */ 221 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */ 222 /* EType Queue Filter */ 223 #define WX_PSR_ETYPE_SWC(_i) (0x15128 + ((_i) * 4)) 224 #define WX_PSR_ETYPE_SWC_FILTER_1588 3 225 #define WX_PSR_ETYPE_SWC_FILTER_EN BIT(31) 226 #define WX_PSR_ETYPE_SWC_1588 BIT(30) 227 /* 1588 */ 228 #define WX_PSR_1588_MSG 0x15120 229 #define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0) 230 #define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1) 231 #define WX_PSR_1588_STMPL 0x151E8 232 #define WX_PSR_1588_STMPH 0x151A4 233 #define WX_PSR_1588_CTL 0x15188 234 #define WX_PSR_1588_CTL_ENABLED BIT(4) 235 #define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1) 236 #define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1) 237 #define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5) 238 #define WX_PSR_1588_CTL_VALID BIT(0) 239 /* mcasst/ucast overflow tbl */ 240 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4)) 241 #define WX_PSR_MC_TBL_REG(_i) FIELD_GET(GENMASK(11, 5), (_i)) 242 #define WX_PSR_MC_TBL_BIT(_i) FIELD_GET(GENMASK(4, 0), (_i)) 243 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4)) 244 #define WX_PSR_VM_CTL_REPLEN BIT(30) /* replication enabled */ 245 #define WX_PSR_VM_CTL_POOL_MASK GENMASK(12, 7) 246 247 /* VM L2 contorl */ 248 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4)) 249 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */ 250 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */ 251 #define WX_PSR_VM_L2CTL_VPE BIT(7) /* vlan promiscuous mode */ 252 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */ 253 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */ 254 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */ 255 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */ 256 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */ 257 258 /* Management */ 259 #define WX_PSR_MNG_FLEX_SEL 0x1582C 260 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16)) 261 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16)) 262 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16)) 263 #define WX_PSR_LAN_FLEX_SEL 0x15B8C 264 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16)) 265 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16)) 266 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16)) 267 268 #define WX_PSR_WKUP_CTL 0x15B80 269 /* Wake Up Filter Control Bit */ 270 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */ 271 272 /* vlan tbl */ 273 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4)) 274 275 /* mac switcher */ 276 #define WX_PSR_MAC_SWC_AD_L 0x16200 277 #define WX_PSR_MAC_SWC_AD_H 0x16204 278 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v) 279 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v) 280 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31) 281 #define WX_PSR_MAC_SWC_VM_L 0x16208 282 #define WX_PSR_MAC_SWC_VM_H 0x1620C 283 #define WX_PSR_MAC_SWC_IDX 0x16210 284 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU 285 286 /* vlan switch */ 287 #define WX_PSR_VLAN_SWC 0x16220 288 #define WX_PSR_VLAN_SWC_VM_L 0x16224 289 #define WX_PSR_VLAN_SWC_VM_H 0x16228 290 #define WX_PSR_VLAN_SWC_VM(_i) (0x16224 + ((_i) * 4)) 291 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */ 292 /* VLAN pool filtering masks */ 293 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */ 294 #define WX_PSR_VLAN_SWC_ENTRIES 64 295 #define WX_PSR_VLAN_SWC_VLANID_MASK GENMASK(11, 0) 296 297 /********************************* RSEC **************************************/ 298 /* general rsec */ 299 #define WX_RSC_CTL 0x17000 300 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6) 301 #define WX_RSC_CTL_CRC_STRIP BIT(2) 302 #define WX_RSC_CTL_RX_DIS BIT(1) 303 #define WX_RSC_ST 0x17004 304 #define WX_RSC_ST_RSEC_RDY BIT(0) 305 306 /*********************** Transmit DMA registers **************************/ 307 /* transmit global control */ 308 #define WX_TDM_ETYPE_AS(_i) (0x18058 + ((_i) * 4)) 309 #define WX_TDM_VLAN_INS(_i) (0x18100 + ((_i) * 4)) 310 /* Per VF Port VLAN insertion rules */ 311 #define WX_TDM_VLAN_INS_VLANA_DEFAULT BIT(30) /* Always use default VLAN*/ 312 313 /****************************** TDB ******************************************/ 314 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4)) 315 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 316 317 /****************************** TSEC *****************************************/ 318 /* Security Control Registers */ 319 #define WX_TSC_CTL 0x1D000 320 #define WX_TSC_CTL_TX_DIS BIT(1) 321 #define WX_TSC_CTL_TSEC_DIS BIT(0) 322 #define WX_TSC_ST 0x1D004 323 #define WX_TSC_ST_SECTX_RDY BIT(0) 324 #define WX_TSC_BUF_AE 0x1D00C 325 #define WX_TSC_BUF_AE_THR GENMASK(9, 0) 326 /* 1588 */ 327 #define WX_TSC_1588_CTL 0x11F00 328 #define WX_TSC_1588_CTL_ENABLED BIT(4) 329 #define WX_TSC_1588_CTL_VALID BIT(0) 330 #define WX_TSC_1588_STMPL 0x11F04 331 #define WX_TSC_1588_STMPH 0x11F08 332 #define WX_TSC_1588_SYSTIML 0x11F0C 333 #define WX_TSC_1588_SYSTIMH 0x11F10 334 #define WX_TSC_1588_INC 0x11F14 335 #define WX_TSC_1588_INT_ST 0x11F20 336 #define WX_TSC_1588_INT_ST_TT1 BIT(5) 337 #define WX_TSC_1588_INT_EN 0x11F24 338 #define WX_TSC_1588_INT_EN_TT1 BIT(5) 339 #define WX_TSC_1588_AUX_CTL 0x11F28 340 #define WX_TSC_1588_AUX_CTL_EN_TS0 BIT(8) 341 #define WX_TSC_1588_AUX_CTL_EN_TT1 BIT(2) 342 #define WX_TSC_1588_AUX_CTL_PLSG BIT(1) 343 #define WX_TSC_1588_AUX_CTL_EN_TT0 BIT(0) 344 #define WX_TSC_1588_TRGT_L(i) (0x11F2C + ((i) * 8)) /* [0,1] */ 345 #define WX_TSC_1588_TRGT_H(i) (0x11F30 + ((i) * 8)) /* [0,1] */ 346 #define WX_TSC_1588_SDP(i) (0x11F5C + ((i) * 4)) /* [0,3] */ 347 #define WX_TSC_1588_SDP_OUT_LEVEL_H FIELD_PREP(BIT(4), 0) 348 #define WX_TSC_1588_SDP_OUT_LEVEL_L FIELD_PREP(BIT(4), 1) 349 #define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0) 350 #define WX_TSC_1588_SDP_FUN_SEL_TT0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 1) 351 #define WX_TSC_1588_SDP_FUN_SEL_TS0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 5) 352 353 /************************************** MNG ********************************/ 354 #define WX_MNG_SWFW_SYNC 0x1E008 355 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2) 356 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3) 357 #define WX_MNG_MBOX 0x1E100 358 #define WX_MNG_MBOX_CTL 0x1E044 359 #define WX_MNG_MBOX_CTL_SWRDY BIT(0) 360 #define WX_MNG_MBOX_CTL_FWRDY BIT(2) 361 #define WX_MNG_BMC2OS_CNT 0x1E090 362 #define WX_MNG_OS2BMC_CNT 0x1E094 363 #define WX_SW2FW_MBOX_CMD 0x1E0A0 364 #define WX_SW2FW_MBOX_CMD_VLD BIT(31) 365 #define WX_SW2FW_MBOX 0x1E200 366 #define WX_FW2SW_MBOX 0x1E300 367 368 /************************************* ETH MAC *****************************/ 369 #define WX_MAC_TX_CFG 0x11000 370 #define WX_MAC_TX_CFG_TE BIT(0) 371 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29) 372 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0) 373 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3) 374 #define WX_MAC_RX_CFG 0x11004 375 #define WX_MAC_RX_CFG_RE BIT(0) 376 #define WX_MAC_RX_CFG_JE BIT(8) 377 #define WX_MAC_PKT_FLT 0x11008 378 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */ 379 #define WX_MAC_WDG_TIMEOUT 0x1100C 380 #define WX_MAC_RX_FLOW_CTRL 0x11090 381 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */ 382 383 #define WX_MAC_WDG_TIMEOUT_WTO_MASK GENMASK(3, 0) 384 #define WX_MAC_WDG_TIMEOUT_WTO_DELTA 2 385 /* MDIO Registers */ 386 #define WX_MSCA 0x11200 387 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v) 388 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v) 389 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v) 390 #define WX_MSCC 0x11204 391 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v) 392 393 enum WX_MSCA_CMD_value { 394 WX_MSCA_CMD_RSV = 0, 395 WX_MSCA_CMD_WRITE, 396 WX_MSCA_CMD_POST_READ, 397 WX_MSCA_CMD_READ, 398 }; 399 400 #define WX_MSCC_SADDR BIT(18) 401 #define WX_MSCC_BUSY BIT(22) 402 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v) 403 #define WX_MDIO_CLAUSE_SELECT 0x11220 404 #define WX_MMC_CONTROL 0x11800 405 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */ 406 407 /********************************* BAR registers ***************************/ 408 /* Interrupt Registers */ 409 #define WX_BME_CTL 0x12020 410 #define WX_PX_MISC_IC 0x100 411 #define WX_PX_MISC_ICS 0x104 412 #define WX_PX_MISC_IEN 0x108 413 #define WX_PX_INTA 0x110 414 #define WX_PX_GPIE 0x118 415 #define WX_PX_GPIE_MODEL BIT(0) 416 #define WX_PX_IC(_i) (0x120 + (_i) * 4) 417 #define WX_PX_IMS(_i) (0x140 + (_i) * 4) 418 #define WX_PX_IMC(_i) (0x150 + (_i) * 4) 419 #define WX_PX_ISB_ADDR_L 0x160 420 #define WX_PX_ISB_ADDR_H 0x164 421 #define WX_PX_TRANSACTION_PENDING 0x168 422 #define WX_PX_ITRSEL 0x180 423 #define WX_PX_ITR(_i) (0x200 + (_i) * 4) 424 #define WX_PX_ITR_CNT_WDIS BIT(31) 425 #define WX_PX_MISC_IVAR 0x4FC 426 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4) 427 428 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 429 #define WX_7K_ITR 595 430 #define WX_12K_ITR 336 431 #define WX_20K_ITR 200 432 #define WX_MIN_RSC_ITR 24 433 #define WX_SP_MAX_EITR 0x00000FF8U 434 #define WX_AML_MAX_EITR 0x00000FFFU 435 #define WX_EM_MAX_EITR 0x00007FFCU 436 437 /* transmit DMA Registers */ 438 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40)) 439 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40)) 440 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40)) 441 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40)) 442 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40)) 443 #define WX_PX_TR_HEAD_ADDRL(_i) (0x03028 + ((_i) * 0x40)) 444 #define WX_PX_TR_HEAD_ADDRH(_i) (0x0302C + ((_i) * 0x40)) 445 /* Transmit Config masks */ 446 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */ 447 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */ 448 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */ 449 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 450 #define WX_PX_TR_CFG_THRE_SHIFT 8 451 #define WX_PX_TR_CFG_HEAD_WB BIT(27) 452 453 /* Receive DMA Registers */ 454 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40)) 455 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40)) 456 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40)) 457 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40)) 458 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40)) 459 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40)) 460 /* PX_RR_CFG bit definitions */ 461 #define WX_PX_RR_CFG_VLAN BIT(31) 462 #define WX_PX_RR_CFG_DROP_EN BIT(30) 463 #define WX_PX_RR_CFG_RSC BIT(29) 464 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26) 465 #define WX_PX_RR_CFG_MAX_RSCBUF_16 FIELD_PREP(GENMASK(24, 23), 3) 466 #define WX_PX_RR_CFG_DESC_MERGE BIT(19) 467 #define WX_PX_RR_CFG_RR_THER_SHIFT 16 468 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12) 469 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8) 470 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6) 471 * + at bit 8 offset (<< 12) 472 * = (<< 6) 473 */ 474 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */ 475 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1 476 #define WX_PX_RR_CFG_RR_EN BIT(0) 477 478 /* Number of 80 microseconds we wait for PCI Express master disable */ 479 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000 480 481 #define WX_RSS_64Q_MASK 0x3F 482 #define WX_RSS_8Q_MASK 0x7 483 #define WX_RSS_4Q_MASK 0x3 484 #define WX_RSS_2Q_MASK 0x1 485 #define WX_RSS_DISABLED_MASK 0x0 486 487 #define WX_VMDQ_4Q_MASK 0x7C 488 #define WX_VMDQ_2Q_MASK 0x7E 489 490 /****************** Manageablility Host Interface defines ********************/ 491 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */ 492 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */ 493 #define WX_HIC_HDR_INDEX_MAX 255 494 495 #define FW_READ_SHADOW_RAM_CMD 0x31 496 #define FW_READ_SHADOW_RAM_LEN 0x6 497 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 498 #define FW_NVM_DATA_OFFSET 3 499 #define FW_MAX_READ_BUFFER_SIZE 244 500 #define FW_RESET_CMD 0xDF 501 #define FW_RESET_LEN 0x2 502 #define FW_CEM_HDR_LEN 0x4 503 #define FW_CEM_CMD_RESERVED 0X0 504 #define FW_CEM_MAX_RETRIES 3 505 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 506 #define FW_PPS_SET_CMD 0xF6 507 #define FW_PPS_SET_LEN 0x14 508 509 #define WX_SW_REGION_PTR 0x1C 510 511 #define WX_MAC_STATE_DEFAULT 0x1 512 #define WX_MAC_STATE_MODIFIED 0x2 513 #define WX_MAC_STATE_IN_USE 0x4 514 515 /* BitTimes (BT) conversion */ 516 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024)) 517 #define WX_B2BT(BT) ((BT) * 8) 518 519 /* Calculate Delay to respond to PFC */ 520 #define WX_PFC_D 672 521 /* Calculate Cable Delay */ 522 #define WX_CABLE_DC 5556 /* Delay Copper */ 523 /* Calculate Delay incurred from higher layer */ 524 #define WX_HD 6144 525 526 /* Calculate Interface Delay */ 527 #define WX_PHY_D 12800 528 #define WX_MAC_D 4096 529 #define WX_XAUI_D (2 * 1024) 530 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D) 531 /* Calculate PCI Bus delay for low thresholds */ 532 #define WX_PCI_DELAY 10000 533 534 /* Calculate delay value in bit times */ 535 #define WX_DV(_max_frame_link, _max_frame_tc) \ 536 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \ 537 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \ 538 2 * WX_B2BT(_max_frame_tc)) 539 540 /* Calculate low threshold delay values */ 541 #define WX_LOW_DV(_max_frame_tc) \ 542 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1)) 543 544 /* flow control */ 545 #define WX_DEFAULT_FCPAUSE 0xFFFF 546 547 #define WX_MAX_RXD 8192 548 #define WX_MAX_TXD 8192 549 #define WX_MIN_RXD 128 550 #define WX_MIN_TXD 128 551 552 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */ 553 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128 554 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128 555 556 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */ 557 #define VMDQ_P(p) ((p) + wx->ring_feature[RING_F_VMDQ].offset) 558 559 /* Supported Rx Buffer Sizes */ 560 #define WX_RXBUFFER_256 256 /* Used for skb receive header */ 561 #define WX_RXBUFFER_2K 2048 562 #define WX_RXBUFFER_3K 3072 563 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */ 564 565 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 566 567 #define WX_MAX_DATA_PER_TXD BIT(14) 568 /* Tx Descriptors needed, worst case */ 569 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD) 570 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 571 572 /******************* Receive Descriptor bit definitions **********************/ 573 #define WX_RXD_STAT_DD BIT(0) /* Done */ 574 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */ 575 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */ 576 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */ 577 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */ 578 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/ 579 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */ 580 #define WX_RXD_STAT_TS BIT(14) /* IEEE1588 Time Stamp */ 581 582 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */ 583 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */ 584 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */ 585 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */ 586 587 /* RSS Hash results */ 588 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0) 589 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U 590 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U 591 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U 592 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U 593 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U 594 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U 595 596 #define WX_RSS_L4_TYPES_MASK \ 597 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \ 598 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \ 599 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \ 600 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \ 601 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \ 602 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP)) 603 /* TUN */ 604 #define WX_PTYPE_TUN_IPV4 0x80 605 #define WX_PTYPE_TUN_IPV6 0xC0 606 607 /* PKT for TUN */ 608 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */ 609 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */ 610 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */ 611 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */ 612 /* PKT for !TUN */ 613 #define WX_PTYPE_PKT_MAC 0x10 614 #define WX_PTYPE_PKT_IP 0x20 615 616 /* TYP for PKT=mac */ 617 #define WX_PTYPE_TYP_MAC 0x01 618 /* TYP for PKT=ip */ 619 #define WX_PTYPE_PKT_IPV6 0x08 620 #define WX_PTYPE_TYP_IPFRAG 0x01 621 #define WX_PTYPE_TYP_IP 0x02 622 #define WX_PTYPE_TYP_UDP 0x03 623 #define WX_PTYPE_TYP_TCP 0x04 624 #define WX_PTYPE_TYP_SCTP 0x05 625 626 /* Packet type non-ip values */ 627 enum wx_l2_ptypes { 628 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC), 629 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC), 630 631 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG), 632 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP), 633 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP), 634 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP), 635 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP), 636 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 | 637 WX_PTYPE_TYP_IPFRAG), 638 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 | 639 WX_PTYPE_TYP_IP), 640 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 | 641 WX_PTYPE_TYP_UDP), 642 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 | 643 WX_PTYPE_TYP_TCP), 644 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 | 645 WX_PTYPE_TYP_SCTP), 646 647 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM), 648 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM), 649 }; 650 651 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30) 652 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07) 653 654 #define WX_RXD_PKTTYPE(_rxd) \ 655 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF) 656 657 #define WX_RXD_RSCCNT_MASK GENMASK(20, 17) 658 #define WX_RXD_RSCCNT_SHIFT 17 659 #define WX_RXD_NEXTP_MASK GENMASK(19, 4) 660 #define WX_RXD_NEXTP_SHIFT 4 661 662 /*********************** Transmit Descriptor Config Masks ****************/ 663 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */ 664 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */ 665 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */ 666 #define WX_TXD_EOP BIT(24) /* End of Packet */ 667 #define WX_TXD_IFCS BIT(25) /* Insert FCS */ 668 #define WX_TXD_RS BIT(27) /* Report Status */ 669 670 /*********************** Adv Transmit Descriptor Config Masks ****************/ 671 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */ 672 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */ 673 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */ 674 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */ 675 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */ 676 #define WX_TXD_CC BIT(7) /* Check Context */ 677 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */ 678 #define WX_TXD_L4CS BIT(9) 679 #define WX_TXD_IIPCS BIT(10) 680 #define WX_TXD_EIPCS BIT(11) 681 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */ 682 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 683 #define WX_TXD_TAG_TPID_SEL_SHIFT 11 684 685 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 686 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 687 688 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */ 689 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */ 690 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */ 691 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0) 692 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1) 693 694 enum wx_tx_flags { 695 /* cmd_type flags */ 696 WX_TX_FLAGS_HW_VLAN = 0x01, 697 WX_TX_FLAGS_TSO = 0x02, 698 WX_TX_FLAGS_TSTAMP = 0x04, 699 700 /* olinfo flags */ 701 WX_TX_FLAGS_CC = 0x08, 702 WX_TX_FLAGS_IPV4 = 0x10, 703 WX_TX_FLAGS_CSUM = 0x20, 704 WX_TX_FLAGS_OUTER_IPV4 = 0x100, 705 WX_TX_FLAGS_LINKSEC = 0x200, 706 WX_TX_FLAGS_IPSEC = 0x400, 707 708 /* software defined flags */ 709 WX_TX_FLAGS_SW_VLAN = 0x40, 710 }; 711 712 /* VLAN info */ 713 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16) 714 #define WX_TX_FLAGS_VLAN_SHIFT 16 715 716 /* wx_dec_ptype.mac: outer mac */ 717 enum wx_dec_ptype_mac { 718 WX_DEC_PTYPE_MAC_IP = 0, 719 WX_DEC_PTYPE_MAC_L2 = 2, 720 WX_DEC_PTYPE_MAC_FCOE = 3, 721 }; 722 723 /* wx_dec_ptype.[e]ip: outer&encaped ip */ 724 #define WX_DEC_PTYPE_IP_FRAG 0x4 725 enum wx_dec_ptype_ip { 726 WX_DEC_PTYPE_IP_NONE = 0, 727 WX_DEC_PTYPE_IP_IPV4 = 1, 728 WX_DEC_PTYPE_IP_IPV6 = 2, 729 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4, 730 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6, 731 }; 732 733 /* wx_dec_ptype.etype: encaped type */ 734 enum wx_dec_ptype_etype { 735 WX_DEC_PTYPE_ETYPE_NONE = 0, 736 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */ 737 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */ 738 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */ 739 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */ 740 }; 741 742 /* wx_dec_ptype.proto: payload proto */ 743 enum wx_dec_ptype_prot { 744 WX_DEC_PTYPE_PROT_NONE = 0, 745 WX_DEC_PTYPE_PROT_UDP = 1, 746 WX_DEC_PTYPE_PROT_TCP = 2, 747 WX_DEC_PTYPE_PROT_SCTP = 3, 748 WX_DEC_PTYPE_PROT_ICMP = 4, 749 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */ 750 }; 751 752 /* wx_dec_ptype.layer: payload layer */ 753 enum wx_dec_ptype_layer { 754 WX_DEC_PTYPE_LAYER_NONE = 0, 755 WX_DEC_PTYPE_LAYER_PAY2 = 1, 756 WX_DEC_PTYPE_LAYER_PAY3 = 2, 757 WX_DEC_PTYPE_LAYER_PAY4 = 3, 758 }; 759 760 struct wx_dec_ptype { 761 u32 known:1; 762 u32 mac:2; /* outer mac */ 763 u32 ip:3; /* outer ip*/ 764 u32 etype:3; /* encaped type */ 765 u32 eip:3; /* encaped ip */ 766 u32 prot:4; /* payload proto */ 767 u32 layer:3; /* payload layer */ 768 }; 769 770 /* macro to make the table lines short */ 771 #define WX_PTT(mac, ip, etype, eip, proto, layer)\ 772 {1, \ 773 WX_DEC_PTYPE_MAC_##mac, /* mac */\ 774 WX_DEC_PTYPE_IP_##ip, /* ip */ \ 775 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\ 776 WX_DEC_PTYPE_IP_##eip, /* eip */\ 777 WX_DEC_PTYPE_PROT_##proto, /* proto */\ 778 WX_DEC_PTYPE_LAYER_##layer /* layer */} 779 780 /* Host Interface Command Structures */ 781 struct wx_hic_hdr { 782 u8 cmd; 783 u8 buf_len; 784 union { 785 u8 cmd_resv; 786 u8 ret_status; 787 } cmd_or_resp; 788 union { 789 u8 checksum; 790 u8 index; 791 }; 792 }; 793 794 struct wx_hic_hdr2_req { 795 u8 cmd; 796 u8 buf_lenh; 797 u8 buf_lenl; 798 union { 799 u8 checksum; 800 u8 index; 801 }; 802 }; 803 804 struct wx_hic_hdr2_rsp { 805 u8 cmd; 806 u8 buf_lenl; 807 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 808 union { 809 u8 checksum; 810 u8 index; 811 }; 812 }; 813 814 union wx_hic_hdr2 { 815 struct wx_hic_hdr2_req req; 816 struct wx_hic_hdr2_rsp rsp; 817 }; 818 819 /* These need to be dword aligned */ 820 struct wx_hic_read_shadow_ram { 821 union wx_hic_hdr2 hdr; 822 u32 address; 823 u16 length; 824 u16 pad2; 825 u16 data; 826 u16 pad3; 827 }; 828 829 struct wx_hic_reset { 830 struct wx_hic_hdr hdr; 831 u16 lan_id; 832 u16 reset_type; 833 }; 834 835 struct wx_hic_set_pps { 836 struct wx_hic_hdr hdr; 837 u8 lan_id; 838 u8 enable; 839 u16 pad2; 840 u64 nsec; 841 u64 cycles; 842 }; 843 844 /* Bus parameters */ 845 struct wx_bus_info { 846 u8 func; 847 u16 device; 848 }; 849 850 struct wx_mbx_info { 851 u16 size; 852 u32 mailbox; 853 u32 udelay; 854 u32 timeout; 855 /* lock mbx access */ 856 spinlock_t mbx_lock; 857 }; 858 859 struct wx_thermal_sensor_data { 860 s16 temp; 861 s16 alarm_thresh; 862 s16 dalarm_thresh; 863 }; 864 865 enum wx_mac_type { 866 wx_mac_unknown = 0, 867 wx_mac_sp, 868 wx_mac_em, 869 wx_mac_aml, 870 wx_mac_aml40, 871 }; 872 873 enum wx_media_type { 874 wx_media_unknown = 0, 875 wx_media_fiber, 876 wx_media_copper, 877 wx_media_backplane 878 }; 879 880 enum em_mac_type { 881 em_mac_type_unknown = 0, 882 em_mac_type_mdi, 883 em_mac_type_rgmii 884 }; 885 886 struct wx_mac_info { 887 enum wx_mac_type type; 888 bool set_lben; 889 u8 addr[ETH_ALEN]; 890 u8 perm_addr[ETH_ALEN]; 891 u32 mta_shadow[128]; 892 s32 mc_filter_type; 893 u32 mcft_size; 894 u32 vft_shadow[128]; 895 u32 vft_size; 896 u32 num_rar_entries; 897 u32 rx_pb_size; 898 u32 tx_pb_size; 899 u32 max_tx_queues; 900 u32 max_rx_queues; 901 902 u16 max_msix_vectors; 903 struct wx_thermal_sensor_data sensor; 904 }; 905 906 enum wx_eeprom_type { 907 wx_eeprom_uninitialized = 0, 908 wx_eeprom_spi, 909 wx_flash, 910 wx_eeprom_none /* No NVM support */ 911 }; 912 913 struct wx_eeprom_info { 914 enum wx_eeprom_type type; 915 u32 semaphore_delay; 916 u16 word_size; 917 u16 sw_region_offset; 918 }; 919 920 struct wx_addr_filter_info { 921 u32 num_mc_addrs; 922 u32 mta_in_use; 923 bool user_set_promisc; 924 }; 925 926 struct wx_mac_addr { 927 u8 addr[ETH_ALEN]; 928 u16 state; /* bitmask */ 929 u64 pools; 930 }; 931 932 enum wx_reset_type { 933 WX_LAN_RESET = 0, 934 WX_SW_RESET, 935 WX_GLOBAL_RESET 936 }; 937 938 struct wx_cb { 939 dma_addr_t dma; 940 u16 append_cnt; /* number of skb's appended */ 941 bool dma_released; 942 }; 943 944 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb) 945 946 /* Transmit Descriptor */ 947 union wx_tx_desc { 948 struct { 949 __le64 buffer_addr; /* Address of descriptor's data buf */ 950 __le32 cmd_type_len; 951 __le32 olinfo_status; 952 } read; 953 struct { 954 __le64 rsvd; /* Reserved */ 955 __le32 nxtseq_seed; 956 __le32 status; 957 } wb; 958 }; 959 960 /* Receive Descriptor */ 961 union wx_rx_desc { 962 struct { 963 __le64 pkt_addr; /* Packet buffer address */ 964 __le64 hdr_addr; /* Header buffer address */ 965 } read; 966 struct { 967 struct { 968 union { 969 __le32 data; 970 struct { 971 __le16 pkt_info; /* RSS, Pkt type */ 972 __le16 hdr_info; /* Splithdr, hdrlen */ 973 } hs_rss; 974 } lo_dword; 975 union { 976 __le32 rss; /* RSS Hash */ 977 struct { 978 __le16 ip_id; /* IP id */ 979 __le16 csum; /* Packet Checksum */ 980 } csum_ip; 981 } hi_dword; 982 } lower; 983 struct { 984 __le32 status_error; /* ext status/error */ 985 __le16 length; /* Packet length */ 986 __le16 vlan; /* VLAN tag */ 987 } upper; 988 } wb; /* writeback */ 989 }; 990 991 struct wx_tx_context_desc { 992 __le32 vlan_macip_lens; 993 __le32 seqnum_seed; 994 __le32 type_tucmd_mlhl; 995 __le32 mss_l4len_idx; 996 }; 997 998 /* if _flag is in _input, return _result */ 999 #define WX_SET_FLAG(_input, _flag, _result) \ 1000 (((_flag) <= (_result)) ? \ 1001 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \ 1002 ((u32)((_input) & (_flag)) / ((_flag) / (_result)))) 1003 1004 #define WX_RX_DESC(R, i) \ 1005 (&(((union wx_rx_desc *)((R)->desc))[i])) 1006 #define WX_TX_DESC(R, i) \ 1007 (&(((union wx_tx_desc *)((R)->desc))[i])) 1008 #define WX_TX_CTXTDESC(R, i) \ 1009 (&(((struct wx_tx_context_desc *)((R)->desc))[i])) 1010 1011 /* wrapper around a pointer to a socket buffer, 1012 * so a DMA handle can be stored along with the buffer 1013 */ 1014 struct wx_tx_buffer { 1015 union wx_tx_desc *next_to_watch; 1016 unsigned long time_stamp; 1017 struct sk_buff *skb; 1018 unsigned int bytecount; 1019 unsigned short gso_segs; 1020 DEFINE_DMA_UNMAP_ADDR(dma); 1021 DEFINE_DMA_UNMAP_LEN(len); 1022 __be16 protocol; 1023 u32 tx_flags; 1024 u32 next_eop; 1025 }; 1026 1027 struct wx_rx_buffer { 1028 struct sk_buff *skb; 1029 dma_addr_t dma; 1030 struct page *page; 1031 unsigned int page_offset; 1032 }; 1033 1034 struct wx_queue_stats { 1035 u64 packets; 1036 u64 bytes; 1037 }; 1038 1039 struct wx_tx_queue_stats { 1040 u64 restart_queue; 1041 u64 tx_busy; 1042 }; 1043 1044 struct wx_rx_queue_stats { 1045 u64 non_eop_descs; 1046 u64 csum_good_cnt; 1047 u64 csum_err; 1048 u64 alloc_rx_buff_failed; 1049 u64 rsc_count; 1050 u64 rsc_flush; 1051 }; 1052 1053 /* iterator for handling rings in ring container */ 1054 #define wx_for_each_ring(posm, headm) \ 1055 for (posm = (headm).ring; posm; posm = posm->next) 1056 1057 struct wx_ring_container { 1058 struct wx_ring *ring; /* pointer to linked list of rings */ 1059 unsigned int total_bytes; /* total bytes processed this int */ 1060 unsigned int total_packets; /* total packets processed this int */ 1061 u8 count; /* total number of rings in vector */ 1062 u8 itr; /* current ITR setting for ring */ 1063 struct dim dim; /* data for net_dim algorithm */ 1064 }; 1065 struct wx_ring { 1066 struct wx_ring *next; /* pointer to next ring in q_vector */ 1067 struct wx_q_vector *q_vector; /* backpointer to host q_vector */ 1068 struct net_device *netdev; /* netdev ring belongs to */ 1069 struct device *dev; /* device for DMA mapping */ 1070 struct page_pool *page_pool; 1071 void *desc; /* descriptor ring memory */ 1072 union { 1073 struct wx_tx_buffer *tx_buffer_info; 1074 struct wx_rx_buffer *rx_buffer_info; 1075 }; 1076 u8 __iomem *tail; 1077 dma_addr_t dma; /* phys. address of descriptor ring */ 1078 dma_addr_t headwb_dma; 1079 u32 *headwb_mem; 1080 unsigned int size; /* length in bytes */ 1081 1082 u16 count; /* amount of descriptors */ 1083 unsigned long last_rx_timestamp; 1084 1085 u8 queue_index; /* needed for multiqueue queue management */ 1086 u8 reg_idx; /* holds the special value that gets 1087 * the hardware register offset 1088 * associated with this ring, which is 1089 * different for DCB and RSS modes 1090 */ 1091 u16 next_to_use; 1092 u16 next_to_clean; 1093 u16 rx_buf_len; 1094 union { 1095 u16 next_to_alloc; 1096 struct { 1097 u8 atr_sample_rate; 1098 u8 atr_count; 1099 }; 1100 }; 1101 1102 struct wx_queue_stats stats; 1103 struct u64_stats_sync syncp; 1104 union { 1105 struct wx_tx_queue_stats tx_stats; 1106 struct wx_rx_queue_stats rx_stats; 1107 }; 1108 } ____cacheline_internodealigned_in_smp; 1109 1110 struct wx_q_vector { 1111 struct wx *wx; 1112 int cpu; /* CPU for DCA */ 1113 int numa_node; 1114 u16 v_idx; /* index of q_vector within array, also used for 1115 * finding the bit in EICR and friends that 1116 * represents the vector for this ring 1117 */ 1118 u16 itr; /* Interrupt throttle rate written to EITR */ 1119 struct wx_ring_container rx, tx; 1120 struct napi_struct napi; 1121 struct rcu_head rcu; /* to avoid race with update stats on free */ 1122 1123 u16 total_events; /* number of interrupts processed */ 1124 1125 char name[IFNAMSIZ + 17]; 1126 1127 /* for dynamic allocation of rings associated with this q_vector */ 1128 struct wx_ring ring[] ____cacheline_internodealigned_in_smp; 1129 }; 1130 1131 struct wx_ring_feature { 1132 u16 limit; /* upper limit on feature indices */ 1133 u16 indices; /* current value of indices */ 1134 u16 mask; /* Mask used for feature to ring mapping */ 1135 u16 offset; /* offset to start of feature */ 1136 }; 1137 1138 enum wx_ring_f_enum { 1139 RING_F_NONE = 0, 1140 RING_F_VMDQ, 1141 RING_F_RSS, 1142 RING_F_FDIR, 1143 RING_F_ARRAY_SIZE /* must be last in enum set */ 1144 }; 1145 1146 enum wx_isb_idx { 1147 WX_ISB_HEADER, 1148 WX_ISB_MISC, 1149 WX_ISB_VEC0, 1150 WX_ISB_VEC1, 1151 WX_ISB_MAX 1152 }; 1153 1154 /* Flow Control Settings */ 1155 enum wx_fc_mode { 1156 wx_fc_none = 0, 1157 wx_fc_rx_pause, 1158 wx_fc_tx_pause, 1159 wx_fc_full 1160 }; 1161 1162 struct wx_fc_info { 1163 u32 high_water; /* Flow Ctrl High-water */ 1164 u32 low_water; /* Flow Ctrl Low-water */ 1165 enum wx_fc_mode mode; /* Flow Control Mode */ 1166 }; 1167 1168 /* Statistics counters collected by the MAC */ 1169 struct wx_hw_stats { 1170 u64 gprc; 1171 u64 gptc; 1172 u64 gorc; 1173 u64 gotc; 1174 u64 tpr; 1175 u64 tpt; 1176 u64 bprc; 1177 u64 bptc; 1178 u64 mprc; 1179 u64 mptc; 1180 u64 roc; 1181 u64 ruc; 1182 u64 lxonrxc; 1183 u64 lxoffrxc; 1184 u64 lxontxc; 1185 u64 lxofftxc; 1186 u64 o2bgptc; 1187 u64 b2ospc; 1188 u64 o2bspc; 1189 u64 b2ogprc; 1190 u64 rdmdrop; 1191 u64 crcerrs; 1192 u64 rlec; 1193 u64 qmprc; 1194 u64 fdirmatch; 1195 u64 fdirmiss; 1196 }; 1197 1198 struct wx_last_stats { 1199 u32 qmprc[128]; 1200 u32 lxoffrxc; 1201 u32 lxonrxc; 1202 }; 1203 1204 enum wx_state { 1205 WX_STATE_RESETTING, 1206 WX_STATE_SWFW_BUSY, 1207 WX_STATE_PTP_RUNNING, 1208 WX_STATE_PTP_TX_IN_PROGRESS, 1209 WX_STATE_SERVICE_SCHED, 1210 WX_STATE_NBITS /* must be last */ 1211 }; 1212 1213 struct vf_data_storage { 1214 struct pci_dev *vfdev; 1215 unsigned char vf_mac_addr[ETH_ALEN]; 1216 bool spoofchk_enabled; 1217 bool link_enable; 1218 bool trusted; 1219 int xcast_mode; 1220 unsigned int vf_api; 1221 bool clear_to_send; 1222 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 1223 u16 pf_qos; 1224 bool pf_set_mac; 1225 1226 u16 vf_mc_hashes[WX_MAX_VF_MC_ENTRIES]; 1227 u16 num_vf_mc_hashes; 1228 u16 vlan_count; 1229 int link_state; 1230 }; 1231 1232 struct vf_macvlans { 1233 struct list_head mvlist; 1234 int vf; 1235 bool free; 1236 bool is_macvlan; 1237 u8 vf_macvlan[ETH_ALEN]; 1238 }; 1239 1240 #define WX_RSS_FIELD_IPV4_TCP BIT(0) 1241 #define WX_RSS_FIELD_IPV4 BIT(1) 1242 #define WX_RSS_FIELD_IPV4_SCTP BIT(2) 1243 #define WX_RSS_FIELD_IPV6_SCTP BIT(3) 1244 #define WX_RSS_FIELD_IPV6_TCP BIT(4) 1245 #define WX_RSS_FIELD_IPV6 BIT(5) 1246 #define WX_RSS_FIELD_IPV4_UDP BIT(6) 1247 #define WX_RSS_FIELD_IPV6_UDP BIT(7) 1248 1249 struct wx_rss_flow_map { 1250 u8 flow_type; 1251 u32 data; 1252 u8 flag; 1253 }; 1254 1255 enum wx_pf_flags { 1256 WX_FLAG_MULTI_64_FUNC, 1257 WX_FLAG_SWFW_RING, 1258 WX_FLAG_VMDQ_ENABLED, 1259 WX_FLAG_VLAN_PROMISC, 1260 WX_FLAG_SRIOV_ENABLED, 1261 WX_FLAG_IRQ_VECTOR_SHARED, 1262 WX_FLAG_FDIR_CAPABLE, 1263 WX_FLAG_FDIR_HASH, 1264 WX_FLAG_FDIR_PERFECT, 1265 WX_FLAG_RSC_CAPABLE, 1266 WX_FLAG_RSC_ENABLED, 1267 WX_FLAG_RX_HWTSTAMP_ENABLED, 1268 WX_FLAG_RX_HWTSTAMP_IN_REGISTER, 1269 WX_FLAG_PTP_PPS_ENABLED, 1270 WX_FLAG_NEED_LINK_CONFIG, 1271 WX_FLAG_NEED_MODULE_RESET, 1272 WX_FLAG_NEED_UPDATE_LINK, 1273 WX_FLAG_NEED_DO_RESET, 1274 WX_FLAG_RX_MERGE_ENABLED, 1275 WX_FLAG_TXHEAD_WB_ENABLED, 1276 WX_PF_FLAGS_NBITS /* must be last */ 1277 }; 1278 1279 struct wx { 1280 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1281 DECLARE_BITMAP(state, WX_STATE_NBITS); 1282 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS); 1283 1284 void *priv; 1285 u8 __iomem *hw_addr; 1286 u8 __iomem *b4_addr; /* vf only */ 1287 struct pci_dev *pdev; 1288 struct net_device *netdev; 1289 struct wx_bus_info bus; 1290 struct wx_mbx_info mbx; 1291 struct wx_mac_info mac; 1292 enum em_mac_type mac_type; 1293 enum wx_media_type media_type; 1294 struct wx_eeprom_info eeprom; 1295 struct wx_addr_filter_info addr_ctrl; 1296 struct wx_fc_info fc; 1297 struct wx_mac_addr *mac_table; 1298 u16 device_id; 1299 u16 vendor_id; 1300 u16 subsystem_device_id; 1301 u16 subsystem_vendor_id; 1302 u8 revision_id; 1303 u16 oem_ssid; 1304 u16 oem_svid; 1305 u16 msg_enable; 1306 bool adapter_stopped; 1307 u16 tpid[8]; 1308 char eeprom_id[32]; 1309 char *driver_name; 1310 enum wx_reset_type reset_type; 1311 u8 swfw_index; 1312 1313 /* PHY stuff */ 1314 bool notify_down; 1315 unsigned int link; 1316 int speed; 1317 int duplex; 1318 struct phy_device *phydev; 1319 struct phylink *phylink; 1320 struct phylink_config phylink_config; 1321 1322 bool wol_hw_supported; 1323 bool ncsi_enabled; 1324 bool gpio_ctrl; 1325 raw_spinlock_t gpio_lock; 1326 1327 /* Tx fast path data */ 1328 int num_tx_queues; 1329 u16 tx_itr_setting; 1330 u16 tx_work_limit; 1331 1332 /* Rx fast path data */ 1333 int num_rx_queues; 1334 u16 rx_itr_setting; 1335 u16 rx_work_limit; 1336 bool adaptive_itr; 1337 1338 int num_q_vectors; /* current number of q_vectors for device */ 1339 int max_q_vectors; /* upper limit of q_vectors for device */ 1340 1341 u32 tx_ring_count; 1342 u32 rx_ring_count; 1343 1344 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp; 1345 struct wx_ring *rx_ring[64]; 1346 struct wx_q_vector *q_vector[64]; 1347 int num_rx_pools; 1348 int num_rx_queues_per_pool; 1349 1350 unsigned int queues_per_pool; 1351 struct msix_entry *msix_q_entries; 1352 struct msix_entry *msix_entry; 1353 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 1354 1355 /* misc interrupt status block */ 1356 dma_addr_t isb_dma; 1357 u32 *isb_mem; 1358 u32 isb_tag[WX_ISB_MAX]; 1359 bool misc_irq_domain; 1360 u32 eims_other; 1361 u32 eims_enable_mask; 1362 1363 #define WX_MAX_RETA_ENTRIES 128 1364 #define WX_RSS_INDIR_TBL_MAX 64 1365 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES]; 1366 u8 rss_flags; 1367 bool rss_enabled; 1368 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 1369 u32 *rss_key; 1370 u32 wol; 1371 1372 u16 bd_number; 1373 bool default_up; 1374 1375 struct wx_hw_stats stats; 1376 struct wx_last_stats last_stats; 1377 spinlock_t hw_stats_lock; /* spinlock for accessing to hw stats */ 1378 u64 tx_busy; 1379 u64 non_eop_descs; 1380 u64 restart_queue; 1381 u64 hw_csum_rx_good; 1382 u64 hw_csum_rx_error; 1383 u64 alloc_rx_buff_failed; 1384 u64 rsc_count; 1385 u64 rsc_flush; 1386 unsigned int num_vfs; 1387 struct vf_data_storage *vfinfo; 1388 struct vf_macvlans vf_mvs; 1389 struct vf_macvlans *mv_list; 1390 unsigned long fwd_bitmask; 1391 1392 u32 atr_sample_rate; 1393 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype); 1394 void (*configure_fdir)(struct wx *wx); 1395 int (*setup_tc)(struct net_device *netdev, u8 tc); 1396 void (*do_reset)(struct net_device *netdev); 1397 int (*ptp_setup_sdp)(struct wx *wx); 1398 void (*set_num_queues)(struct wx *wx); 1399 1400 bool pps_enabled; 1401 u64 pps_width; 1402 u64 pps_edge_start; 1403 u64 pps_edge_end; 1404 u64 sec_to_cc; 1405 u32 base_incval; 1406 u32 tx_hwtstamp_pkts; 1407 u32 tx_hwtstamp_timeouts; 1408 u32 tx_hwtstamp_skipped; 1409 u32 tx_hwtstamp_errors; 1410 u32 rx_hwtstamp_cleared; 1411 unsigned long last_overflow_check; 1412 unsigned long last_rx_ptp_check; 1413 unsigned long ptp_tx_start; 1414 seqlock_t hw_tc_lock; /* seqlock for ptp */ 1415 struct cyclecounter hw_cc; 1416 struct timecounter hw_tc; 1417 struct ptp_clock *ptp_clock; 1418 struct ptp_clock_info ptp_caps; 1419 struct kernel_hwtstamp_config tstamp_config; 1420 struct sk_buff *ptp_tx_skb; 1421 1422 struct timer_list service_timer; 1423 struct work_struct service_task; 1424 struct mutex reset_lock; /* mutex for reset */ 1425 }; 1426 1427 #define WX_INTR_ALL (~0ULL) 1428 #define WX_INTR_Q(i) BIT((i)) 1429 1430 /* register operations */ 1431 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) 1432 #define rd32(a, reg) readl((a)->hw_addr + (reg)) 1433 #define rd32a(a, reg, offset) ( \ 1434 rd32((a), (reg) + ((offset) << 2))) 1435 #define wr32a(a, reg, off, val) \ 1436 wr32((a), (reg) + ((off) << 2), (val)) 1437 1438 static inline u32 1439 rd32m(struct wx *wx, u32 reg, u32 mask) 1440 { 1441 u32 val; 1442 1443 val = rd32(wx, reg); 1444 return val & mask; 1445 } 1446 1447 static inline void 1448 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field) 1449 { 1450 u32 val; 1451 1452 val = rd32(wx, reg); 1453 val = ((val & ~mask) | (field & mask)); 1454 1455 wr32(wx, reg, val); 1456 } 1457 1458 static inline u64 1459 rd64(struct wx *wx, u32 reg) 1460 { 1461 u64 lsb, msb; 1462 1463 lsb = rd32(wx, reg); 1464 msb = rd32(wx, reg + 4); 1465 1466 return (lsb | msb << 32); 1467 } 1468 1469 static inline u32 1470 rd32ptp(struct wx *wx, u32 reg) 1471 { 1472 if (wx->mac.type == wx_mac_em) 1473 return rd32(wx, reg); 1474 1475 return rd32(wx, reg + 0xB500); 1476 } 1477 1478 static inline void 1479 wr32ptp(struct wx *wx, u32 reg, u32 value) 1480 { 1481 if (wx->mac.type == wx_mac_em) 1482 return wr32(wx, reg, value); 1483 1484 return wr32(wx, reg + 0xB500, value); 1485 } 1486 1487 static inline u32 1488 rd32_wrap(struct wx *wx, u32 reg, u32 *last) 1489 { 1490 u32 val, delta; 1491 1492 val = rd32(wx, reg); 1493 delta = val - *last; 1494 *last = val; 1495 1496 return delta; 1497 } 1498 1499 /* On some domestic CPU platforms, sometimes IO is not synchronized with 1500 * flushing memory, here use readl() to flush PCI read and write. 1501 */ 1502 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR) 1503 1504 #define wx_err(wx, fmt, arg...) \ 1505 dev_err(&(wx)->pdev->dev, fmt, ##arg) 1506 1507 #define wx_dbg(wx, fmt, arg...) \ 1508 dev_dbg(&(wx)->pdev->dev, fmt, ##arg) 1509 1510 static inline struct wx *phylink_to_wx(struct phylink_config *config) 1511 { 1512 return container_of(config, struct wx, phylink_config); 1513 } 1514 1515 static inline unsigned int wx_rx_pg_order(struct wx_ring *ring) 1516 { 1517 #if (PAGE_SIZE < 8192) 1518 if (ring->rx_buf_len == WX_RXBUFFER_3K) 1519 return 1; 1520 #endif 1521 return 0; 1522 } 1523 1524 #define wx_rx_pg_size(_ring) (PAGE_SIZE << wx_rx_pg_order(_ring)) 1525 1526 #endif /* _WX_TYPE_H_ */ 1527