1 /* 2 * linux/include/video/vga.h -- standard VGA chipset interaction 3 * 4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> 5 * 6 * Copyright history from vga16fb.c: 7 * Copyright 1999 Ben Pfaff and Petr Vandrovec 8 * Based on VGA info at http://www.osdever.net/FreeVGA/home.htm 9 * Based on VESA framebuffer (c) 1998 Gerd Knorr 10 * 11 * This file is subject to the terms and conditions of the GNU General 12 * Public License. See the file COPYING in the main directory of this 13 * archive for more details. 14 * 15 */ 16 17 #ifndef __linux_video_vga_h__ 18 #define __linux_video_vga_h__ 19 20 #include <linux/types.h> 21 #include <linux/io.h> 22 #include <asm/vga.h> 23 #include <asm/byteorder.h> 24 25 #define VGA_FB_PHYS_BASE 0xA0000 /* VGA framebuffer I/O base */ 26 #define VGA_FB_PHYS_SIZE 65536 /* VGA framebuffer I/O size */ 27 28 /* Some of the code below is taken from SVGAlib. The original, 29 unmodified copyright notice for that code is below. */ 30 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */ 31 /* */ 32 /* This library is free software; you can redistribute it and/or */ 33 /* modify it without any restrictions. This library is distributed */ 34 /* in the hope that it will be useful, but without any warranty. */ 35 36 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */ 37 /* partially copyrighted (C) 1993 by Hartmut Schirmer */ 38 39 /* VGA data register ports */ 40 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ 41 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ 42 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */ 43 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */ 44 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */ 45 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */ 46 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */ 47 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */ 48 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */ 49 #define VGA_IS0_R 0x3C2 /* Input Status Register 0 */ 50 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ 51 #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ 52 #define VGA_PEL_D 0x3C9 /* PEL Data Register */ 53 #define VGA_PEL_MSK 0x3C6 /* PEL mask register */ 54 55 /* EGA-specific registers */ 56 #define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */ 57 #define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */ 58 59 /* VGA index register ports */ 60 #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ 61 #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ 62 #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ 63 #define VGA_GFX_I 0x3CE /* Graphics Controller Index */ 64 #define VGA_SEQ_I 0x3C4 /* Sequencer Index */ 65 #define VGA_PEL_IW 0x3C8 /* PEL Write Index */ 66 #define VGA_PEL_IR 0x3C7 /* PEL Read Index */ 67 68 /* standard VGA indexes max counts */ 69 #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */ 70 #define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */ 71 #define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */ 72 #define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */ 73 #define VGA_MIS_C 0x01 /* Number of Misc Output Register */ 74 75 /* VGA misc register bit masks */ 76 #define VGA_MIS_COLOR 0x01 77 #define VGA_MIS_ENB_MEM_ACCESS 0x02 78 #define VGA_MIS_DCLK_28322_720 0x04 79 #define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08) 80 #define VGA_MIS_SEL_HIGH_PAGE 0x20 81 82 /* VGA CRT controller register indices */ 83 #define VGA_CRTC_H_TOTAL 0 84 #define VGA_CRTC_H_DISP 1 85 #define VGA_CRTC_H_BLANK_START 2 86 #define VGA_CRTC_H_BLANK_END 3 87 #define VGA_CRTC_H_SYNC_START 4 88 #define VGA_CRTC_H_SYNC_END 5 89 #define VGA_CRTC_V_TOTAL 6 90 #define VGA_CRTC_OVERFLOW 7 91 #define VGA_CRTC_PRESET_ROW 8 92 #define VGA_CRTC_MAX_SCAN 9 93 #define VGA_CRTC_CURSOR_START 0x0A 94 #define VGA_CRTC_CURSOR_END 0x0B 95 #define VGA_CRTC_START_HI 0x0C 96 #define VGA_CRTC_START_LO 0x0D 97 #define VGA_CRTC_CURSOR_HI 0x0E 98 #define VGA_CRTC_CURSOR_LO 0x0F 99 #define VGA_CRTC_V_SYNC_START 0x10 100 #define VGA_CRTC_V_SYNC_END 0x11 101 #define VGA_CRTC_V_DISP_END 0x12 102 #define VGA_CRTC_OFFSET 0x13 103 #define VGA_CRTC_UNDERLINE 0x14 104 #define VGA_CRTC_V_BLANK_START 0x15 105 #define VGA_CRTC_V_BLANK_END 0x16 106 #define VGA_CRTC_MODE 0x17 107 #define VGA_CRTC_LINE_COMPARE 0x18 108 #define VGA_CRTC_REGS VGA_CRT_C 109 110 /* VGA CRT controller bit masks */ 111 #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */ 112 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80 113 114 /* VGA attribute controller register indices */ 115 #define VGA_ATC_PALETTE0 0x00 116 #define VGA_ATC_PALETTE1 0x01 117 #define VGA_ATC_PALETTE2 0x02 118 #define VGA_ATC_PALETTE3 0x03 119 #define VGA_ATC_PALETTE4 0x04 120 #define VGA_ATC_PALETTE5 0x05 121 #define VGA_ATC_PALETTE6 0x06 122 #define VGA_ATC_PALETTE7 0x07 123 #define VGA_ATC_PALETTE8 0x08 124 #define VGA_ATC_PALETTE9 0x09 125 #define VGA_ATC_PALETTEA 0x0A 126 #define VGA_ATC_PALETTEB 0x0B 127 #define VGA_ATC_PALETTEC 0x0C 128 #define VGA_ATC_PALETTED 0x0D 129 #define VGA_ATC_PALETTEE 0x0E 130 #define VGA_ATC_PALETTEF 0x0F 131 #define VGA_ATC_MODE 0x10 132 #define VGA_ATC_OVERSCAN 0x11 133 #define VGA_ATC_PLANE_ENABLE 0x12 134 #define VGA_ATC_PEL 0x13 135 #define VGA_ATC_COLOR_PAGE 0x14 136 137 #define VGA_AR_ENABLE_DISPLAY 0x20 138 139 /* VGA sequencer register indices */ 140 #define VGA_SEQ_RESET 0x00 141 #define VGA_SEQ_CLOCK_MODE 0x01 142 #define VGA_SEQ_PLANE_WRITE 0x02 143 #define VGA_SEQ_CHARACTER_MAP 0x03 144 #define VGA_SEQ_MEMORY_MODE 0x04 145 146 /* VGA sequencer register bit masks */ 147 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */ 148 #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */ 149 #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */ 150 #define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */ 151 #define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */ 152 #define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */ 153 154 /* VGA graphics controller register indices */ 155 #define VGA_GFX_SR_VALUE 0x00 156 #define VGA_GFX_SR_ENABLE 0x01 157 #define VGA_GFX_COMPARE_VALUE 0x02 158 #define VGA_GFX_DATA_ROTATE 0x03 159 #define VGA_GFX_PLANE_READ 0x04 160 #define VGA_GFX_MODE 0x05 161 #define VGA_GFX_MISC 0x06 162 #define VGA_GFX_COMPARE_MASK 0x07 163 #define VGA_GFX_BIT_MASK 0x08 164 165 /* VGA graphics controller bit masks */ 166 #define VGA_GR06_GRAPHICS_MODE 0x01 167 168 /* macro for composing an 8-bit VGA register index and value 169 * into a single 16-bit quantity */ 170 #define VGA_OUT16VAL(v, r) (((v) << 8) | (r)) 171 172 /* decide whether we should enable the faster 16-bit VGA register writes */ 173 #ifdef __LITTLE_ENDIAN 174 #define VGA_OUTW_WRITE 175 #endif 176 177 /* VGA State Save and Restore */ 178 #define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */ 179 #define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */ 180 #define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */ 181 #define VGA_SAVE_FONTS 7 /* save/restore all fonts */ 182 #define VGA_SAVE_MODE 8 /* save/restore video mode */ 183 #define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */ 184 185 struct vgastate { 186 void __iomem *vgabase; /* mmio base, if supported */ 187 unsigned long membase; /* VGA window base, 0 for default - 0xA000 */ 188 __u32 memsize; /* VGA window size, 0 for default 64K */ 189 __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */ 190 __u32 depth; /* current fb depth, not important */ 191 __u32 num_attr; /* number of att registers, 0 for default */ 192 __u32 num_crtc; /* number of crt registers, 0 for default */ 193 __u32 num_gfx; /* number of gfx registers, 0 for default */ 194 __u32 num_seq; /* number of seq registers, 0 for default */ 195 void *vidstate; 196 }; 197 198 extern int save_vga(struct vgastate *state); 199 extern int restore_vga(struct vgastate *state); 200 201 static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port) 202 { 203 return readb (regbase + port); 204 } 205 206 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) 207 { 208 writeb (val, regbase + port); 209 } 210 211 static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port, 212 unsigned char reg, unsigned char val) 213 { 214 writew (VGA_OUT16VAL (val, reg), regbase + port); 215 } 216 217 /* 218 * generic VGA port read/write 219 */ 220 #ifdef CONFIG_HAS_IOPORT 221 222 static inline unsigned char vga_io_r (unsigned short port) 223 { 224 return inb_p(port); 225 } 226 227 static inline void vga_io_w (unsigned short port, unsigned char val) 228 { 229 outb_p(val, port); 230 } 231 232 static inline void vga_io_w_fast (unsigned short port, unsigned char reg, 233 unsigned char val) 234 { 235 outw(VGA_OUT16VAL (val, reg), port); 236 } 237 238 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) 239 { 240 if (regbase) 241 return vga_mm_r (regbase, port); 242 else 243 return vga_io_r (port); 244 } 245 246 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) 247 { 248 if (regbase) 249 vga_mm_w (regbase, port, val); 250 else 251 vga_io_w (port, val); 252 } 253 254 255 static inline void vga_w_fast (void __iomem *regbase, unsigned short port, 256 unsigned char reg, unsigned char val) 257 { 258 if (regbase) 259 vga_mm_w_fast (regbase, port, reg, val); 260 else 261 vga_io_w_fast (port, reg, val); 262 } 263 #else /* CONFIG_HAS_IOPORT */ 264 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) 265 { 266 return vga_mm_r (regbase, port); 267 } 268 269 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) 270 { 271 vga_mm_w (regbase, port, val); 272 } 273 274 275 static inline void vga_w_fast (void __iomem *regbase, unsigned short port, 276 unsigned char reg, unsigned char val) 277 { 278 vga_mm_w_fast (regbase, port, reg, val); 279 } 280 #endif /* CONFIG_HAS_IOPORT */ 281 282 /* 283 * VGA CRTC register read/write 284 */ 285 286 static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg) 287 { 288 vga_w (regbase, VGA_CRT_IC, reg); 289 return vga_r (regbase, VGA_CRT_DC); 290 } 291 292 static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) 293 { 294 #ifdef VGA_OUTW_WRITE 295 vga_w_fast (regbase, VGA_CRT_IC, reg, val); 296 #else 297 vga_w (regbase, VGA_CRT_IC, reg); 298 vga_w (regbase, VGA_CRT_DC, val); 299 #endif /* VGA_OUTW_WRITE */ 300 } 301 302 #ifdef CONFIG_HAS_IOPORT 303 static inline unsigned char vga_io_rcrt (unsigned char reg) 304 { 305 vga_io_w (VGA_CRT_IC, reg); 306 return vga_io_r (VGA_CRT_DC); 307 } 308 309 static inline void vga_io_wcrt (unsigned char reg, unsigned char val) 310 { 311 #ifdef VGA_OUTW_WRITE 312 vga_io_w_fast (VGA_CRT_IC, reg, val); 313 #else 314 vga_io_w (VGA_CRT_IC, reg); 315 vga_io_w (VGA_CRT_DC, val); 316 #endif /* VGA_OUTW_WRITE */ 317 } 318 #endif /* CONFIG_HAS_IOPORT */ 319 320 static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg) 321 { 322 vga_mm_w (regbase, VGA_CRT_IC, reg); 323 return vga_mm_r (regbase, VGA_CRT_DC); 324 } 325 326 static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) 327 { 328 #ifdef VGA_OUTW_WRITE 329 vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); 330 #else 331 vga_mm_w (regbase, VGA_CRT_IC, reg); 332 vga_mm_w (regbase, VGA_CRT_DC, val); 333 #endif /* VGA_OUTW_WRITE */ 334 } 335 336 337 /* 338 * VGA sequencer register read/write 339 */ 340 341 static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg) 342 { 343 vga_w (regbase, VGA_SEQ_I, reg); 344 return vga_r (regbase, VGA_SEQ_D); 345 } 346 347 static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) 348 { 349 #ifdef VGA_OUTW_WRITE 350 vga_w_fast (regbase, VGA_SEQ_I, reg, val); 351 #else 352 vga_w (regbase, VGA_SEQ_I, reg); 353 vga_w (regbase, VGA_SEQ_D, val); 354 #endif /* VGA_OUTW_WRITE */ 355 } 356 357 #ifdef CONFIG_HAS_IOPORT 358 static inline unsigned char vga_io_rseq (unsigned char reg) 359 { 360 vga_io_w (VGA_SEQ_I, reg); 361 return vga_io_r (VGA_SEQ_D); 362 } 363 364 static inline void vga_io_wseq (unsigned char reg, unsigned char val) 365 { 366 #ifdef VGA_OUTW_WRITE 367 vga_io_w_fast (VGA_SEQ_I, reg, val); 368 #else 369 vga_io_w (VGA_SEQ_I, reg); 370 vga_io_w (VGA_SEQ_D, val); 371 #endif /* VGA_OUTW_WRITE */ 372 } 373 #endif /* CONFIG_HAS_IOPORT */ 374 375 static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg) 376 { 377 vga_mm_w (regbase, VGA_SEQ_I, reg); 378 return vga_mm_r (regbase, VGA_SEQ_D); 379 } 380 381 static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) 382 { 383 #ifdef VGA_OUTW_WRITE 384 vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); 385 #else 386 vga_mm_w (regbase, VGA_SEQ_I, reg); 387 vga_mm_w (regbase, VGA_SEQ_D, val); 388 #endif /* VGA_OUTW_WRITE */ 389 } 390 391 /* 392 * VGA graphics controller register read/write 393 */ 394 395 static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg) 396 { 397 vga_w (regbase, VGA_GFX_I, reg); 398 return vga_r (regbase, VGA_GFX_D); 399 } 400 401 static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) 402 { 403 #ifdef VGA_OUTW_WRITE 404 vga_w_fast (regbase, VGA_GFX_I, reg, val); 405 #else 406 vga_w (regbase, VGA_GFX_I, reg); 407 vga_w (regbase, VGA_GFX_D, val); 408 #endif /* VGA_OUTW_WRITE */ 409 } 410 411 #ifdef CONFIG_HAS_IOPORT 412 static inline unsigned char vga_io_rgfx (unsigned char reg) 413 { 414 vga_io_w (VGA_GFX_I, reg); 415 return vga_io_r (VGA_GFX_D); 416 } 417 418 static inline void vga_io_wgfx (unsigned char reg, unsigned char val) 419 { 420 #ifdef VGA_OUTW_WRITE 421 vga_io_w_fast (VGA_GFX_I, reg, val); 422 #else 423 vga_io_w (VGA_GFX_I, reg); 424 vga_io_w (VGA_GFX_D, val); 425 #endif /* VGA_OUTW_WRITE */ 426 } 427 #endif /* CONFIG_HAS_IOPORT */ 428 429 static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg) 430 { 431 vga_mm_w (regbase, VGA_GFX_I, reg); 432 return vga_mm_r (regbase, VGA_GFX_D); 433 } 434 435 static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) 436 { 437 #ifdef VGA_OUTW_WRITE 438 vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); 439 #else 440 vga_mm_w (regbase, VGA_GFX_I, reg); 441 vga_mm_w (regbase, VGA_GFX_D, val); 442 #endif /* VGA_OUTW_WRITE */ 443 } 444 445 446 /* 447 * VGA attribute controller register read/write 448 */ 449 450 static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg) 451 { 452 vga_w (regbase, VGA_ATT_IW, reg); 453 return vga_r (regbase, VGA_ATT_R); 454 } 455 456 static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) 457 { 458 vga_w (regbase, VGA_ATT_IW, reg); 459 vga_w (regbase, VGA_ATT_W, val); 460 } 461 462 #ifdef CONFIG_HAS_IOPORT 463 static inline unsigned char vga_io_rattr (unsigned char reg) 464 { 465 vga_io_w (VGA_ATT_IW, reg); 466 return vga_io_r (VGA_ATT_R); 467 } 468 469 static inline void vga_io_wattr (unsigned char reg, unsigned char val) 470 { 471 vga_io_w (VGA_ATT_IW, reg); 472 vga_io_w (VGA_ATT_W, val); 473 } 474 #endif /* CONFIG_HAS_IOPORT */ 475 476 static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg) 477 { 478 vga_mm_w (regbase, VGA_ATT_IW, reg); 479 return vga_mm_r (regbase, VGA_ATT_R); 480 } 481 482 static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) 483 { 484 vga_mm_w (regbase, VGA_ATT_IW, reg); 485 vga_mm_w (regbase, VGA_ATT_W, val); 486 } 487 488 #endif /* __linux_video_vga_h__ */ 489