1 /* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License terms: GNU General Public License (GPL) version 2 5 */ 6 7 #ifndef __MACH_DB5500_REGS_H 8 #define __MACH_DB5500_REGS_H 9 10 #define U5500_PER1_BASE 0xA0020000 11 #define U5500_PER2_BASE 0xA0010000 12 #define U5500_PER3_BASE 0x80140000 13 #define U5500_PER4_BASE 0x80150000 14 #define U5500_PER5_BASE 0x80100000 15 #define U5500_PER6_BASE 0x80120000 16 17 #define U5500_GIC_DIST_BASE 0xA0411000 18 #define U5500_GIC_CPU_BASE 0xA0410100 19 #define U5500_DMA_BASE 0x90030000 20 #define U5500_STM_BASE 0x90020000 21 #define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000) 22 #define U5500_MCDE_BASE 0xA0400000 23 #define U5500_MODEM_BASE 0xB0000000 24 #define U5500_L2CC_BASE 0xA0412000 25 #define U5500_SCU_BASE 0xA0410000 26 #define U5500_DSI1_BASE 0xA0401000 27 #define U5500_DSI2_BASE 0xA0402000 28 #define U5500_SIA_BASE 0xA0100000 29 #define U5500_SVA_BASE 0x80200000 30 #define U5500_HSEM_BASE 0xA0000000 31 #define U5500_NAND0_BASE 0x60000000 32 #define U5500_NAND1_BASE 0x70000000 33 #define U5500_TWD_BASE 0xa0410600 34 #define U5500_ICN_BASE 0xA0040000 35 #define U5500_B2R2_BASE 0xa0200000 36 #define U5500_BOOT_ROM_BASE 0x90000000 37 38 #define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) 39 #define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) 40 #define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) 41 #define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) 42 #define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) 43 #define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) 44 #define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) 45 #define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) 46 47 #define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) 48 #define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) 49 #define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) 50 51 #define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) 52 #define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) 53 #define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) 54 #define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) 55 56 #define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) 57 #define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) 58 #define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) 59 #define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) 60 #define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) 61 #define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) 62 #define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) 63 #define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) 64 #define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) 65 #define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) 66 #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) 67 #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) 68 #define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000) 69 #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) 70 #define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) 71 #define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000) 72 #define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000) 73 74 #define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) 75 #define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) 76 #define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) 77 #define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) 78 #define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) 79 #define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) 80 #define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) 81 #define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) 82 #define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) 83 #define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) 84 #define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) 85 #define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) 86 #define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) 87 #define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) 88 #define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) 89 #define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) 90 #define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) 91 92 #define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) 93 #define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) 94 #define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) 95 #define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) 96 #define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100) 97 #define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) 98 #define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) 99 #define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) 100 #define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) 101 #define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) 102 #define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) 103 104 #define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE 105 #define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80) 106 #define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE 107 #define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE 108 #define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE 109 #define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE 110 #define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) 111 #define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) 112 113 #define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000) 114 #define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40) 115 #define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F) 116 #define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60) 117 #define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F) 118 #define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80) 119 #define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F) 120 #define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0) 121 #define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF) 122 #define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00) 123 #define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F) 124 #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) 125 #define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) 126 127 #define U5500_ACCCON_BASE_SEC (0xBFFF0000) 128 #define U5500_ACCCON_BASE (0xBFFF1000) 129 #define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) 130 #define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) 131 #define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4) 132 133 #define U5500_ESRAM_BASE 0x40000000 134 #define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 135 #define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) 136 137 #define U5500_MCDE_SIZE 0x1000 138 #define U5500_DSI_LINK_SIZE 0x1000 139 #define U5500_DSI_LINK_COUNT 0x2 140 #define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE) 141 #define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE) 142 143 #endif 144