1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _CORESIGHT_CORESIGHT_ETM_H
7 #define _CORESIGHT_CORESIGHT_ETM_H
8
9 #include <asm/local.h>
10 #include <linux/const.h>
11 #include <linux/spinlock.h>
12 #include <linux/types.h>
13 #include "coresight-priv.h"
14
15 /*
16 * Device registers:
17 * 0x000 - 0x2FC: Trace registers
18 * 0x300 - 0x314: Management registers
19 * 0x318 - 0xEFC: Trace registers
20 * 0xF00: Management registers
21 * 0xFA0 - 0xFA4: Trace registers
22 * 0xFA8 - 0xFFC: Management registers
23 */
24 /* Trace registers (0x000-0x2FC) */
25 /* Main control and configuration registers */
26 #define TRCPRGCTLR 0x004
27 #define TRCPROCSELR 0x008
28 #define TRCSTATR 0x00C
29 #define TRCCONFIGR 0x010
30 #define TRCAUXCTLR 0x018
31 #define TRCEVENTCTL0R 0x020
32 #define TRCEVENTCTL1R 0x024
33 #define TRCRSR 0x028
34 #define TRCSTALLCTLR 0x02C
35 #define TRCTSCTLR 0x030
36 #define TRCSYNCPR 0x034
37 #define TRCCCCTLR 0x038
38 #define TRCBBCTLR 0x03C
39 #define TRCTRACEIDR 0x040
40 #define TRCQCTLR 0x044
41 /* Filtering control registers */
42 #define TRCVICTLR 0x080
43 #define TRCVIIECTLR 0x084
44 #define TRCVISSCTLR 0x088
45 #define TRCVIPCSSCTLR 0x08C
46 /* Derived resources registers */
47 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */
48 #define TRCSEQRSTEVR 0x118
49 #define TRCSEQSTR 0x11C
50 #define TRCEXTINSELR 0x120
51 #define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */
52 #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */
53 #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */
54 #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */
55 /* ID registers */
56 #define TRCIDR8 0x180
57 #define TRCIDR9 0x184
58 #define TRCIDR10 0x188
59 #define TRCIDR11 0x18C
60 #define TRCIDR12 0x190
61 #define TRCIDR13 0x194
62 #define TRCIMSPEC0 0x1C0
63 #define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */
64 #define TRCIDR0 0x1E0
65 #define TRCIDR1 0x1E4
66 #define TRCIDR2 0x1E8
67 #define TRCIDR3 0x1EC
68 #define TRCIDR4 0x1F0
69 #define TRCIDR5 0x1F4
70 #define TRCIDR6 0x1F8
71 #define TRCIDR7 0x1FC
72 /*
73 * Resource selection registers, n = 2-31.
74 * First pair (regs 0, 1) is always present and is reserved.
75 */
76 #define TRCRSCTLRn(n) (0x200 + (n * 4))
77 /* Single-shot comparator registers, n = 0-7 */
78 #define TRCSSCCRn(n) (0x280 + (n * 4))
79 #define TRCSSCSRn(n) (0x2A0 + (n * 4))
80 #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
81 /* Management registers (0x300-0x314) */
82 #define TRCOSLAR 0x300
83 #define TRCOSLSR 0x304
84 #define TRCPDCR 0x310
85 #define TRCPDSR 0x314
86 /* Trace registers (0x318-0xEFC) */
87 /* Address Comparator registers n = 0-15 */
88 #define TRCACVRn(n) (0x400 + (n * 8))
89 #define TRCACATRn(n) (0x480 + (n * 8))
90 /* ContextID/Virtual ContextID comparators, n = 0-7 */
91 #define TRCCIDCVRn(n) (0x600 + (n * 8))
92 #define TRCVMIDCVRn(n) (0x640 + (n * 8))
93 #define TRCCIDCCTLR0 0x680
94 #define TRCCIDCCTLR1 0x684
95 #define TRCVMIDCCTLR0 0x688
96 #define TRCVMIDCCTLR1 0x68C
97 /* Management register (0xF00) */
98 /* Integration control registers */
99 #define TRCITCTRL 0xF00
100 /* Trace registers (0xFA0-0xFA4) */
101 /* Claim tag registers */
102 #define TRCCLAIMSET 0xFA0
103 #define TRCCLAIMCLR 0xFA4
104 /* Management registers (0xFA8-0xFFC) */
105 #define TRCDEVAFF0 0xFA8
106 #define TRCDEVAFF1 0xFAC
107 #define TRCLAR 0xFB0
108 #define TRCLSR 0xFB4
109 #define TRCAUTHSTATUS 0xFB8
110 #define TRCDEVARCH 0xFBC
111 #define TRCDEVID 0xFC8
112 #define TRCDEVTYPE 0xFCC
113 #define TRCPIDR4 0xFD0
114 #define TRCPIDR5 0xFD4
115 #define TRCPIDR6 0xFD8
116 #define TRCPIDR7 0xFDC
117 #define TRCPIDR0 0xFE0
118 #define TRCPIDR1 0xFE4
119 #define TRCPIDR2 0xFE8
120 #define TRCPIDR3 0xFEC
121 #define TRCCIDR0 0xFF0
122 #define TRCCIDR1 0xFF4
123 #define TRCCIDR2 0xFF8
124 #define TRCCIDR3 0xFFC
125
126 #define TRCRSR_TA BIT(12)
127
128 /*
129 * Bit positions of registers that are defined above, in the sysreg.h style
130 * of _MASK for multi bit fields and BIT() for single bits.
131 */
132 #define TRCIDR0_INSTP0_MASK GENMASK(2, 1)
133 #define TRCIDR0_TRCBB BIT(5)
134 #define TRCIDR0_TRCCOND BIT(6)
135 #define TRCIDR0_TRCCCI BIT(7)
136 #define TRCIDR0_RETSTACK BIT(9)
137 #define TRCIDR0_NUMEVENT_MASK GENMASK(11, 10)
138 #define TRCIDR0_QFILT BIT(14)
139 #define TRCIDR0_QSUPP_MASK GENMASK(16, 15)
140 #define TRCIDR0_TSSIZE_MASK GENMASK(28, 24)
141
142 #define TRCIDR2_CIDSIZE_MASK GENMASK(9, 5)
143 #define TRCIDR2_VMIDSIZE_MASK GENMASK(14, 10)
144 #define TRCIDR2_CCSIZE_MASK GENMASK(28, 25)
145
146 #define TRCIDR3_CCITMIN_MASK GENMASK(11, 0)
147 #define TRCIDR3_EXLEVEL_S_MASK GENMASK(19, 16)
148 #define TRCIDR3_EXLEVEL_NS_MASK GENMASK(23, 20)
149 #define TRCIDR3_TRCERR BIT(24)
150 #define TRCIDR3_SYNCPR BIT(25)
151 #define TRCIDR3_STALLCTL BIT(26)
152 #define TRCIDR3_SYSSTALL BIT(27)
153 #define TRCIDR3_NUMPROC_LO_MASK GENMASK(30, 28)
154 #define TRCIDR3_NUMPROC_HI_MASK GENMASK(13, 12)
155 #define TRCIDR3_NOOVERFLOW BIT(31)
156
157 #define TRCIDR4_NUMACPAIRS_MASK GENMASK(3, 0)
158 #define TRCIDR4_NUMPC_MASK GENMASK(15, 12)
159 #define TRCIDR4_NUMRSPAIR_MASK GENMASK(19, 16)
160 #define TRCIDR4_NUMSSCC_MASK GENMASK(23, 20)
161 #define TRCIDR4_NUMCIDC_MASK GENMASK(27, 24)
162 #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28)
163
164 #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0)
165 #define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9)
166 #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16)
167 #define TRCIDR5_ATBTRIG BIT(22)
168 #define TRCIDR5_LPOVERRIDE BIT(23)
169 #define TRCIDR5_NUMSEQSTATE_MASK GENMASK(27, 25)
170 #define TRCIDR5_NUMCNTR_MASK GENMASK(30, 28)
171
172 #define TRCCONFIGR_INSTP0_LOAD BIT(1)
173 #define TRCCONFIGR_INSTP0_STORE BIT(2)
174 #define TRCCONFIGR_INSTP0_LOAD_STORE (TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE)
175 #define TRCCONFIGR_BB BIT(3)
176 #define TRCCONFIGR_CCI BIT(4)
177 #define TRCCONFIGR_CID BIT(6)
178 #define TRCCONFIGR_VMID BIT(7)
179 #define TRCCONFIGR_COND_MASK GENMASK(10, 8)
180 #define TRCCONFIGR_TS BIT(11)
181 #define TRCCONFIGR_RS BIT(12)
182 #define TRCCONFIGR_QE_W_COUNTS BIT(13)
183 #define TRCCONFIGR_QE_WO_COUNTS BIT(14)
184 #define TRCCONFIGR_VMIDOPT BIT(15)
185 #define TRCCONFIGR_DA BIT(16)
186 #define TRCCONFIGR_DV BIT(17)
187
188 #define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0)
189 #define TRCEVENTCTL1R_INSTEN_0 BIT(0)
190 #define TRCEVENTCTL1R_INSTEN_1 BIT(1)
191 #define TRCEVENTCTL1R_INSTEN_2 BIT(2)
192 #define TRCEVENTCTL1R_INSTEN_3 BIT(3)
193 #define TRCEVENTCTL1R_ATB BIT(11)
194 #define TRCEVENTCTL1R_LPOVERRIDE BIT(12)
195
196 #define TRCSTALLCTLR_ISTALL BIT(8)
197 #define TRCSTALLCTLR_INSTPRIORITY BIT(10)
198 #define TRCSTALLCTLR_NOOVERFLOW BIT(13)
199
200 #define TRCVICTLR_EVENT_MASK GENMASK(7, 0)
201 #define TRCVICTLR_SSSTATUS BIT(9)
202 #define TRCVICTLR_TRCRESET BIT(10)
203 #define TRCVICTLR_TRCERR BIT(11)
204 #define TRCVICTLR_EXLEVEL_MASK GENMASK(22, 16)
205 #define TRCVICTLR_EXLEVEL_S_MASK GENMASK(19, 16)
206 #define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(22, 20)
207
208 #define TRCACATRn_TYPE_MASK GENMASK(1, 0)
209 #define TRCACATRn_CONTEXTTYPE_MASK GENMASK(3, 2)
210 #define TRCACATRn_CONTEXTTYPE_CTXID BIT(2)
211 #define TRCACATRn_CONTEXTTYPE_VMID BIT(3)
212 #define TRCACATRn_CONTEXT_MASK GENMASK(6, 4)
213 #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
214
215 #define TRCSSCSRn_STATUS BIT(31)
216 #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
217
218 #define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
219
220 #define TRCBBCTLR_MODE BIT(8)
221 #define TRCBBCTLR_RANGE_MASK GENMASK(7, 0)
222
223 #define TRCRSCTLRn_PAIRINV BIT(21)
224 #define TRCRSCTLRn_INV BIT(20)
225 #define TRCRSCTLRn_GROUP_MASK GENMASK(19, 16)
226 #define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0)
227
228 #define TRCCNTCTLRn_CNTCHAIN BIT(17)
229 #define TRCCNTCTLRn_RLDSELF BIT(16)
230 #define TRCCNTCTLRn_RLDEVENT_MASK GENMASK(15, 8)
231 #define TRCCNTCTLRn_CNTEVENT_MASK GENMASK(7, 0)
232
233 #define TRCTSCTLR_EVENT_MASK GENMASK(7, 0)
234
235 #define ETM4_RES_SEL_FALSE 0 /* Fixed function 'always false' resource selector */
236 #define ETM4_RES_SEL_TRUE 1 /* Fixed function 'always true' resource selector */
237
238 #define ETM4_RES_SEL_SINGLE_MASK GENMASK(4, 0)
239 #define ETM4_RES_SEL_PAIR_MASK GENMASK(3, 0)
240 #define ETM4_RES_SEL_TYPE_PAIR BIT(7)
241
242 /*
243 * Utilities for programming EVENT resource selectors, e.g. TRCCNTCTLRn_RLDEVENT.
244 *
245 * Resource selectors have a common format across registers:
246 *
247 * 7 6 5 4 0
248 * +------+------+-------+
249 * | TYPE | RES0 | SEL |
250 * +------+------+-------+
251 *
252 * Where TYPE indicates whether the selector is for a single event or a pair.
253 * When TYPE is pair, SEL is 4 bits wide and using pair 0 is UNPREDICTABLE.
254 * Otherwise for single it's 5 bits wide.
255 */
etm4_res_sel_single(u8 res_sel_idx)256 static inline u32 etm4_res_sel_single(u8 res_sel_idx)
257 {
258 WARN_ON_ONCE(!FIELD_FIT(ETM4_RES_SEL_SINGLE_MASK, res_sel_idx));
259 return FIELD_PREP(ETM4_RES_SEL_SINGLE_MASK, res_sel_idx);
260 }
261
etm4_res_sel_pair(u8 res_sel_idx)262 static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
263 {
264 if (__builtin_constant_p(res_sel_idx))
265 BUILD_BUG_ON(res_sel_idx == 0);
266 WARN_ON_ONCE(!FIELD_FIT(ETM4_RES_SEL_PAIR_MASK, res_sel_idx) ||
267 (res_sel_idx == 0));
268 return FIELD_PREP(ETM4_RES_SEL_PAIR_MASK, res_sel_idx) |
269 ETM4_RES_SEL_TYPE_PAIR;
270 }
271
272 /*
273 * System instructions to access ETM registers.
274 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
275 */
276 #define ETM4x_OFFSET_TO_REG(x) ((x) >> 2)
277
278 #define ETM4x_CRn(n) (((n) >> 7) & 0x7)
279 #define ETM4x_Op2(n) (((n) >> 4) & 0x7)
280 #define ETM4x_CRm(n) ((n) & 0xf)
281
282 #include <asm/sysreg.h>
283 #define ETM4x_REG_NUM_TO_SYSREG(n) \
284 sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n))
285
286 #define READ_ETM4x_REG(reg) \
287 read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg)))
288 #define WRITE_ETM4x_REG(val, reg) \
289 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
290
291 #define read_etm4x_sysreg_const_offset(offset) \
292 READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset))
293
294 #define write_etm4x_sysreg_const_offset(val, offset) \
295 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
296
297 #define CASE_READ(res, x) \
298 case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }
299
300 #define CASE_WRITE(val, x) \
301 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
302
303 #define CASE_NOP(__unused, x) \
304 case (x): /* fall through */
305
306 #define ETE_ONLY_SYSREG_LIST(op, val) \
307 CASE_##op((val), TRCRSR) \
308 CASE_##op((val), TRCEXTINSELRn(1)) \
309 CASE_##op((val), TRCEXTINSELRn(2)) \
310 CASE_##op((val), TRCEXTINSELRn(3))
311
312 /* List of registers accessible via System instructions */
313 #define ETM4x_ONLY_SYSREG_LIST(op, val) \
314 CASE_##op((val), TRCPROCSELR) \
315 CASE_##op((val), TRCOSLAR)
316
317 #define ETM_COMMON_SYSREG_LIST(op, val) \
318 CASE_##op((val), TRCPRGCTLR) \
319 CASE_##op((val), TRCSTATR) \
320 CASE_##op((val), TRCCONFIGR) \
321 CASE_##op((val), TRCAUXCTLR) \
322 CASE_##op((val), TRCEVENTCTL0R) \
323 CASE_##op((val), TRCEVENTCTL1R) \
324 CASE_##op((val), TRCSTALLCTLR) \
325 CASE_##op((val), TRCTSCTLR) \
326 CASE_##op((val), TRCSYNCPR) \
327 CASE_##op((val), TRCCCCTLR) \
328 CASE_##op((val), TRCBBCTLR) \
329 CASE_##op((val), TRCTRACEIDR) \
330 CASE_##op((val), TRCQCTLR) \
331 CASE_##op((val), TRCVICTLR) \
332 CASE_##op((val), TRCVIIECTLR) \
333 CASE_##op((val), TRCVISSCTLR) \
334 CASE_##op((val), TRCVIPCSSCTLR) \
335 CASE_##op((val), TRCSEQEVRn(0)) \
336 CASE_##op((val), TRCSEQEVRn(1)) \
337 CASE_##op((val), TRCSEQEVRn(2)) \
338 CASE_##op((val), TRCSEQRSTEVR) \
339 CASE_##op((val), TRCSEQSTR) \
340 CASE_##op((val), TRCEXTINSELR) \
341 CASE_##op((val), TRCCNTRLDVRn(0)) \
342 CASE_##op((val), TRCCNTRLDVRn(1)) \
343 CASE_##op((val), TRCCNTRLDVRn(2)) \
344 CASE_##op((val), TRCCNTRLDVRn(3)) \
345 CASE_##op((val), TRCCNTCTLRn(0)) \
346 CASE_##op((val), TRCCNTCTLRn(1)) \
347 CASE_##op((val), TRCCNTCTLRn(2)) \
348 CASE_##op((val), TRCCNTCTLRn(3)) \
349 CASE_##op((val), TRCCNTVRn(0)) \
350 CASE_##op((val), TRCCNTVRn(1)) \
351 CASE_##op((val), TRCCNTVRn(2)) \
352 CASE_##op((val), TRCCNTVRn(3)) \
353 CASE_##op((val), TRCIDR8) \
354 CASE_##op((val), TRCIDR9) \
355 CASE_##op((val), TRCIDR10) \
356 CASE_##op((val), TRCIDR11) \
357 CASE_##op((val), TRCIDR12) \
358 CASE_##op((val), TRCIDR13) \
359 CASE_##op((val), TRCIMSPECn(0)) \
360 CASE_##op((val), TRCIMSPECn(1)) \
361 CASE_##op((val), TRCIMSPECn(2)) \
362 CASE_##op((val), TRCIMSPECn(3)) \
363 CASE_##op((val), TRCIMSPECn(4)) \
364 CASE_##op((val), TRCIMSPECn(5)) \
365 CASE_##op((val), TRCIMSPECn(6)) \
366 CASE_##op((val), TRCIMSPECn(7)) \
367 CASE_##op((val), TRCIDR0) \
368 CASE_##op((val), TRCIDR1) \
369 CASE_##op((val), TRCIDR2) \
370 CASE_##op((val), TRCIDR3) \
371 CASE_##op((val), TRCIDR4) \
372 CASE_##op((val), TRCIDR5) \
373 CASE_##op((val), TRCIDR6) \
374 CASE_##op((val), TRCIDR7) \
375 CASE_##op((val), TRCRSCTLRn(2)) \
376 CASE_##op((val), TRCRSCTLRn(3)) \
377 CASE_##op((val), TRCRSCTLRn(4)) \
378 CASE_##op((val), TRCRSCTLRn(5)) \
379 CASE_##op((val), TRCRSCTLRn(6)) \
380 CASE_##op((val), TRCRSCTLRn(7)) \
381 CASE_##op((val), TRCRSCTLRn(8)) \
382 CASE_##op((val), TRCRSCTLRn(9)) \
383 CASE_##op((val), TRCRSCTLRn(10)) \
384 CASE_##op((val), TRCRSCTLRn(11)) \
385 CASE_##op((val), TRCRSCTLRn(12)) \
386 CASE_##op((val), TRCRSCTLRn(13)) \
387 CASE_##op((val), TRCRSCTLRn(14)) \
388 CASE_##op((val), TRCRSCTLRn(15)) \
389 CASE_##op((val), TRCRSCTLRn(16)) \
390 CASE_##op((val), TRCRSCTLRn(17)) \
391 CASE_##op((val), TRCRSCTLRn(18)) \
392 CASE_##op((val), TRCRSCTLRn(19)) \
393 CASE_##op((val), TRCRSCTLRn(20)) \
394 CASE_##op((val), TRCRSCTLRn(21)) \
395 CASE_##op((val), TRCRSCTLRn(22)) \
396 CASE_##op((val), TRCRSCTLRn(23)) \
397 CASE_##op((val), TRCRSCTLRn(24)) \
398 CASE_##op((val), TRCRSCTLRn(25)) \
399 CASE_##op((val), TRCRSCTLRn(26)) \
400 CASE_##op((val), TRCRSCTLRn(27)) \
401 CASE_##op((val), TRCRSCTLRn(28)) \
402 CASE_##op((val), TRCRSCTLRn(29)) \
403 CASE_##op((val), TRCRSCTLRn(30)) \
404 CASE_##op((val), TRCRSCTLRn(31)) \
405 CASE_##op((val), TRCSSCCRn(0)) \
406 CASE_##op((val), TRCSSCCRn(1)) \
407 CASE_##op((val), TRCSSCCRn(2)) \
408 CASE_##op((val), TRCSSCCRn(3)) \
409 CASE_##op((val), TRCSSCCRn(4)) \
410 CASE_##op((val), TRCSSCCRn(5)) \
411 CASE_##op((val), TRCSSCCRn(6)) \
412 CASE_##op((val), TRCSSCCRn(7)) \
413 CASE_##op((val), TRCSSCSRn(0)) \
414 CASE_##op((val), TRCSSCSRn(1)) \
415 CASE_##op((val), TRCSSCSRn(2)) \
416 CASE_##op((val), TRCSSCSRn(3)) \
417 CASE_##op((val), TRCSSCSRn(4)) \
418 CASE_##op((val), TRCSSCSRn(5)) \
419 CASE_##op((val), TRCSSCSRn(6)) \
420 CASE_##op((val), TRCSSCSRn(7)) \
421 CASE_##op((val), TRCSSPCICRn(0)) \
422 CASE_##op((val), TRCSSPCICRn(1)) \
423 CASE_##op((val), TRCSSPCICRn(2)) \
424 CASE_##op((val), TRCSSPCICRn(3)) \
425 CASE_##op((val), TRCSSPCICRn(4)) \
426 CASE_##op((val), TRCSSPCICRn(5)) \
427 CASE_##op((val), TRCSSPCICRn(6)) \
428 CASE_##op((val), TRCSSPCICRn(7)) \
429 CASE_##op((val), TRCOSLSR) \
430 CASE_##op((val), TRCACVRn(0)) \
431 CASE_##op((val), TRCACVRn(1)) \
432 CASE_##op((val), TRCACVRn(2)) \
433 CASE_##op((val), TRCACVRn(3)) \
434 CASE_##op((val), TRCACVRn(4)) \
435 CASE_##op((val), TRCACVRn(5)) \
436 CASE_##op((val), TRCACVRn(6)) \
437 CASE_##op((val), TRCACVRn(7)) \
438 CASE_##op((val), TRCACVRn(8)) \
439 CASE_##op((val), TRCACVRn(9)) \
440 CASE_##op((val), TRCACVRn(10)) \
441 CASE_##op((val), TRCACVRn(11)) \
442 CASE_##op((val), TRCACVRn(12)) \
443 CASE_##op((val), TRCACVRn(13)) \
444 CASE_##op((val), TRCACVRn(14)) \
445 CASE_##op((val), TRCACVRn(15)) \
446 CASE_##op((val), TRCACATRn(0)) \
447 CASE_##op((val), TRCACATRn(1)) \
448 CASE_##op((val), TRCACATRn(2)) \
449 CASE_##op((val), TRCACATRn(3)) \
450 CASE_##op((val), TRCACATRn(4)) \
451 CASE_##op((val), TRCACATRn(5)) \
452 CASE_##op((val), TRCACATRn(6)) \
453 CASE_##op((val), TRCACATRn(7)) \
454 CASE_##op((val), TRCACATRn(8)) \
455 CASE_##op((val), TRCACATRn(9)) \
456 CASE_##op((val), TRCACATRn(10)) \
457 CASE_##op((val), TRCACATRn(11)) \
458 CASE_##op((val), TRCACATRn(12)) \
459 CASE_##op((val), TRCACATRn(13)) \
460 CASE_##op((val), TRCACATRn(14)) \
461 CASE_##op((val), TRCACATRn(15)) \
462 CASE_##op((val), TRCCIDCVRn(0)) \
463 CASE_##op((val), TRCCIDCVRn(1)) \
464 CASE_##op((val), TRCCIDCVRn(2)) \
465 CASE_##op((val), TRCCIDCVRn(3)) \
466 CASE_##op((val), TRCCIDCVRn(4)) \
467 CASE_##op((val), TRCCIDCVRn(5)) \
468 CASE_##op((val), TRCCIDCVRn(6)) \
469 CASE_##op((val), TRCCIDCVRn(7)) \
470 CASE_##op((val), TRCVMIDCVRn(0)) \
471 CASE_##op((val), TRCVMIDCVRn(1)) \
472 CASE_##op((val), TRCVMIDCVRn(2)) \
473 CASE_##op((val), TRCVMIDCVRn(3)) \
474 CASE_##op((val), TRCVMIDCVRn(4)) \
475 CASE_##op((val), TRCVMIDCVRn(5)) \
476 CASE_##op((val), TRCVMIDCVRn(6)) \
477 CASE_##op((val), TRCVMIDCVRn(7)) \
478 CASE_##op((val), TRCCIDCCTLR0) \
479 CASE_##op((val), TRCCIDCCTLR1) \
480 CASE_##op((val), TRCVMIDCCTLR0) \
481 CASE_##op((val), TRCVMIDCCTLR1) \
482 CASE_##op((val), TRCCLAIMSET) \
483 CASE_##op((val), TRCCLAIMCLR) \
484 CASE_##op((val), TRCAUTHSTATUS) \
485 CASE_##op((val), TRCDEVARCH) \
486 CASE_##op((val), TRCDEVID)
487
488 /* List of registers only accessible via memory-mapped interface */
489 #define ETM_MMAP_LIST(op, val) \
490 CASE_##op((val), TRCDEVTYPE) \
491 CASE_##op((val), TRCPDCR) \
492 CASE_##op((val), TRCPDSR) \
493 CASE_##op((val), TRCDEVAFF0) \
494 CASE_##op((val), TRCDEVAFF1) \
495 CASE_##op((val), TRCLAR) \
496 CASE_##op((val), TRCLSR) \
497 CASE_##op((val), TRCITCTRL) \
498 CASE_##op((val), TRCPIDR4) \
499 CASE_##op((val), TRCPIDR0) \
500 CASE_##op((val), TRCPIDR1) \
501 CASE_##op((val), TRCPIDR2) \
502 CASE_##op((val), TRCPIDR3)
503
504 #define ETM4x_READ_SYSREG_CASES(res) \
505 ETM_COMMON_SYSREG_LIST(READ, (res)) \
506 ETM4x_ONLY_SYSREG_LIST(READ, (res))
507
508 #define ETM4x_WRITE_SYSREG_CASES(val) \
509 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
510 ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
511
512 #define ETM_COMMON_SYSREG_LIST_CASES \
513 ETM_COMMON_SYSREG_LIST(NOP, __unused)
514
515 #define ETM4x_ONLY_SYSREG_LIST_CASES \
516 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
517
518 #define ETM4x_SYSREG_LIST_CASES \
519 ETM_COMMON_SYSREG_LIST_CASES \
520 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
521
522 #define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused)
523
524 /* ETE only supports system register access */
525 #define ETE_READ_CASES(res) \
526 ETM_COMMON_SYSREG_LIST(READ, (res)) \
527 ETE_ONLY_SYSREG_LIST(READ, (res))
528
529 #define ETE_WRITE_CASES(val) \
530 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
531 ETE_ONLY_SYSREG_LIST(WRITE, (val))
532
533 #define ETE_ONLY_SYSREG_LIST_CASES \
534 ETE_ONLY_SYSREG_LIST(NOP, __unused)
535
536 #define read_etm4x_sysreg_offset(offset, _64bit) \
537 ({ \
538 u64 __val; \
539 \
540 if (__is_constexpr((offset))) \
541 __val = read_etm4x_sysreg_const_offset((offset)); \
542 else \
543 __val = etm4x_sysreg_read((offset), true, (_64bit)); \
544 __val; \
545 })
546
547 #define write_etm4x_sysreg_offset(val, offset, _64bit) \
548 do { \
549 if (__builtin_constant_p((offset))) \
550 write_etm4x_sysreg_const_offset((val), \
551 (offset)); \
552 else \
553 etm4x_sysreg_write((val), (offset), true, \
554 (_64bit)); \
555 } while (0)
556
557
558 #define etm4x_relaxed_read32(csa, offset) \
559 ((u32)((csa)->io_mem ? \
560 readl_relaxed((csa)->base + (offset)) : \
561 read_etm4x_sysreg_offset((offset), false)))
562
563 #define etm4x_relaxed_read64(csa, offset) \
564 ((u64)((csa)->io_mem ? \
565 readq_relaxed((csa)->base + (offset)) : \
566 read_etm4x_sysreg_offset((offset), true)))
567
568 #define etm4x_read32(csa, offset) \
569 ({ \
570 u32 __val = etm4x_relaxed_read32((csa), (offset)); \
571 __io_ar(__val); \
572 __val; \
573 })
574
575 #define etm4x_read64(csa, offset) \
576 ({ \
577 u64 __val = etm4x_relaxed_read64((csa), (offset)); \
578 __io_ar(__val); \
579 __val; \
580 })
581
582 #define etm4x_relaxed_write32(csa, val, offset) \
583 do { \
584 if ((csa)->io_mem) \
585 writel_relaxed((val), (csa)->base + (offset)); \
586 else \
587 write_etm4x_sysreg_offset((val), (offset), \
588 false); \
589 } while (0)
590
591 #define etm4x_relaxed_write64(csa, val, offset) \
592 do { \
593 if ((csa)->io_mem) \
594 writeq_relaxed((val), (csa)->base + (offset)); \
595 else \
596 write_etm4x_sysreg_offset((val), (offset), \
597 true); \
598 } while (0)
599
600 #define etm4x_write32(csa, val, offset) \
601 do { \
602 __io_bw(); \
603 etm4x_relaxed_write32((csa), (val), (offset)); \
604 } while (0)
605
606 #define etm4x_write64(csa, val, offset) \
607 do { \
608 __io_bw(); \
609 etm4x_relaxed_write64((csa), (val), (offset)); \
610 } while (0)
611
612
613 /* ETMv4 resources */
614 #define ETM_MAX_NR_PE 8
615 #define ETMv4_MAX_CNTR 4
616 #define ETM_MAX_SEQ_STATES 4
617 #define ETM_MAX_EXT_INP_SEL 4
618 #define ETM_MAX_EXT_INP 256
619 #define ETM_MAX_EXT_OUT 4
620 #define ETM_MAX_SINGLE_ADDR_CMP 16
621 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
622 #define ETM_MAX_DATA_VAL_CMP 8
623 #define ETMv4_MAX_CTXID_CMP 8
624 #define ETM_MAX_VMID_CMP 8
625 #define ETM_MAX_PE_CMP 8
626 #define ETM_MAX_RES_SEL 32
627 #define ETM_MAX_SS_CMP 8
628
629 #define ETMv4_SYNC_MASK 0x1F
630 #define ETM_CYC_THRESHOLD_MASK 0xFFF
631 #define ETM_CYC_THRESHOLD_DEFAULT 0x100
632 #define ETMv4_EVENT_MASK 0xFF
633 #define ETM_CNTR_MAX_VAL 0xFFFF
634 #define ETM_TRACEID_MASK 0x3f
635
636 /* ETMv4 programming modes */
637 #define ETM_MODE_EXCLUDE BIT(0)
638 #define ETM_MODE_LOAD BIT(1)
639 #define ETM_MODE_STORE BIT(2)
640 #define ETM_MODE_LOAD_STORE BIT(3)
641 #define ETM_MODE_BB BIT(4)
642 #define ETMv4_MODE_CYCACC BIT(5)
643 #define ETMv4_MODE_CTXID BIT(6)
644 #define ETM_MODE_VMID BIT(7)
645 #define ETM_MODE_COND(val) BMVAL(val, 8, 10)
646 #define ETMv4_MODE_TIMESTAMP BIT(11)
647 #define ETM_MODE_RETURNSTACK BIT(12)
648 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
649 #define ETM_MODE_DATA_TRACE_ADDR BIT(15)
650 #define ETM_MODE_DATA_TRACE_VAL BIT(16)
651 #define ETM_MODE_ISTALL BIT(17)
652 #define ETM_MODE_DSTALL BIT(18)
653 #define ETM_MODE_ATB_TRIGGER BIT(19)
654 #define ETM_MODE_LPOVERRIDE BIT(20)
655 #define ETM_MODE_ISTALL_EN BIT(21)
656 #define ETM_MODE_DSTALL_EN BIT(22)
657 #define ETM_MODE_INSTPRIO BIT(23)
658 #define ETM_MODE_NOOVERFLOW BIT(24)
659 #define ETM_MODE_TRACE_RESET BIT(25)
660 #define ETM_MODE_TRACE_ERR BIT(26)
661 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
662 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \
663 ETM_MODE_EXCL_KERN | \
664 ETM_MODE_EXCL_USER)
665
666 /*
667 * TRCOSLSR.OSLM advertises the OS Lock model.
668 * OSLM[2:0] = TRCOSLSR[4:3,0]
669 *
670 * 0b000 - Trace OS Lock is not implemented.
671 * 0b010 - Trace OS Lock is implemented.
672 * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
673 */
674 #define ETM_OSLOCK_NI 0b000
675 #define ETM_OSLOCK_PRESENT 0b010
676 #define ETM_OSLOCK_PE 0b100
677
678 #define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
679
680 /*
681 * TRCDEVARCH Bit field definitions
682 * Bits[31:21] - ARCHITECT = Always Arm Ltd.
683 * * Bits[31:28] = 0x4
684 * * Bits[27:21] = 0b0111011
685 * Bit[20] - PRESENT, Indicates the presence of this register.
686 *
687 * Bit[19:16] - REVISION, Revision of the architecture.
688 *
689 * Bit[15:0] - ARCHID, Identifies this component as an ETM
690 * * Bits[15:12] - architecture version of ETM
691 * * = 4 for ETMv4
692 * * Bits[11:0] = 0xA13, architecture part number for ETM.
693 */
694 #define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21)
695 #define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21))
696 #define ETM_DEVARCH_PRESENT BIT(20)
697 #define ETM_DEVARCH_REVISION_SHIFT 16
698 #define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16)
699 #define ETM_DEVARCH_REVISION(x) \
700 (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)
701 #define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0)
702 #define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12
703 #define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12)
704 #define ETM_DEVARCH_ARCHID_ARCH_VER(x) \
705 (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
706
707 #define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \
708 (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)
709
710 #define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL)
711
712 #define ETM_DEVARCH_MAKE_ARCHID(major) \
713 ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
714
715 #define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4)
716 #define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5)
717
718 #define ETM_DEVARCH_ID_MASK \
719 (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
720 #define ETM_DEVARCH_ETMv4x_ARCH \
721 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
722 #define ETM_DEVARCH_ETE_ARCH \
723 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
724
725 #define CS_DEVTYPE_PE_TRACE 0x00000013
726
727 #define TRCSTATR_IDLE_BIT 0
728 #define TRCSTATR_PMSTABLE_BIT 1
729 #define ETM_DEFAULT_ADDR_COMP 0
730
731 #define TRCSSCSRn_PC BIT(3)
732
733 /* PowerDown Control Register bits */
734 #define TRCPDCR_PU BIT(3)
735
736 #define TRCACATR_EXLEVEL_SHIFT 8
737
738 /*
739 * Exception level mask for Secure and Non-Secure ELs.
740 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
741 * The Secure and Non-Secure ELs are always to gether.
742 * Non-secure EL3 is never implemented.
743 * We use the following generic mask as they appear in different
744 * registers and this can be shifted for the appropriate
745 * fields.
746 */
747 #define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */
748 #define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */
749 #define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */
750 #define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */
751 #define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */
752 #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */
753 #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */
754
755 /* access level controls in TRCACATRn */
756 #define TRCACATR_EXLEVEL_SHIFT 8
757
758 #define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8
759 #define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
760 #define ETM_TRCIDR1_ARCH_MAJOR(x) \
761 (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
762 #define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4
763 #define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT)
764 #define ETM_TRCIDR1_ARCH_MINOR(x) \
765 (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT)
766 #define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT
767 #define ETM_TRCIDR1_ARCH_MASK \
768 (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK)
769
770 #define ETM_TRCIDR1_ARCH_ETMv4 0x4
771
772 /*
773 * Driver representation of the ETM architecture.
774 * The version of an ETM component can be detected from
775 *
776 * TRCDEVARCH - CoreSight architected register
777 * - Bits[15:12] - Major version
778 * - Bits[19:16] - Minor version
779 *
780 * We must rely only on TRCDEVARCH for the version information. Even though,
781 * TRCIDR1 also provides the architecture version, it is a "Trace" register
782 * and as such must be accessed only with Trace power domain ON. This may
783 * not be available at probe time.
784 *
785 * Now to make certain decisions easier based on the version
786 * we use an internal representation of the version in the
787 * driver, as follows :
788 *
789 * ETM_ARCH_VERSION[7:0], where :
790 * Bits[7:4] - Major version
791 * Bits[3:0] - Minro version
792 */
793 #define ETM_ARCH_VERSION(major, minor) \
794 ((((major) & 0xfU) << 4) | (((minor) & 0xfU)))
795 #define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU)
796 #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU)
797
798 #define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0)
799 #define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0)
800
801 /* Interpretation of resource numbers change at ETM v4.3 architecture */
802 #define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3)
803
etm_devarch_to_arch(u32 devarch)804 static inline u8 etm_devarch_to_arch(u32 devarch)
805 {
806 return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch),
807 ETM_DEVARCH_REVISION(devarch));
808 }
809
810 enum etm_impdef_type {
811 ETM4_IMPDEF_HISI_CORE_COMMIT,
812 ETM4_IMPDEF_FEATURE_MAX,
813 };
814
815 /**
816 * struct etmv4_config - configuration information related to an ETMv4
817 * @mode: Controls various modes supported by this ETM.
818 * @pe_sel: Controls which PE to trace.
819 * @cfg: Controls the tracing options.
820 * @eventctrl0: Controls the tracing of arbitrary events.
821 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
822 * @stallctl: If functionality that prevents trace unit buffer overflows
823 * is available.
824 * @ts_ctrl: Controls the insertion of global timestamps in the
825 * trace streams.
826 * @syncfreq: Controls how often trace synchronization requests occur.
827 * the TRCCCCTLR register.
828 * @ccctlr: Sets the threshold value for cycle counting.
829 * @vinst_ctrl: Controls instruction trace filtering.
830 * @viiectlr: Set or read, the address range comparators.
831 * @vissctlr: Set, or read, the single address comparators that control the
832 * ViewInst start-stop logic.
833 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
834 * ViewInst start-stop logic.
835 * @seq_idx: Sequencor index selector.
836 * @seq_ctrl: Control for the sequencer state transition control register.
837 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
838 * @seq_state: Set, or read the sequencer state.
839 * @cntr_idx: Counter index seletor.
840 * @cntrldvr: Sets or returns the reload count value for a counter.
841 * @cntr_ctrl: Controls the operation of a counter.
842 * @cntr_val: Sets or returns the value for a counter.
843 * @res_idx: Resource index selector.
844 * @res_ctrl: Controls the selection of the resources in the trace unit.
845 * @ss_idx: Single-shot index selector.
846 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
847 * @ss_status: The status of the corresponding single-shot comparator.
848 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
849 * @addr_idx: Address comparator index selector.
850 * @addr_val: Value for address comparator.
851 * @addr_acc: Address comparator access type.
852 * @addr_type: Current status of the comparator register.
853 * @ctxid_idx: Context ID index selector.
854 * @ctxid_pid: Value of the context ID comparator.
855 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
856 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
857 * @vmid_idx: VM ID index selector.
858 * @vmid_val: Value of the VM ID comparator.
859 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
860 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
861 * @ext_inp: External input selection.
862 * @s_ex_level: Secure ELs where tracing is supported.
863 */
864 struct etmv4_config {
865 u64 mode;
866 u32 pe_sel;
867 u32 cfg;
868 u32 eventctrl0;
869 u32 eventctrl1;
870 u32 stall_ctrl;
871 u32 ts_ctrl; /* TRCTSCTLR */
872 u32 ccctlr;
873 u32 bb_ctrl;
874 u32 vinst_ctrl;
875 u32 viiectlr;
876 u32 vissctlr;
877 u32 vipcssctlr;
878 u8 seq_idx;
879 u8 syncfreq;
880 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
881 u32 seq_rst;
882 u32 seq_state;
883 u8 cntr_idx;
884 u32 cntrldvr[ETMv4_MAX_CNTR]; /* TRCCNTRLDVRn */
885 u32 cntr_ctrl[ETMv4_MAX_CNTR]; /* TRCCNTCTLRn */
886 u32 cntr_val[ETMv4_MAX_CNTR]; /* TRCCNTVRn */
887 u8 res_idx;
888 u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */
889 u8 ss_idx;
890 u32 ss_ctrl[ETM_MAX_SS_CMP];
891 u32 ss_status[ETM_MAX_SS_CMP];
892 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
893 u8 addr_idx;
894 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
895 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
896 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
897 u8 ctxid_idx;
898 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
899 u32 ctxid_mask0;
900 u32 ctxid_mask1;
901 u8 vmid_idx;
902 u64 vmid_val[ETM_MAX_VMID_CMP];
903 u32 vmid_mask0;
904 u32 vmid_mask1;
905 u32 ext_inp;
906 u8 s_ex_level;
907 };
908
909 /**
910 * struct etm4_save_state - state to be preserved when ETM is without power
911 */
912 struct etmv4_save_state {
913 u32 trcprocselr;
914 u32 trcconfigr;
915 u32 trcauxctlr;
916 u32 trceventctl0r;
917 u32 trceventctl1r;
918 u32 trcstallctlr;
919 u32 trctsctlr;
920 u32 trcsyncpr;
921 u32 trcccctlr;
922 u32 trcbbctlr;
923 u32 trctraceidr;
924 u32 trcqctlr;
925
926 u32 trcvictlr;
927 u32 trcviiectlr;
928 u32 trcvissctlr;
929 u32 trcvipcssctlr;
930
931 u32 trcseqevr[ETM_MAX_SEQ_STATES];
932 u32 trcseqrstevr;
933 u32 trcseqstr;
934 u32 trcextinselr;
935 u32 trccntrldvr[ETMv4_MAX_CNTR];
936 u32 trccntctlr[ETMv4_MAX_CNTR];
937 u32 trccntvr[ETMv4_MAX_CNTR];
938
939 u32 trcrsctlr[ETM_MAX_RES_SEL];
940
941 u32 trcssccr[ETM_MAX_SS_CMP];
942 u32 trcsscsr[ETM_MAX_SS_CMP];
943 u32 trcsspcicr[ETM_MAX_SS_CMP];
944
945 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
946 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
947 u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
948 u64 trcvmidcvr[ETM_MAX_VMID_CMP];
949 u32 trccidcctlr0;
950 u32 trccidcctlr1;
951 u32 trcvmidcctlr0;
952 u32 trcvmidcctlr1;
953
954 u32 trcclaimset;
955
956 u32 cntr_val[ETMv4_MAX_CNTR];
957 u32 seq_state;
958 u32 vinst_ctrl;
959 u32 ss_status[ETM_MAX_SS_CMP];
960
961 u32 trcpdcr;
962 };
963
964 /**
965 * struct etm4_drvdata - specifics associated to an ETM component
966 * @pclk: APB clock if present, otherwise NULL
967 * @atclk: Optional clock for the core parts of the ETMv4.
968 * @base: Memory mapped base address for this component.
969 * @csdev: Component vitals needed by the framework.
970 * @spinlock: Only one at a time pls.
971 * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
972 * @cpu: The cpu this component is affined to.
973 * @arch: ETM architecture version.
974 * @nr_pe: The number of processing entity available for tracing.
975 * @nr_pe_cmp: The number of processing entity comparator inputs that are
976 * available for tracing.
977 * @nr_addr_cmp:Number of pairs of address comparators available
978 * as found in ETMIDR4 0-3.
979 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
980 * @nr_ext_inp: Number of external input.
981 * @numcidc: Number of contextID comparators.
982 * @numvmidc: Number of VMID comparators.
983 * @nrseqstate: The number of sequencer states that are implemented.
984 * @nr_event: Indicates how many events the trace unit support.
985 * @nr_resource:The number of resource selection pairs available for tracing.
986 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
987 * @trcid: value of the current ID for this component.
988 * @trcid_size: Indicates the trace ID width.
989 * @ts_size: Global timestamp size field.
990 * @ctxid_size: Size of the context ID field to consider.
991 * @vmid_size: Size of the VM ID comparator to consider.
992 * @ccsize: Indicates the size of the cycle counter in bits.
993 * @ccitmin: minimum value that can be programmed in
994 * @s_ex_level: In secure state, indicates whether instruction tracing is
995 * supported for the corresponding Exception level.
996 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
997 * supported for the corresponding Exception level.
998 * @sticky_enable: true if ETM base configuration has been done.
999 * @boot_enable:True if we should start tracing at boot time.
1000 * @os_unlock: True if access to management registers is allowed.
1001 * @instrp0: Tracing of load and store instructions
1002 * as P0 elements is supported.
1003 * @q_filt: Q element filtering support, if Q elements are supported.
1004 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
1005 * @trccond: If the trace unit supports conditional
1006 * instruction tracing.
1007 * @retstack: Indicates if the implementation supports a return stack.
1008 * @trccci: Indicates if the trace unit supports cycle counting
1009 * for instruction.
1010 * @q_support: Q element support characteristics.
1011 * @trc_error: Whether a trace unit can trace a system
1012 * error exception.
1013 * @syncpr: Indicates if an implementation has a fixed
1014 * synchronization period.
1015 * @stall_ctrl: Enables trace unit functionality that prevents trace
1016 * unit buffer overflows.
1017 * @sysstall: Does the system support stall control of the PE?
1018 * @nooverflow: Indicate if overflow prevention is supported.
1019 * @atbtrig: If the implementation can support ATB triggers
1020 * @lpoverride: If the implementation can support low-power state over.
1021 * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
1022 * allows tracing at all ELs. We don't want to compute this
1023 * at runtime, due to the additional setting of TRFCR_CX when
1024 * in EL2. Otherwise, 0.
1025 * @config: structure holding configuration parameters.
1026 * @save_state: State to be preserved across power loss
1027 * @skip_power_up: Indicates if an implementation can skip powering up
1028 * the trace unit.
1029 * @paused: Indicates if the trace unit is paused.
1030 * @arch_features: Bitmap of arch features of etmv4 devices.
1031 */
1032 struct etmv4_drvdata {
1033 struct clk *pclk;
1034 struct clk *atclk;
1035 void __iomem *base;
1036 struct coresight_device *csdev;
1037 raw_spinlock_t spinlock;
1038 int cpu;
1039 u8 arch;
1040 u8 nr_pe;
1041 u8 nr_pe_cmp;
1042 u8 nr_addr_cmp;
1043 u8 nr_cntr;
1044 u8 nr_ext_inp;
1045 u8 numcidc;
1046 u8 numextinsel;
1047 u8 numvmidc;
1048 u8 nrseqstate;
1049 u8 nr_event;
1050 u8 nr_resource;
1051 u8 nr_ss_cmp;
1052 u8 trcid;
1053 u8 trcid_size;
1054 u8 ts_size;
1055 u8 ctxid_size;
1056 u8 vmid_size;
1057 u8 ccsize;
1058 u16 ccitmin;
1059 u8 s_ex_level;
1060 u8 ns_ex_level;
1061 u8 q_support;
1062 u8 os_lock_model;
1063 bool sticky_enable : 1;
1064 bool boot_enable : 1;
1065 bool os_unlock : 1;
1066 bool instrp0 : 1;
1067 bool q_filt : 1;
1068 bool trcbb : 1;
1069 bool trccond : 1;
1070 bool retstack : 1;
1071 bool trccci : 1;
1072 bool trc_error : 1;
1073 bool syncpr : 1;
1074 bool stallctl : 1;
1075 bool sysstall : 1;
1076 bool nooverflow : 1;
1077 bool atbtrig : 1;
1078 bool lpoverride : 1;
1079 bool skip_power_up : 1;
1080 bool paused : 1;
1081 u64 trfcr;
1082 struct etmv4_config config;
1083 struct etmv4_save_state *save_state;
1084 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
1085 };
1086
1087 /* Address comparator access types */
1088 enum etm_addr_acctype {
1089 TRCACATRn_TYPE_ADDR,
1090 TRCACATRn_TYPE_DATA_LOAD_ADDR,
1091 TRCACATRn_TYPE_DATA_STORE_ADDR,
1092 TRCACATRn_TYPE_DATA_LOAD_STORE_ADDR,
1093 };
1094
1095 /* Address comparator context types */
1096 enum etm_addr_ctxtype {
1097 ETM_CTX_NONE,
1098 ETM_CTX_CTXID,
1099 ETM_CTX_VMID,
1100 ETM_CTX_CTXID_VMID,
1101 };
1102
1103 extern const struct attribute_group *coresight_etmv4_groups[];
1104 void etm4_config_trace_mode(struct etmv4_config *config);
1105
1106 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
1107 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
1108
etm4x_is_ete(struct etmv4_drvdata * drvdata)1109 static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
1110 {
1111 return drvdata->arch >= ETM_ARCH_ETE;
1112 }
1113
1114 void etm4_release_trace_id(struct etmv4_drvdata *drvdata);
1115 #endif
1116