1 /* 2 * TLB flags definition 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef TLB_FLAGS_H 20 #define TLB_FLAGS_H 21 22 /* 23 * Flags returned for lookup of a TLB virtual address. 24 */ 25 26 #ifdef CONFIG_USER_ONLY 27 28 /* 29 * Allow some level of source compatibility with softmmu. 30 * Invalid is set when the page does not have requested permissions. 31 * MMIO is set when we want the target helper to use the functional 32 * interface for load/store so that plugins see the access. 33 */ 34 #define TLB_INVALID_MASK (1 << 0) 35 #define TLB_MMIO (1 << 1) 36 #define TLB_WATCHPOINT 0 37 38 #else 39 40 /* 41 * Flags stored in CPUTLBEntryFull.slow_flags[x]. 42 * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. 43 */ 44 45 /* Set if TLB entry requires byte swap. */ 46 #define TLB_BSWAP (1 << 0) 47 /* Set if TLB entry contains a watchpoint. */ 48 #define TLB_WATCHPOINT (1 << 1) 49 /* Set if TLB entry requires aligned accesses. */ 50 #define TLB_CHECK_ALIGNED (1 << 2) 51 /* Set if TLB entry writes ignored. */ 52 #define TLB_DISCARD_WRITE (1 << 3) 53 /* Set if TLB entry is an IO callback. */ 54 #define TLB_MMIO (1 << 4) 55 56 #define TLB_SLOW_FLAGS_MASK \ 57 (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED | \ 58 TLB_DISCARD_WRITE | TLB_MMIO) 59 60 /* 61 * Flags stored in CPUTLBEntry.addr_idx[x]. 62 * These must be above the largest alignment (64 bytes), 63 * and below the smallest page size (1024 bytes). 64 * This leaves bits [9:6] available for use. 65 */ 66 67 /* Zero if TLB entry is valid. */ 68 #define TLB_INVALID_MASK (1 << 6) 69 /* Set if TLB entry references a clean RAM page. */ 70 #define TLB_NOTDIRTY (1 << 7) 71 /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ 72 #define TLB_FORCE_SLOW (1 << 8) 73 74 /* 75 * Use this mask to check interception with an alignment mask 76 * in a TCG backend. 77 */ 78 #define TLB_FLAGS_MASK \ 79 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_FORCE_SLOW) 80 81 /* The two sets of flags must not overlap. */ 82 QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); 83 84 #endif /* !CONFIG_USER_ONLY */ 85 86 #endif /* TLB_FLAGS_H */ 87