1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Header File to describe the DMA descriptors and related definitions specific 4 * for DesignWare databook 4.xx. 5 * 6 * Copyright (C) 2015 STMicroelectronics Ltd 7 * 8 * Author: Alexandre Torgue <alexandre.torgue@st.com> 9 */ 10 11 #ifndef __DWMAC4_DESCS_H__ 12 #define __DWMAC4_DESCS_H__ 13 14 #include <linux/bitops.h> 15 16 /* Normal transmit descriptor defines (without split feature) */ 17 18 /* TDES2 (read format) */ 19 #define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0) 20 #define TDES2_VLAN_TAG_MASK GENMASK(15, 14) 21 #define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16) 22 #define TDES3_IVTIR_MASK GENMASK(19, 18) 23 #define TDES3_IVLTV BIT(17) 24 #define TDES2_TIMESTAMP_ENABLE BIT(30) 25 #define TDES2_IVT_MASK GENMASK(31, 16) 26 #define TDES2_INTERRUPT_ON_COMPLETION BIT(31) 27 28 /* TDES3 (read format) */ 29 #define TDES3_PACKET_SIZE_MASK GENMASK(14, 0) 30 #define TDES3_VLAN_TAG GENMASK(15, 0) 31 #define TDES3_VLTV BIT(16) 32 #define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16) 33 #define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0) 34 #define TDES3_TCP_SEGMENTATION_ENABLE BIT(18) 35 #define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19) 36 #define TDES3_SA_INSERT_CTRL_MASK GENMASK(25, 23) 37 #define TDES3_CRC_PAD_CTRL_MASK GENMASK(27, 26) 38 39 /* TDES3 (write back format) */ 40 #define TDES3_IP_HDR_ERROR BIT(0) 41 #define TDES3_DEFERRED BIT(1) 42 #define TDES3_UNDERFLOW_ERROR BIT(2) 43 #define TDES3_EXCESSIVE_DEFERRAL BIT(3) 44 #define TDES3_COLLISION_COUNT_MASK GENMASK(7, 4) 45 #define TDES3_EXCESSIVE_COLLISION BIT(8) 46 #define TDES3_LATE_COLLISION BIT(9) 47 #define TDES3_NO_CARRIER BIT(10) 48 #define TDES3_LOSS_CARRIER BIT(11) 49 #define TDES3_PAYLOAD_ERROR BIT(12) 50 #define TDES3_PACKET_FLUSHED BIT(13) 51 #define TDES3_JABBER_TIMEOUT BIT(14) 52 #define TDES3_ERROR_SUMMARY BIT(15) 53 #define TDES3_TIMESTAMP_STATUS BIT(17) 54 #define TDES3_TIMESTAMP_STATUS_SHIFT 17 55 56 /* TDES3 context */ 57 #define TDES3_CTXT_TCMSSV BIT(26) 58 59 /* TDES3 Common */ 60 #define TDES3_RS1V BIT(26) 61 #define TDES3_RS1V_SHIFT 26 62 #define TDES3_LAST_DESCRIPTOR BIT(28) 63 #define TDES3_LAST_DESCRIPTOR_SHIFT 28 64 #define TDES3_FIRST_DESCRIPTOR BIT(29) 65 #define TDES3_CONTEXT_TYPE BIT(30) 66 #define TDES3_CONTEXT_TYPE_SHIFT 30 67 68 /* TDES4 */ 69 #define TDES4_LTV BIT(31) 70 #define TDES4_LT GENMASK(7, 0) 71 72 /* TDES5 */ 73 #define TDES5_LT GENMASK(31, 8) 74 75 /* TDS3 use for both format (read and write back) */ 76 #define TDES3_OWN BIT(31) 77 #define TDES3_OWN_SHIFT 31 78 79 /* Normal receive descriptor defines (without split feature) */ 80 81 /* RDES0 (write back format) */ 82 #define RDES0_VLAN_TAG_MASK GENMASK(15, 0) 83 84 /* RDES1 (write back format) */ 85 #define RDES1_IP_PAYLOAD_TYPE_MASK GENMASK(2, 0) 86 #define RDES1_IP_HDR_ERROR BIT(3) 87 #define RDES1_IPV4_HEADER BIT(4) 88 #define RDES1_IPV6_HEADER BIT(5) 89 #define RDES1_IP_CSUM_BYPASSED BIT(6) 90 #define RDES1_IP_PAYLOAD_ERROR BIT(7) 91 #define RDES1_PTP_MSG_TYPE_MASK GENMASK(11, 8) 92 #define RDES1_PTP_PACKET_TYPE BIT(12) 93 #define RDES1_PTP_VER BIT(13) 94 #define RDES1_TIMESTAMP_AVAILABLE BIT(14) 95 #define RDES1_TIMESTAMP_AVAILABLE_SHIFT 14 96 #define RDES1_TIMESTAMP_DROPPED BIT(15) 97 #define RDES1_IP_TYPE1_CSUM_MASK GENMASK(31, 16) 98 99 /* RDES2 (write back format) */ 100 #define RDES2_L3_L4_HEADER_SIZE_MASK GENMASK(9, 0) 101 #define RDES2_VLAN_FILTER_STATUS BIT(15) 102 #define RDES2_SA_FILTER_FAIL BIT(16) 103 #define RDES2_DA_FILTER_FAIL BIT(17) 104 #define RDES2_HASH_FILTER_STATUS BIT(18) 105 #define RDES2_MAC_ADDR_MATCH_MASK GENMASK(26, 19) 106 #define RDES2_HASH_VALUE_MATCH_MASK GENMASK(26, 19) 107 #define RDES2_L3_FILTER_MATCH BIT(27) 108 #define RDES2_L4_FILTER_MATCH BIT(28) 109 #define RDES2_L3_L4_FILT_NB_MATCH_MASK GENMASK(27, 26) 110 #define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26 111 #define RDES2_HL GENMASK(9, 0) 112 113 /* RDES3 (write back format) */ 114 #define RDES3_PACKET_SIZE_MASK GENMASK(14, 0) 115 #define RDES3_ERROR_SUMMARY BIT(15) 116 #define RDES3_PACKET_LEN_TYPE_MASK GENMASK(18, 16) 117 #define RDES3_DRIBBLE_ERROR BIT(19) 118 #define RDES3_RECEIVE_ERROR BIT(20) 119 #define RDES3_OVERFLOW_ERROR BIT(21) 120 #define RDES3_RECEIVE_WATCHDOG BIT(22) 121 #define RDES3_GIANT_PACKET BIT(23) 122 #define RDES3_CRC_ERROR BIT(24) 123 #define RDES3_RDES0_VALID BIT(25) 124 #define RDES3_RDES1_VALID BIT(26) 125 #define RDES3_RDES2_VALID BIT(27) 126 #define RDES3_LAST_DESCRIPTOR BIT(28) 127 #define RDES3_FIRST_DESCRIPTOR BIT(29) 128 #define RDES3_CONTEXT_DESCRIPTOR BIT(30) 129 #define RDES3_CONTEXT_DESCRIPTOR_SHIFT 30 130 131 /* RDES3 (read format) */ 132 #define RDES3_BUFFER1_VALID_ADDR BIT(24) 133 #define RDES3_BUFFER2_VALID_ADDR BIT(25) 134 #define RDES3_INT_ON_COMPLETION_EN BIT(30) 135 136 /* TDS3 use for both format (read and write back) */ 137 #define RDES3_OWN BIT(31) 138 139 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; 140 extern const struct stmmac_desc_ops dwmac4_desc_ops; 141 142 #endif /* __DWMAC4_DESCS_H__ */ 143