1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015-2017 Google, Inc 4 * 5 * USB Type-C Port Controller Interface. 6 */ 7 8 #ifndef __LINUX_USB_TCPCI_H 9 #define __LINUX_USB_TCPCI_H 10 11 #define TCPC_VENDOR_ID 0x0 12 #define TCPC_PRODUCT_ID 0x2 13 #define TCPC_BCD_DEV 0x4 14 #define TCPC_TC_REV 0x6 15 #define TCPC_PD_REV 0x8 16 #define TCPC_PD_INT_REV 0xa 17 18 #define TCPC_ALERT 0x10 19 #define TCPC_ALERT_EXTND BIT(14) 20 #define TCPC_ALERT_EXTENDED_STATUS BIT(13) 21 #define TCPC_ALERT_VBUS_DISCNCT BIT(11) 22 #define TCPC_ALERT_RX_BUF_OVF BIT(10) 23 #define TCPC_ALERT_FAULT BIT(9) 24 #define TCPC_ALERT_V_ALARM_LO BIT(8) 25 #define TCPC_ALERT_V_ALARM_HI BIT(7) 26 #define TCPC_ALERT_TX_SUCCESS BIT(6) 27 #define TCPC_ALERT_TX_DISCARDED BIT(5) 28 #define TCPC_ALERT_TX_FAILED BIT(4) 29 #define TCPC_ALERT_RX_HARD_RST BIT(3) 30 #define TCPC_ALERT_RX_STATUS BIT(2) 31 #define TCPC_ALERT_POWER_STATUS BIT(1) 32 #define TCPC_ALERT_CC_STATUS BIT(0) 33 34 #define TCPC_ALERT_MASK 0x12 35 #define TCPC_POWER_STATUS_MASK 0x14 36 #define TCPC_FAULT_STATUS_MASK 0x15 37 38 #define TCPC_EXTENDED_STATUS_MASK 0x16 39 #define TCPC_EXTENDED_STATUS_MASK_VSAFE0V BIT(0) 40 41 #define TCPC_ALERT_EXTENDED_MASK 0x17 42 #define TCPC_SINK_FAST_ROLE_SWAP BIT(0) 43 44 #define TCPC_CONFIG_STD_OUTPUT 0x18 45 46 #define TCPC_TCPC_CTRL 0x19 47 #define TCPC_TCPC_CTRL_ORIENTATION BIT(0) 48 #define TCPC_TCPC_CTRL_BIST_TM BIT(1) 49 50 #define TCPC_ROLE_CTRL 0x1a 51 #define TCPC_ROLE_CTRL_DRP BIT(6) 52 #define TCPC_ROLE_CTRL_RP_VAL_SHIFT 4 53 #define TCPC_ROLE_CTRL_RP_VAL_MASK 0x3 54 #define TCPC_ROLE_CTRL_RP_VAL_DEF 0x0 55 #define TCPC_ROLE_CTRL_RP_VAL_1_5 0x1 56 #define TCPC_ROLE_CTRL_RP_VAL_3_0 0x2 57 #define TCPC_ROLE_CTRL_CC2_SHIFT 2 58 #define TCPC_ROLE_CTRL_CC2_MASK 0x3 59 #define TCPC_ROLE_CTRL_CC1_SHIFT 0 60 #define TCPC_ROLE_CTRL_CC1_MASK 0x3 61 #define TCPC_ROLE_CTRL_CC_RA 0x0 62 #define TCPC_ROLE_CTRL_CC_RP 0x1 63 #define TCPC_ROLE_CTRL_CC_RD 0x2 64 #define TCPC_ROLE_CTRL_CC_OPEN 0x3 65 66 #define TCPC_FAULT_CTRL 0x1b 67 68 #define TCPC_POWER_CTRL 0x1c 69 #define TCPC_POWER_CTRL_VCONN_ENABLE BIT(0) 70 #define TCPC_FAST_ROLE_SWAP_EN BIT(7) 71 72 #define TCPC_CC_STATUS 0x1d 73 #define TCPC_CC_STATUS_TOGGLING BIT(5) 74 #define TCPC_CC_STATUS_TERM BIT(4) 75 #define TCPC_CC_STATUS_CC2_SHIFT 2 76 #define TCPC_CC_STATUS_CC2_MASK 0x3 77 #define TCPC_CC_STATUS_CC1_SHIFT 0 78 #define TCPC_CC_STATUS_CC1_MASK 0x3 79 80 #define TCPC_POWER_STATUS 0x1e 81 #define TCPC_POWER_STATUS_UNINIT BIT(6) 82 #define TCPC_POWER_STATUS_SOURCING_VBUS BIT(4) 83 #define TCPC_POWER_STATUS_VBUS_DET BIT(3) 84 #define TCPC_POWER_STATUS_VBUS_PRES BIT(2) 85 86 #define TCPC_FAULT_STATUS 0x1f 87 88 #define TCPC_ALERT_EXTENDED 0x21 89 90 #define TCPC_COMMAND 0x23 91 #define TCPC_CMD_WAKE_I2C 0x11 92 #define TCPC_CMD_DISABLE_VBUS_DETECT 0x22 93 #define TCPC_CMD_ENABLE_VBUS_DETECT 0x33 94 #define TCPC_CMD_DISABLE_SINK_VBUS 0x44 95 #define TCPC_CMD_SINK_VBUS 0x55 96 #define TCPC_CMD_DISABLE_SRC_VBUS 0x66 97 #define TCPC_CMD_SRC_VBUS_DEFAULT 0x77 98 #define TCPC_CMD_SRC_VBUS_HIGH 0x88 99 #define TCPC_CMD_LOOK4CONNECTION 0x99 100 #define TCPC_CMD_RXONEMORE 0xAA 101 #define TCPC_CMD_I2C_IDLE 0xFF 102 103 #define TCPC_DEV_CAP_1 0x24 104 #define TCPC_DEV_CAP_2 0x26 105 #define TCPC_STD_INPUT_CAP 0x28 106 #define TCPC_STD_OUTPUT_CAP 0x29 107 108 #define TCPC_MSG_HDR_INFO 0x2e 109 #define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3) 110 #define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0) 111 #define TCPC_MSG_HDR_INFO_REV_SHIFT 1 112 #define TCPC_MSG_HDR_INFO_REV_MASK 0x3 113 114 #define TCPC_RX_DETECT 0x2f 115 #define TCPC_RX_DETECT_HARD_RESET BIT(5) 116 #define TCPC_RX_DETECT_SOP BIT(0) 117 118 #define TCPC_RX_BYTE_CNT 0x30 119 #define TCPC_RX_BUF_FRAME_TYPE 0x31 120 #define TCPC_RX_BUF_FRAME_TYPE_SOP 0 121 #define TCPC_RX_HDR 0x32 122 #define TCPC_RX_DATA 0x34 /* through 0x4f */ 123 124 #define TCPC_TRANSMIT 0x50 125 #define TCPC_TRANSMIT_RETRY_SHIFT 4 126 #define TCPC_TRANSMIT_RETRY_MASK 0x3 127 #define TCPC_TRANSMIT_TYPE_SHIFT 0 128 #define TCPC_TRANSMIT_TYPE_MASK 0x7 129 130 #define TCPC_TX_BYTE_CNT 0x51 131 #define TCPC_TX_HDR 0x52 132 #define TCPC_TX_DATA 0x54 /* through 0x6f */ 133 134 #define TCPC_VBUS_VOLTAGE 0x70 135 #define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72 136 #define TCPC_VBUS_STOP_DISCHARGE_THRESH 0x74 137 #define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 138 #define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 139 140 /* I2C_WRITE_BYTE_COUNT + 1 when TX_BUF_BYTE_x is only accessible I2C_WRITE_BYTE_COUNT */ 141 #define TCPC_TRANSMIT_BUFFER_MAX_LEN 31 142 143 /* 144 * @TX_BUF_BYTE_x_hidden 145 * optional; Set when TX_BUF_BYTE_x can only be accessed through I2C_WRITE_BYTE_COUNT. 146 */ 147 struct tcpci; 148 struct tcpci_data { 149 struct regmap *regmap; 150 unsigned char TX_BUF_BYTE_x_hidden:1; 151 int (*init)(struct tcpci *tcpci, struct tcpci_data *data); 152 int (*set_vconn)(struct tcpci *tcpci, struct tcpci_data *data, 153 bool enable); 154 int (*start_drp_toggling)(struct tcpci *tcpci, struct tcpci_data *data, 155 enum typec_cc_status cc); 156 int (*set_vbus)(struct tcpci *tcpci, struct tcpci_data *data, bool source, bool sink); 157 }; 158 159 struct tcpci *tcpci_register_port(struct device *dev, struct tcpci_data *data); 160 void tcpci_unregister_port(struct tcpci *tcpci); 161 irqreturn_t tcpci_irq(struct tcpci *tcpci); 162 163 struct tcpm_port; 164 struct tcpm_port *tcpci_get_tcpm_port(struct tcpci *tcpci); 165 #endif /* __LINUX_USB_TCPCI_H */ 166