1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #ifndef R8190P_DEF_H 8 #define R8190P_DEF_H 9 10 #include <linux/types.h> 11 12 #define MAX_SILENT_RESET_RX_SLOT_NUM 10 13 14 enum rtl819x_loopback { 15 RTL819X_NO_LOOPBACK = 0, 16 RTL819X_MAC_LOOPBACK = 1, 17 RTL819X_DMA_LOOPBACK = 2, 18 RTL819X_CCK_LOOPBACK = 3, 19 }; 20 21 #define DESC90_RATE1M 0x00 22 #define DESC90_RATE2M 0x01 23 #define DESC90_RATE5_5M 0x02 24 #define DESC90_RATE11M 0x03 25 #define DESC90_RATE6M 0x04 26 #define DESC90_RATE9M 0x05 27 #define DESC90_RATE12M 0x06 28 #define DESC90_RATE18M 0x07 29 #define DESC90_RATE24M 0x08 30 #define DESC90_RATE36M 0x09 31 #define DESC90_RATE48M 0x0a 32 #define DESC90_RATE54M 0x0b 33 #define DESC90_RATEMCS0 0x00 34 #define DESC90_RATEMCS1 0x01 35 #define DESC90_RATEMCS2 0x02 36 #define DESC90_RATEMCS3 0x03 37 #define DESC90_RATEMCS4 0x04 38 #define DESC90_RATEMCS5 0x05 39 #define DESC90_RATEMCS6 0x06 40 #define DESC90_RATEMCS7 0x07 41 #define DESC90_RATEMCS8 0x08 42 #define DESC90_RATEMCS9 0x09 43 #define DESC90_RATEMCS10 0x0a 44 #define DESC90_RATEMCS11 0x0b 45 #define DESC90_RATEMCS12 0x0c 46 #define DESC90_RATEMCS13 0x0d 47 #define DESC90_RATEMCS14 0x0e 48 #define DESC90_RATEMCS15 0x0f 49 #define DESC90_RATEMCS32 0x20 50 51 #define SHORT_SLOT_TIME 9 52 #define NON_SHORT_SLOT_TIME 20 53 54 #define RX_SMOOTH 20 55 56 #define QSLT_BK 0x1 57 #define QSLT_BE 0x0 58 #define QSLT_VI 0x4 59 #define QSLT_VO 0x6 60 #define QSLT_BEACON 0x10 61 #define QSLT_HIGH 0x11 62 #define QSLT_MGNT 0x12 63 #define QSLT_CMD 0x13 64 65 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007 66 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa 67 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024 68 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007 69 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10 70 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 71 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd 72 73 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 74 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 75 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 76 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 77 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 78 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 79 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 80 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 81 82 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 83 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 84 #define HAL_PRIME_CHNL_OFFSET_UPPER 2 85 86 enum version_8190_loopback { 87 VERSION_8190_BD = 0x3, 88 VERSION_8190_BE 89 }; 90 91 #define IC_VersionCut_C 0x2 92 #define IC_VersionCut_D 0x3 93 #define IC_VersionCut_E 0x4 94 95 enum rf_optype { 96 RF_OP_By_SW_3wire = 0, 97 RF_OP_By_FW, 98 RF_OP_MAX 99 }; 100 101 struct bb_reg_definition { 102 u32 rfintfs; 103 u32 rfintfo; 104 u32 rfintfe; 105 u32 rf3wireOffset; 106 u32 rfHSSIPara2; 107 u32 rfLSSIReadBack; 108 u32 rfLSSIReadBackPi; 109 }; 110 111 struct tx_fwinfo_8190pci { 112 u8 TxRate:7; 113 u8 CtsEnable:1; 114 u8 RtsRate:7; 115 u8 RtsEnable:1; 116 u8 TxHT:1; 117 u8 Short:1; 118 u8 TxBandwidth:1; 119 u8 TxSubCarrier:2; 120 u8 STBC:2; 121 u8 AllowAggregation:1; 122 u8 RtsHT:1; 123 u8 RtsShort:1; 124 u8 RtsBandwidth:1; 125 u8 RtsSubcarrier:2; 126 u8 RtsSTBC:2; 127 u8 EnableCPUDur:1; 128 129 u32 RxMF:2; 130 u32 RxAMD:3; 131 u32 TxPerPktInfoFeedback:1; 132 u32 Reserved1:2; 133 u32 TxAGCOffset:4; 134 u32 TxAGCSign:1; 135 u32 RAW_TXD:1; 136 u32 Retry_Limit:4; 137 u32 Reserved2:1; 138 u32 PacketID:13; 139 }; 140 141 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag { 142 u8 reserved:4; 143 u8 rxsc:2; 144 u8 sgi_en:1; 145 u8 ex_intf_flag:1; 146 }; 147 148 struct phy_sts_ofdm_819xpci { 149 u8 trsw_gain_X[4]; 150 u8 pwdb_all; 151 u8 cfosho_X[4]; 152 u8 cfotail_X[4]; 153 u8 rxevm_X[2]; 154 u8 rxsnr_X[4]; 155 u8 pdsnr_X[2]; 156 u8 csi_current_X[2]; 157 u8 csi_target_X[2]; 158 u8 sigevm; 159 u8 max_ex_pwr; 160 u8 sgi_en; 161 u8 rxsc_sgien_exflg; 162 }; 163 164 struct phy_sts_cck_819xpci { 165 u8 adc_pwdb_X[4]; 166 u8 sq_rpt; 167 u8 cck_agc_rpt; 168 }; 169 170 #define PHY_RSSI_SLID_WIN_MAX 100 171 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 172 173 struct tx_desc { 174 u16 PktSize; 175 u8 Offset; 176 u8 Reserved1:3; 177 u8 CmdInit:1; 178 u8 LastSeg:1; 179 u8 FirstSeg:1; 180 u8 LINIP:1; 181 u8 OWN:1; 182 183 u8 TxFWInfoSize; 184 u8 RATid:3; 185 u8 DISFB:1; 186 u8 USERATE:1; 187 u8 MOREFRAG:1; 188 u8 NoEnc:1; 189 u8 PIFS:1; 190 u8 QueueSelect:5; 191 u8 NoACM:1; 192 u8 Resv:2; 193 u8 SecCAMID:5; 194 u8 SecDescAssign:1; 195 u8 SecType:2; 196 197 u16 TxBufferSize; 198 u8 PktId:7; 199 u8 Resv1:1; 200 u8 Reserved2; 201 202 u32 TxBuffAddr; 203 204 u32 NextDescAddress; 205 206 u32 Reserved5; 207 u32 Reserved6; 208 u32 Reserved7; 209 }; 210 211 struct tx_desc_cmd { 212 u16 PktSize; 213 u8 Reserved1; 214 u8 CmdType:3; 215 u8 CmdInit:1; 216 u8 LastSeg:1; 217 u8 FirstSeg:1; 218 u8 LINIP:1; 219 u8 OWN:1; 220 221 u16 ElementReport; 222 u16 Reserved2; 223 224 u16 TxBufferSize; 225 u16 Reserved3; 226 227 u32 TxBuffAddr; 228 u32 NextDescAddress; 229 u32 Reserved4; 230 u32 Reserved5; 231 u32 Reserved6; 232 }; 233 234 struct rx_desc { 235 u16 Length:14; 236 u16 CRC32:1; 237 u16 ICV:1; 238 u8 RxDrvInfoSize; 239 u8 Shift:2; 240 u8 PHYStatus:1; 241 u8 SWDec:1; 242 u8 LastSeg:1; 243 u8 FirstSeg:1; 244 u8 EOR:1; 245 u8 OWN:1; 246 247 u32 Reserved2; 248 249 u32 Reserved3; 250 251 u32 BufferAddress; 252 }; 253 254 struct rx_fwinfo { 255 u16 Reserved1:12; 256 u16 PartAggr:1; 257 u16 FirstAGGR:1; 258 u16 Reserved2:2; 259 260 u8 RxRate:7; 261 u8 RxHT:1; 262 263 u8 BW:1; 264 u8 SPLCP:1; 265 u8 Reserved3:2; 266 u8 PAM:1; 267 u8 Mcast:1; 268 u8 Bcast:1; 269 u8 Reserved4:1; 270 271 u32 TSFL; 272 }; 273 274 #endif 275