1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2012-15 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DAL_AMDGPU_DM_MST_TYPES_H__ 28 #define __DAL_AMDGPU_DM_MST_TYPES_H__ 29 30 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24 31 32 #define SYNAPTICS_RC_COMMAND 0x4B2 33 #define SYNAPTICS_RC_RESULT 0x4B3 34 #define SYNAPTICS_RC_LENGTH 0x4B8 35 #define SYNAPTICS_RC_OFFSET 0x4BC 36 #define SYNAPTICS_RC_DATA 0x4C0 37 38 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C 39 40 /** 41 * Panamera MST Hub detection 42 * Offset DPCD 050Eh == 0x5A indicates cascaded MST hub case 43 * Check from beginning of branch device vendor specific field (050Ch) 44 */ 45 #define IS_SYNAPTICS_PANAMERA(branchDevName) (((int)branchDevName[4] & 0xF0) == 0x50 ? 1 : 0) 46 #define BRANCH_HW_REVISION_PANAMERA_A2 0x10 47 #define SYNAPTICS_CASCADED_HUB_ID 0x5A 48 #define IS_SYNAPTICS_CASCADED_PANAMERA(devName, data) ((IS_SYNAPTICS_PANAMERA(devName) && ((int)data[2] == SYNAPTICS_CASCADED_HUB_ID)) ? 1 : 0) 49 50 #define PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B 1031 51 #define PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B 1000 52 53 enum mst_msg_ready_type { 54 NONE_MSG_RDY_EVENT = 0, 55 DOWN_REP_MSG_RDY_EVENT = 1, 56 UP_REQ_MSG_RDY_EVENT = 2, 57 DOWN_OR_UP_MSG_RDY_EVENT = 3 58 }; 59 60 struct amdgpu_display_manager; 61 struct amdgpu_dm_connector; 62 63 uint32_t dm_mst_get_pbn_divider(struct dc_link *link); 64 65 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 66 struct amdgpu_dm_connector *aconnector, 67 int link_index); 68 69 void 70 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev); 71 72 void dm_handle_mst_sideband_msg_ready_event( 73 struct drm_dp_mst_topology_mgr *mgr, 74 enum mst_msg_ready_type msg_rdy_type); 75 76 struct dsc_mst_fairness_vars { 77 int pbn; 78 bool dsc_enabled; 79 int bpp_x16; 80 struct amdgpu_dm_connector *aconnector; 81 }; 82 83 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 84 struct dc_state *dc_state, 85 struct dsc_mst_fairness_vars *vars); 86 87 bool needs_dsc_aux_workaround(struct dc_link *link); 88 89 int pre_validate_dsc(struct drm_atomic_state *state, 90 struct dm_atomic_state **dm_state_ptr, 91 struct dsc_mst_fairness_vars *vars); 92 93 enum dc_status dm_dp_mst_is_port_support_mode( 94 struct amdgpu_dm_connector *aconnector, 95 struct dc_stream_state *stream); 96 97 #endif 98