1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2025 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phy.h> 15 #include <linux/regmap.h> 16 #include <net/dsa.h> 17 #include <linux/irq.h> 18 #include <linux/platform_data/microchip-ksz.h> 19 20 #include "ksz_ptp.h" 21 22 #define KSZ_MAX_NUM_PORTS 8 23 /* all KSZ switches count ports from 1 */ 24 #define KSZ_PORT_1 0 25 #define KSZ_PORT_2 1 26 #define KSZ_PORT_4 3 27 28 struct ksz_device; 29 struct ksz_port; 30 struct phylink_mac_ops; 31 32 enum ksz_regmap_width { 33 KSZ_REGMAP_8, 34 KSZ_REGMAP_16, 35 KSZ_REGMAP_32, 36 __KSZ_NUM_REGMAPS, 37 }; 38 39 struct vlan_table { 40 u32 table[3]; 41 }; 42 43 struct ksz_port_mib { 44 struct mutex cnt_mutex; /* structure access */ 45 u8 cnt_ptr; 46 u64 *counters; 47 struct rtnl_link_stats64 stats64; 48 struct ethtool_pause_stats pause_stats; 49 struct spinlock stats64_lock; 50 }; 51 52 struct ksz_mib_names { 53 int index; 54 char string[ETH_GSTRING_LEN]; 55 }; 56 57 struct ksz_chip_data { 58 u32 chip_id; 59 const char *dev_name; 60 int num_vlans; 61 int num_alus; 62 int num_statics; 63 int cpu_ports; 64 int port_cnt; 65 u8 port_nirqs; 66 u8 num_tx_queues; 67 u8 num_ipms; /* number of Internal Priority Maps */ 68 bool tc_cbs_supported; 69 70 /** 71 * @phy_side_mdio_supported: Indicates if the chip supports an additional 72 * side MDIO channel for accessing integrated PHYs. 73 */ 74 bool phy_side_mdio_supported; 75 const struct ksz_dev_ops *ops; 76 const struct phylink_mac_ops *phylink_mac_ops; 77 bool phy_errata_9477; 78 bool ksz87xx_eee_link_erratum; 79 const struct ksz_mib_names *mib_names; 80 int mib_cnt; 81 u8 reg_mib_cnt; 82 const u16 *regs; 83 const u32 *masks; 84 const u8 *shifts; 85 const u8 *xmii_ctrl0; 86 const u8 *xmii_ctrl1; 87 int stp_ctrl_reg; 88 int broadcast_ctrl_reg; 89 int multicast_ctrl_reg; 90 int start_ctrl_reg; 91 bool supports_mii[KSZ_MAX_NUM_PORTS]; 92 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 93 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 94 bool internal_phy[KSZ_MAX_NUM_PORTS]; 95 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 96 bool ptp_capable; 97 u8 sgmii_port; 98 const struct regmap_access_table *wr_table; 99 const struct regmap_access_table *rd_table; 100 }; 101 102 struct ksz_irq { 103 u16 masked; 104 u16 reg_mask; 105 u16 reg_status; 106 struct irq_domain *domain; 107 int nirqs; 108 int irq_num; 109 char name[16]; 110 struct ksz_device *dev; 111 u16 irq0_offset; 112 }; 113 114 struct ksz_ptp_irq { 115 struct ksz_port *port; 116 u16 ts_reg; 117 bool ts_en; 118 char name[16]; 119 int num; 120 }; 121 122 struct ksz_switch_macaddr { 123 unsigned char addr[ETH_ALEN]; 124 refcount_t refcount; 125 }; 126 127 struct ksz_port { 128 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 129 bool learning; 130 bool isolated; 131 int stp_state; 132 int speed; 133 int duplex; 134 bool link; 135 136 u32 fiber:1; /* port is fiber */ 137 u32 force:1; 138 u32 read:1; /* read MIB counters in background */ 139 u32 freeze:1; /* MIB counter freeze is enabled */ 140 u32 sgmii_adv_write:1; 141 142 struct ksz_port_mib mib; 143 phy_interface_t interface; 144 u32 rgmii_tx_val; 145 u32 rgmii_rx_val; 146 struct ksz_device *ksz_dev; 147 void *acl_priv; 148 struct ksz_irq pirq; 149 u8 num; 150 struct phylink_pcs *pcs; 151 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 152 struct kernel_hwtstamp_config tstamp_config; 153 bool hwts_tx_en; 154 bool hwts_rx_en; 155 struct ksz_irq ptpirq; 156 struct ksz_ptp_irq ptpmsg_irq[3]; 157 ktime_t tstamp_msg; 158 struct completion tstamp_msg_comp; 159 #endif 160 bool manual_flow; 161 }; 162 163 struct ksz_device { 164 struct dsa_switch *ds; 165 struct ksz_platform_data *pdata; 166 const struct ksz_chip_data *info; 167 168 struct mutex dev_mutex; /* device access */ 169 struct mutex regmap_mutex; /* regmap access */ 170 struct mutex alu_mutex; /* ALU access */ 171 struct mutex vlan_mutex; /* vlan access */ 172 const struct ksz_dev_ops *dev_ops; 173 174 struct device *dev; 175 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 176 177 void *priv; 178 int irq; 179 180 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 181 182 /* chip specific data */ 183 u32 chip_id; 184 u8 chip_rev; 185 int cpu_port; /* port connected to CPU */ 186 int phy_port_cnt; 187 phy_interface_t compat_interface; 188 bool synclko_125; 189 bool synclko_disable; 190 bool wakeup_source; 191 bool pme_active_high; 192 193 struct vlan_table *vlan_cache; 194 195 struct ksz_port *ports; 196 struct delayed_work mib_read; 197 unsigned long mib_read_interval; 198 u16 mirror_rx; 199 u16 mirror_tx; 200 u16 port_mask; 201 struct mutex lock_irq; /* IRQ Access */ 202 struct ksz_irq girq; 203 struct ksz_ptp_data ptp_data; 204 205 struct ksz_switch_macaddr *switch_macaddr; 206 struct net_device *hsr_dev; /* HSR */ 207 u8 hsr_ports; 208 209 /** 210 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 211 * addresses. 212 */ 213 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 214 215 /** 216 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 217 * 218 * This points to an external MDIO bus controller that is used to access 219 * the PHYs integrated within the switch. Unlike an integrated MDIO 220 * bus, this external controller provides a direct path for managing 221 * the switch’s internal PHYs, bypassing the main SPI interface. 222 */ 223 struct mii_bus *parent_mdio_bus; 224 }; 225 226 /* List of supported models */ 227 enum ksz_model { 228 KSZ8463, 229 KSZ8563, 230 KSZ8567, 231 KSZ8795, 232 KSZ8794, 233 KSZ8765, 234 KSZ88X3, 235 KSZ8864, 236 KSZ8895, 237 KSZ9477, 238 KSZ9896, 239 KSZ9897, 240 KSZ9893, 241 KSZ9563, 242 KSZ9567, 243 LAN9370, 244 LAN9371, 245 LAN9372, 246 LAN9373, 247 LAN9374, 248 LAN9646, 249 }; 250 251 enum ksz_regs { 252 REG_SW_MAC_ADDR, 253 REG_IND_CTRL_0, 254 REG_IND_DATA_8, 255 REG_IND_DATA_CHECK, 256 REG_IND_DATA_HI, 257 REG_IND_DATA_LO, 258 REG_IND_MIB_CHECK, 259 REG_IND_BYTE, 260 P_FORCE_CTRL, 261 P_LINK_STATUS, 262 P_LOCAL_CTRL, 263 P_NEG_RESTART_CTRL, 264 P_REMOTE_STATUS, 265 P_SPEED_STATUS, 266 S_TAIL_TAG_CTRL, 267 P_STP_CTRL, 268 S_START_CTRL, 269 S_BROADCAST_CTRL, 270 S_MULTICAST_CTRL, 271 P_XMII_CTRL_0, 272 P_XMII_CTRL_1, 273 REG_SW_PME_CTRL, 274 REG_PORT_PME_STATUS, 275 REG_PORT_PME_CTRL, 276 PTP_CLK_CTRL, 277 PTP_RTC_NANOSEC, 278 PTP_RTC_SEC, 279 PTP_RTC_SUB_NANOSEC, 280 PTP_SUBNANOSEC_RATE, 281 PTP_MSG_CONF1, 282 }; 283 284 enum ksz_masks { 285 PORT_802_1P_REMAPPING, 286 SW_TAIL_TAG_ENABLE, 287 MIB_COUNTER_OVERFLOW, 288 MIB_COUNTER_VALID, 289 VLAN_TABLE_FID, 290 VLAN_TABLE_MEMBERSHIP, 291 VLAN_TABLE_VALID, 292 STATIC_MAC_TABLE_VALID, 293 STATIC_MAC_TABLE_USE_FID, 294 STATIC_MAC_TABLE_FID, 295 STATIC_MAC_TABLE_OVERRIDE, 296 STATIC_MAC_TABLE_FWD_PORTS, 297 DYNAMIC_MAC_TABLE_ENTRIES_H, 298 DYNAMIC_MAC_TABLE_MAC_EMPTY, 299 DYNAMIC_MAC_TABLE_NOT_READY, 300 DYNAMIC_MAC_TABLE_ENTRIES, 301 DYNAMIC_MAC_TABLE_FID, 302 DYNAMIC_MAC_TABLE_SRC_PORT, 303 DYNAMIC_MAC_TABLE_TIMESTAMP, 304 ALU_STAT_WRITE, 305 ALU_STAT_READ, 306 ALU_STAT_DIRECT, 307 ALU_RESV_MCAST_ADDR, 308 P_MII_TX_FLOW_CTRL, 309 P_MII_RX_FLOW_CTRL, 310 }; 311 312 enum ksz_shifts { 313 VLAN_TABLE_MEMBERSHIP_S, 314 VLAN_TABLE, 315 STATIC_MAC_FWD_PORTS, 316 STATIC_MAC_FID, 317 DYNAMIC_MAC_ENTRIES_H, 318 DYNAMIC_MAC_ENTRIES, 319 DYNAMIC_MAC_FID, 320 DYNAMIC_MAC_TIMESTAMP, 321 DYNAMIC_MAC_SRC_PORT, 322 ALU_STAT_INDEX, 323 }; 324 325 enum ksz_xmii_ctrl0 { 326 P_MII_100MBIT, 327 P_MII_10MBIT, 328 P_MII_FULL_DUPLEX, 329 P_MII_HALF_DUPLEX, 330 }; 331 332 enum ksz_xmii_ctrl1 { 333 P_RGMII_SEL, 334 P_RMII_SEL, 335 P_GMII_SEL, 336 P_MII_SEL, 337 P_GMII_1GBIT, 338 P_GMII_NOT_1GBIT, 339 }; 340 341 struct alu_struct { 342 /* entry 1 */ 343 u8 is_static:1; 344 u8 is_src_filter:1; 345 u8 is_dst_filter:1; 346 u8 prio_age:3; 347 u32 _reserv_0_1:23; 348 u8 mstp:3; 349 /* entry 2 */ 350 u8 is_override:1; 351 u8 is_use_fid:1; 352 u32 _reserv_1_1:23; 353 u8 port_forward:7; 354 /* entry 3 & 4*/ 355 u32 _reserv_2_1:9; 356 u8 fid:7; 357 u8 mac[ETH_ALEN]; 358 }; 359 360 struct ksz_dev_ops { 361 int (*setup)(struct dsa_switch *ds); 362 void (*teardown)(struct dsa_switch *ds); 363 u32 (*get_port_addr)(int port, int offset); 364 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 365 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 366 void (*port_cleanup)(struct ksz_device *dev, int port); 367 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 368 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 369 370 /** 371 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 372 * for accessing PHYs. 373 * @dev: Pointer to device structure. 374 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 375 * MDIO bus. 376 * 377 * This function pointer is used to configure the MDIO bus for PHY 378 * access before initiating regular PHY operations. It enables either 379 * SPI/I2C or side MDIO access modes by unlocking necessary registers 380 * and setting up access permissions for the selected mode. 381 * 382 * Return: 383 * - 0 on success. 384 * - Negative error code on failure. 385 */ 386 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 387 388 /** 389 * @create_phy_addr_map: Function pointer to create a port-to-PHY 390 * address map. 391 * @dev: Pointer to device structure. 392 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 393 * MDIO bus. 394 * 395 * This function pointer is responsible for mapping switch ports to PHY 396 * addresses according to the configured access mode (SPI or side MDIO) 397 * and the device’s strap configuration. The mapping setup may vary 398 * depending on the chip variant and configuration. Ensures the correct 399 * address mapping for PHY communication. 400 * 401 * Return: 402 * - 0 on success. 403 * - Negative error code on failure (e.g., invalid configuration). 404 */ 405 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 406 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 407 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 408 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 409 u64 *cnt); 410 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 411 u64 *dropped, u64 *cnt); 412 void (*r_mib_stat64)(struct ksz_device *dev, int port); 413 int (*vlan_filtering)(struct ksz_device *dev, int port, 414 bool flag, struct netlink_ext_ack *extack); 415 int (*vlan_add)(struct ksz_device *dev, int port, 416 const struct switchdev_obj_port_vlan *vlan, 417 struct netlink_ext_ack *extack); 418 int (*vlan_del)(struct ksz_device *dev, int port, 419 const struct switchdev_obj_port_vlan *vlan); 420 int (*mirror_add)(struct ksz_device *dev, int port, 421 struct dsa_mall_mirror_tc_entry *mirror, 422 bool ingress, struct netlink_ext_ack *extack); 423 void (*mirror_del)(struct ksz_device *dev, int port, 424 struct dsa_mall_mirror_tc_entry *mirror); 425 int (*fdb_add)(struct ksz_device *dev, int port, 426 const unsigned char *addr, u16 vid, struct dsa_db db); 427 int (*fdb_del)(struct ksz_device *dev, int port, 428 const unsigned char *addr, u16 vid, struct dsa_db db); 429 int (*fdb_dump)(struct ksz_device *dev, int port, 430 dsa_fdb_dump_cb_t *cb, void *data); 431 int (*mdb_add)(struct ksz_device *dev, int port, 432 const struct switchdev_obj_port_mdb *mdb, 433 struct dsa_db db); 434 int (*mdb_del)(struct ksz_device *dev, int port, 435 const struct switchdev_obj_port_mdb *mdb, 436 struct dsa_db db); 437 void (*get_caps)(struct ksz_device *dev, int port, 438 struct phylink_config *config); 439 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 440 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 441 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 442 u8 *data); 443 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 444 u8 data); 445 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 446 void (*port_init_cnt)(struct ksz_device *dev, int port); 447 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 448 unsigned int mode, 449 phy_interface_t interface, 450 struct phy_device *phydev, int speed, 451 int duplex, bool tx_pause, bool rx_pause); 452 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 453 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 454 void (*config_cpu_port)(struct dsa_switch *ds); 455 int (*enable_stp_addr)(struct ksz_device *dev); 456 int (*reset)(struct ksz_device *dev); 457 int (*init)(struct ksz_device *dev); 458 void (*exit)(struct ksz_device *dev); 459 460 int (*pcs_create)(struct ksz_device *dev); 461 }; 462 463 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 464 int ksz_switch_register(struct ksz_device *dev); 465 void ksz_switch_remove(struct ksz_device *dev); 466 int ksz_switch_suspend(struct device *dev); 467 int ksz_switch_resume(struct device *dev); 468 469 void ksz_init_mib_timer(struct ksz_device *dev); 470 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 471 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 472 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 473 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 474 bool ksz_get_gbit(struct ksz_device *dev, int port); 475 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 476 extern const struct ksz_chip_data ksz_switch_chips[]; 477 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 478 struct netlink_ext_ack *extack); 479 void ksz_switch_macaddr_put(struct dsa_switch *ds); 480 void ksz_switch_shutdown(struct ksz_device *dev); 481 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 482 483 /* Common register access functions */ 484 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 485 { 486 return dev->regmap[KSZ_REGMAP_8]; 487 } 488 489 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 490 { 491 return dev->regmap[KSZ_REGMAP_16]; 492 } 493 494 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 495 { 496 return dev->regmap[KSZ_REGMAP_32]; 497 } 498 499 static inline bool ksz_is_ksz8463(struct ksz_device *dev) 500 { 501 return dev->chip_id == KSZ8463_CHIP_ID; 502 } 503 504 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 505 { 506 unsigned int value; 507 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 508 509 if (ret) 510 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 511 ERR_PTR(ret)); 512 513 *val = value; 514 return ret; 515 } 516 517 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 518 { 519 unsigned int value; 520 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 521 522 if (ret) 523 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 524 ERR_PTR(ret)); 525 526 *val = value; 527 return ret; 528 } 529 530 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 531 { 532 unsigned int value; 533 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 534 535 if (ret) 536 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 537 ERR_PTR(ret)); 538 539 *val = value; 540 return ret; 541 } 542 543 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 544 { 545 u32 value[2]; 546 int ret; 547 548 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 549 if (ret) 550 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 551 ERR_PTR(ret)); 552 else 553 *val = (u64)value[0] << 32 | value[1]; 554 555 return ret; 556 } 557 558 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 559 { 560 int ret; 561 562 ret = regmap_write(ksz_regmap_8(dev), reg, value); 563 if (ret) 564 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 565 ERR_PTR(ret)); 566 567 return ret; 568 } 569 570 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 571 { 572 int ret; 573 574 ret = regmap_write(ksz_regmap_16(dev), reg, value); 575 if (ret) 576 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 577 ERR_PTR(ret)); 578 579 return ret; 580 } 581 582 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 583 { 584 int ret; 585 586 ret = regmap_write(ksz_regmap_32(dev), reg, value); 587 if (ret) 588 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 589 ERR_PTR(ret)); 590 591 return ret; 592 } 593 594 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 595 u16 value) 596 { 597 int ret; 598 599 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 600 if (ret) 601 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 602 ERR_PTR(ret)); 603 604 return ret; 605 } 606 607 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 608 u32 value) 609 { 610 int ret; 611 612 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 613 if (ret) 614 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 615 ERR_PTR(ret)); 616 617 return ret; 618 } 619 620 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 621 { 622 u32 val[2]; 623 624 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 625 value = swab64(value); 626 val[0] = swab32(value & 0xffffffffULL); 627 val[1] = swab32(value >> 32ULL); 628 629 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 630 } 631 632 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 633 { 634 int ret; 635 636 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 637 if (ret) 638 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 639 ERR_PTR(ret)); 640 641 return ret; 642 } 643 644 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 645 u8 *data) 646 { 647 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 648 } 649 650 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 651 u16 *data) 652 { 653 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 654 } 655 656 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 657 u32 *data) 658 { 659 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 660 } 661 662 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 663 u8 data) 664 { 665 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 666 } 667 668 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 669 u16 data) 670 { 671 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 672 data); 673 } 674 675 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 676 u32 data) 677 { 678 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 679 data); 680 } 681 682 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 683 u8 mask, u8 val) 684 { 685 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 686 mask, val); 687 } 688 689 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 690 u32 mask, u32 val) 691 { 692 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 693 mask, val); 694 } 695 696 static inline void ksz_regmap_lock(void *__mtx) 697 { 698 struct mutex *mtx = __mtx; 699 mutex_lock(mtx); 700 } 701 702 static inline void ksz_regmap_unlock(void *__mtx) 703 { 704 struct mutex *mtx = __mtx; 705 mutex_unlock(mtx); 706 } 707 708 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 709 { 710 return dev->chip_id == KSZ8795_CHIP_ID || 711 dev->chip_id == KSZ8794_CHIP_ID || 712 dev->chip_id == KSZ8765_CHIP_ID; 713 } 714 715 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 716 { 717 return dev->chip_id == KSZ88X3_CHIP_ID; 718 } 719 720 static inline bool ksz_is_8895_family(struct ksz_device *dev) 721 { 722 return dev->chip_id == KSZ8895_CHIP_ID || 723 dev->chip_id == KSZ8864_CHIP_ID; 724 } 725 726 static inline bool is_ksz8(struct ksz_device *dev) 727 { 728 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 729 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev); 730 } 731 732 static inline bool is_ksz88xx(struct ksz_device *dev) 733 { 734 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) || 735 ksz_is_ksz8463(dev); 736 } 737 738 static inline bool is_ksz9477(struct ksz_device *dev) 739 { 740 return dev->chip_id == KSZ9477_CHIP_ID; 741 } 742 743 static inline int is_lan937x(struct ksz_device *dev) 744 { 745 return dev->chip_id == LAN9370_CHIP_ID || 746 dev->chip_id == LAN9371_CHIP_ID || 747 dev->chip_id == LAN9372_CHIP_ID || 748 dev->chip_id == LAN9373_CHIP_ID || 749 dev->chip_id == LAN9374_CHIP_ID; 750 } 751 752 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 753 { 754 return (dev->chip_id == LAN9371_CHIP_ID || 755 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 756 } 757 758 static inline int ksz_get_sgmii_port(struct ksz_device *dev) 759 { 760 return dev->info->sgmii_port - 1; 761 } 762 763 static inline bool ksz_has_sgmii_port(struct ksz_device *dev) 764 { 765 return dev->info->sgmii_port > 0; 766 } 767 768 static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port) 769 { 770 return dev->info->sgmii_port == port + 1; 771 } 772 773 /* STP State Defines */ 774 #define PORT_TX_ENABLE BIT(2) 775 #define PORT_RX_ENABLE BIT(1) 776 #define PORT_LEARN_DISABLE BIT(0) 777 778 /* Switch ID Defines */ 779 #define REG_CHIP_ID0 0x00 780 781 #define SW_FAMILY_ID_M GENMASK(15, 8) 782 #define KSZ84_FAMILY_ID 0x84 783 #define KSZ87_FAMILY_ID 0x87 784 #define KSZ88_FAMILY_ID 0x88 785 #define KSZ8895_FAMILY_ID 0x95 786 787 #define KSZ8_PORT_STATUS_0 0x08 788 #define KSZ8_PORT_FIBER_MODE BIT(7) 789 790 #define SW_CHIP_ID_M GENMASK(7, 4) 791 #define KSZ87_CHIP_ID_94 0x6 792 #define KSZ87_CHIP_ID_95 0x9 793 #define KSZ88_CHIP_ID_63 0x3 794 #define KSZ8895_CHIP_ID_95 0x4 795 #define KSZ8895_CHIP_ID_95R 0x6 796 797 /* KSZ8895 specific register */ 798 #define REG_KSZ8864_CHIP_ID 0xFE 799 #define SW_KSZ8864 BIT(7) 800 801 #define SW_REV_ID_M GENMASK(7, 4) 802 803 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 804 #define REG_CHIP_ID4 0x0f 805 #define SKU_ID_KSZ8563 0x3c 806 #define SKU_ID_KSZ9563 0x1c 807 808 /* Driver set switch broadcast storm protection at 10% rate. */ 809 #define BROADCAST_STORM_PROT_RATE 10 810 811 /* 148,800 frames * 67 ms / 100 */ 812 #define BROADCAST_STORM_VALUE 9969 813 814 #define BROADCAST_STORM_RATE_HI 0x07 815 #define BROADCAST_STORM_RATE_LO 0xFF 816 #define BROADCAST_STORM_RATE 0x07FF 817 818 #define MULTICAST_STORM_DISABLE BIT(6) 819 820 #define SW_START 0x01 821 822 /* xMII configuration */ 823 #define P_MII_DUPLEX_M BIT(6) 824 #define P_MII_100MBIT_M BIT(4) 825 826 #define P_GMII_1GBIT_M BIT(6) 827 #define P_RGMII_ID_IG_ENABLE BIT(4) 828 #define P_RGMII_ID_EG_ENABLE BIT(3) 829 #define P_MII_MAC_MODE BIT(2) 830 #define P_MII_SEL_M 0x3 831 832 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 833 #define PME_WOL_MAGICPKT BIT(2) 834 #define PME_WOL_LINKUP BIT(1) 835 #define PME_WOL_ENERGY BIT(0) 836 837 #define PME_ENABLE BIT(1) 838 #define PME_POLARITY BIT(0) 839 840 #define KSZ87XX_REG_INT_EN 0x7D 841 #define KSZ87XX_INT_PME_MASK BIT(4) 842 843 /* Interrupt */ 844 #define REG_SW_PORT_INT_STATUS__1 0x001B 845 #define REG_SW_PORT_INT_MASK__1 0x001F 846 847 #define REG_PORT_INT_STATUS 0x001B 848 #define REG_PORT_INT_MASK 0x001F 849 850 #define PORT_SRC_PHY_INT 1 851 #define PORT_SRC_PTP_INT 2 852 853 #define KSZ8795_HUGE_PACKET_SIZE 2000 854 #define KSZ8863_HUGE_PACKET_SIZE 1916 855 #define KSZ8863_NORMAL_PACKET_SIZE 1536 856 #define KSZ8_LEGAL_PACKET_SIZE 1518 857 #define KSZ9477_MAX_FRAME_SIZE 9000 858 859 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 860 /* Drive Strength of I/O Pad 861 * 0: 8mA, 1: 16mA 862 */ 863 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 864 865 #define KSZ8795_REG_SW_CTRL_20 0xa3 866 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 867 #define SW_DRIVE_STRENGTH_M 0x7 868 #define SW_DRIVE_STRENGTH_2MA 0 869 #define SW_DRIVE_STRENGTH_4MA 1 870 #define SW_DRIVE_STRENGTH_8MA 2 871 #define SW_DRIVE_STRENGTH_12MA 3 872 #define SW_DRIVE_STRENGTH_16MA 4 873 #define SW_DRIVE_STRENGTH_20MA 5 874 #define SW_DRIVE_STRENGTH_24MA 6 875 #define SW_DRIVE_STRENGTH_28MA 7 876 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 877 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 878 879 /* TXQ Split Control Register for per-port, per-queue configuration. 880 * Register 0xAF is TXQ Split for Q3 on Port 1. 881 * Register offset formula: 0xAF + (port * 4) + (3 - queue) 882 * where: port = 0..2, queue = 0..3 883 */ 884 #define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \ 885 (0xAF + ((port) * 4) + (3 - (queue))) 886 887 /* Bit 7 selects between: 888 * 0 = Strict priority mode (highest-priority queue first) 889 * 1 = Weighted Fair Queuing (WFQ) mode: 890 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1 891 * If any queues are empty, weight is redistributed. 892 * 893 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873 894 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs. 895 */ 896 #define KSZ8873_TXQ_WFQ_ENABLE BIT(7) 897 898 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 899 #define KSZ9477_OUT_RATE_NO_LIMIT 0 900 901 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 902 903 #define KSZ9477_PORT_TC_MAP_S 4 904 905 /* CBS related registers */ 906 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 907 908 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 909 910 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 911 #define MTI_SCHEDULE_STRICT_PRIO 0 912 #define MTI_SCHEDULE_WRR 2 913 #define MTI_SHAPING_M GENMASK(5, 4) 914 #define MTI_SHAPING_OFF 0 915 #define MTI_SHAPING_SRP 1 916 #define MTI_SHAPING_TIME_AWARE 2 917 918 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 919 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 920 921 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 922 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 923 924 /* Regmap tables generation */ 925 #define KSZ_SPI_OP_RD 3 926 #define KSZ_SPI_OP_WR 2 927 928 #define swabnot_used(x) 0 929 930 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 931 swab##swp((opcode) << ((regbits) + (regpad))) 932 933 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 934 { \ 935 .name = #width, \ 936 .val_bits = (width), \ 937 .reg_stride = 1, \ 938 .reg_bits = (regbits) + (regalign), \ 939 .pad_bits = (regpad), \ 940 .max_register = BIT(regbits) - 1, \ 941 .cache_type = REGCACHE_NONE, \ 942 .read_flag_mask = \ 943 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 944 regbits, regpad), \ 945 .write_flag_mask = \ 946 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 947 regbits, regpad), \ 948 .lock = ksz_regmap_lock, \ 949 .unlock = ksz_regmap_unlock, \ 950 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 951 .val_format_endian = REGMAP_ENDIAN_BIG \ 952 } 953 954 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 955 static const struct regmap_config ksz##_regmap_config[] = { \ 956 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 957 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 958 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 959 } 960 961 #define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \ 962 { \ 963 .name = #width, \ 964 .val_bits = (width), \ 965 .reg_stride = (width / 8), \ 966 .reg_bits = (regbits) + (regalign), \ 967 .pad_bits = (regpad), \ 968 .read = ksz8463_spi_read, \ 969 .write = ksz8463_spi_write, \ 970 .max_register = BIT(regbits) - 1, \ 971 .cache_type = REGCACHE_NONE, \ 972 .zero_flag_mask = 1, \ 973 .use_single_read = 1, \ 974 .use_single_write = 1, \ 975 .lock = ksz_regmap_lock, \ 976 .unlock = ksz_regmap_unlock, \ 977 } 978 979 #define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \ 980 static const struct regmap_config ksz##_regmap_config[] = { \ 981 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \ 982 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \ 983 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \ 984 } 985 986 #endif 987