1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio codec driver for Creative CA0132 chip
4 *
5 * Copyright (c) 2011, Creative Technology Ltd.
6 *
7 * Based on ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 */
10
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <asm/io.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
26 #include "hda_jack.h"
27
28 #include "ca0132_regs.h"
29
30 /* Enable this to see controls for tuning purpose. */
31 #define ENABLE_TUNING_CONTROLS
32
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
35 #endif
36
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
45
46 #define UNSOL_TAG_DSP 0x16
47
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
54
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
58
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
61
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
69
70 #define SCP_SET 0
71 #define SCP_GET 1
72
73 #define EFX_FILE "ctefx.bin"
74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE "ctefx-r3di.bin"
76
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
79 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
80 MODULE_FIRMWARE(R3DI_EFX_FILE);
81 #endif
82
83 static const char *const dirstr[2] = { "Playback", "Capture" };
84
85 #define NUM_OF_OUTPUTS 2
86 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
87 enum {
88 SPEAKER_OUT,
89 HEADPHONE_OUT,
90 };
91
92 enum {
93 DIGITAL_MIC,
94 LINE_MIC_IN
95 };
96
97 /* Strings for Input Source Enum Control */
98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
99 #define IN_SRC_NUM_OF_INPUTS 3
100 enum {
101 REAR_MIC,
102 REAR_LINE_IN,
103 FRONT_MIC,
104 };
105
106 enum {
107 #define VNODE_START_NID 0x80
108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
109 VNID_MIC,
110 VNID_HP_SEL,
111 VNID_AMIC1_SEL,
112 VNID_HP_ASEL,
113 VNID_AMIC1_ASEL,
114 VNODE_END_NID,
115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
116
117 #define EFFECT_START_NID 0x90
118 #define OUT_EFFECT_START_NID EFFECT_START_NID
119 SURROUND = OUT_EFFECT_START_NID,
120 CRYSTALIZER,
121 DIALOG_PLUS,
122 SMART_VOLUME,
123 X_BASS,
124 EQUALIZER,
125 OUT_EFFECT_END_NID,
126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
127
128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
129 ECHO_CANCELLATION = IN_EFFECT_START_NID,
130 VOICE_FOCUS,
131 MIC_SVM,
132 NOISE_REDUCTION,
133 IN_EFFECT_END_NID,
134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
135
136 VOICEFX = IN_EFFECT_END_NID,
137 PLAY_ENHANCEMENT,
138 CRYSTAL_VOICE,
139 EFFECT_END_NID,
140 OUTPUT_SOURCE_ENUM,
141 INPUT_SOURCE_ENUM,
142 XBASS_XOVER,
143 EQ_PRESET_ENUM,
144 SMART_VOLUME_ENUM,
145 MIC_BOOST_ENUM,
146 AE5_HEADPHONE_GAIN_ENUM,
147 AE5_SOUND_FILTER_ENUM,
148 ZXR_HEADPHONE_GAIN,
149 SPEAKER_CHANNEL_CFG_ENUM,
150 SPEAKER_FULL_RANGE_FRONT,
151 SPEAKER_FULL_RANGE_REAR,
152 BASS_REDIRECTION,
153 BASS_REDIRECTION_XOVER,
154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
155 };
156
157 /* Effects values size*/
158 #define EFFECT_VALS_MAX_COUNT 12
159
160 /*
161 * Default values for the effect slider controls, they are in order of their
162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
163 * X-bass.
164 */
165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
166 /* Amount of effect level sliders for ca0132_alt controls. */
167 #define EFFECT_LEVEL_SLIDERS 5
168
169 /* Latency introduced by DSP blocks in milliseconds. */
170 #define DSP_CAPTURE_INIT_LATENCY 0
171 #define DSP_CRYSTAL_VOICE_LATENCY 124
172 #define DSP_PLAYBACK_INIT_LATENCY 13
173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
174 #define DSP_SPEAKER_OUT_LATENCY 7
175
176 struct ct_effect {
177 const char *name;
178 hda_nid_t nid;
179 int mid; /*effect module ID*/
180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
181 int direct; /* 0:output; 1:input*/
182 int params; /* number of default non-on/off params */
183 /*effect default values, 1st is on/off. */
184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
185 };
186
187 #define EFX_DIR_OUT 0
188 #define EFX_DIR_IN 1
189
190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
191 { .name = "Surround",
192 .nid = SURROUND,
193 .mid = 0x96,
194 .reqs = {0, 1},
195 .direct = EFX_DIR_OUT,
196 .params = 1,
197 .def_vals = {0x3F800000, 0x3F2B851F}
198 },
199 { .name = "Crystalizer",
200 .nid = CRYSTALIZER,
201 .mid = 0x96,
202 .reqs = {7, 8},
203 .direct = EFX_DIR_OUT,
204 .params = 1,
205 .def_vals = {0x3F800000, 0x3F266666}
206 },
207 { .name = "Dialog Plus",
208 .nid = DIALOG_PLUS,
209 .mid = 0x96,
210 .reqs = {2, 3},
211 .direct = EFX_DIR_OUT,
212 .params = 1,
213 .def_vals = {0x00000000, 0x3F000000}
214 },
215 { .name = "Smart Volume",
216 .nid = SMART_VOLUME,
217 .mid = 0x96,
218 .reqs = {4, 5, 6},
219 .direct = EFX_DIR_OUT,
220 .params = 2,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
222 },
223 { .name = "X-Bass",
224 .nid = X_BASS,
225 .mid = 0x96,
226 .reqs = {24, 23, 25},
227 .direct = EFX_DIR_OUT,
228 .params = 2,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
230 },
231 { .name = "Equalizer",
232 .nid = EQUALIZER,
233 .mid = 0x96,
234 .reqs = {9, 10, 11, 12, 13, 14,
235 15, 16, 17, 18, 19, 20},
236 .direct = EFX_DIR_OUT,
237 .params = 11,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
241 },
242 { .name = "Echo Cancellation",
243 .nid = ECHO_CANCELLATION,
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
246 .direct = EFX_DIR_IN,
247 .params = 3,
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
249 },
250 { .name = "Voice Focus",
251 .nid = VOICE_FOCUS,
252 .mid = 0x95,
253 .reqs = {6, 7, 8, 9},
254 .direct = EFX_DIR_IN,
255 .params = 3,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
257 },
258 { .name = "Mic SVM",
259 .nid = MIC_SVM,
260 .mid = 0x95,
261 .reqs = {44, 45},
262 .direct = EFX_DIR_IN,
263 .params = 1,
264 .def_vals = {0x00000000, 0x3F3D70A4}
265 },
266 { .name = "Noise Reduction",
267 .nid = NOISE_REDUCTION,
268 .mid = 0x95,
269 .reqs = {4, 5},
270 .direct = EFX_DIR_IN,
271 .params = 1,
272 .def_vals = {0x3F800000, 0x3F000000}
273 },
274 { .name = "VoiceFX",
275 .nid = VOICEFX,
276 .mid = 0x95,
277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
278 .direct = EFX_DIR_IN,
279 .params = 8,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
283 }
284 };
285
286 /* Tuning controls */
287 #ifdef ENABLE_TUNING_CONTROLS
288
289 enum {
290 #define TUNING_CTL_START_NID 0xC0
291 WEDGE_ANGLE = TUNING_CTL_START_NID,
292 SVM_LEVEL,
293 EQUALIZER_BAND_0,
294 EQUALIZER_BAND_1,
295 EQUALIZER_BAND_2,
296 EQUALIZER_BAND_3,
297 EQUALIZER_BAND_4,
298 EQUALIZER_BAND_5,
299 EQUALIZER_BAND_6,
300 EQUALIZER_BAND_7,
301 EQUALIZER_BAND_8,
302 EQUALIZER_BAND_9,
303 TUNING_CTL_END_NID
304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
305 };
306
307 struct ct_tuning_ctl {
308 const char *name;
309 hda_nid_t parent_nid;
310 hda_nid_t nid;
311 int mid; /*effect module ID*/
312 int req; /*effect module request*/
313 int direct; /* 0:output; 1:input*/
314 unsigned int def_val;/*effect default values*/
315 };
316
317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
318 { .name = "Wedge Angle",
319 .parent_nid = VOICE_FOCUS,
320 .nid = WEDGE_ANGLE,
321 .mid = 0x95,
322 .req = 8,
323 .direct = EFX_DIR_IN,
324 .def_val = 0x41F00000
325 },
326 { .name = "SVM Level",
327 .parent_nid = MIC_SVM,
328 .nid = SVM_LEVEL,
329 .mid = 0x95,
330 .req = 45,
331 .direct = EFX_DIR_IN,
332 .def_val = 0x3F3D70A4
333 },
334 { .name = "EQ Band0",
335 .parent_nid = EQUALIZER,
336 .nid = EQUALIZER_BAND_0,
337 .mid = 0x96,
338 .req = 11,
339 .direct = EFX_DIR_OUT,
340 .def_val = 0x00000000
341 },
342 { .name = "EQ Band1",
343 .parent_nid = EQUALIZER,
344 .nid = EQUALIZER_BAND_1,
345 .mid = 0x96,
346 .req = 12,
347 .direct = EFX_DIR_OUT,
348 .def_val = 0x00000000
349 },
350 { .name = "EQ Band2",
351 .parent_nid = EQUALIZER,
352 .nid = EQUALIZER_BAND_2,
353 .mid = 0x96,
354 .req = 13,
355 .direct = EFX_DIR_OUT,
356 .def_val = 0x00000000
357 },
358 { .name = "EQ Band3",
359 .parent_nid = EQUALIZER,
360 .nid = EQUALIZER_BAND_3,
361 .mid = 0x96,
362 .req = 14,
363 .direct = EFX_DIR_OUT,
364 .def_val = 0x00000000
365 },
366 { .name = "EQ Band4",
367 .parent_nid = EQUALIZER,
368 .nid = EQUALIZER_BAND_4,
369 .mid = 0x96,
370 .req = 15,
371 .direct = EFX_DIR_OUT,
372 .def_val = 0x00000000
373 },
374 { .name = "EQ Band5",
375 .parent_nid = EQUALIZER,
376 .nid = EQUALIZER_BAND_5,
377 .mid = 0x96,
378 .req = 16,
379 .direct = EFX_DIR_OUT,
380 .def_val = 0x00000000
381 },
382 { .name = "EQ Band6",
383 .parent_nid = EQUALIZER,
384 .nid = EQUALIZER_BAND_6,
385 .mid = 0x96,
386 .req = 17,
387 .direct = EFX_DIR_OUT,
388 .def_val = 0x00000000
389 },
390 { .name = "EQ Band7",
391 .parent_nid = EQUALIZER,
392 .nid = EQUALIZER_BAND_7,
393 .mid = 0x96,
394 .req = 18,
395 .direct = EFX_DIR_OUT,
396 .def_val = 0x00000000
397 },
398 { .name = "EQ Band8",
399 .parent_nid = EQUALIZER,
400 .nid = EQUALIZER_BAND_8,
401 .mid = 0x96,
402 .req = 19,
403 .direct = EFX_DIR_OUT,
404 .def_val = 0x00000000
405 },
406 { .name = "EQ Band9",
407 .parent_nid = EQUALIZER,
408 .nid = EQUALIZER_BAND_9,
409 .mid = 0x96,
410 .req = 20,
411 .direct = EFX_DIR_OUT,
412 .def_val = 0x00000000
413 }
414 };
415 #endif
416
417 /* Voice FX Presets */
418 #define VOICEFX_MAX_PARAM_COUNT 9
419
420 struct ct_voicefx {
421 const char *name;
422 hda_nid_t nid;
423 int mid;
424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
425 };
426
427 struct ct_voicefx_preset {
428 const char *name; /*preset name*/
429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
430 };
431
432 static const struct ct_voicefx ca0132_voicefx = {
433 .name = "VoiceFX Capture Switch",
434 .nid = VOICEFX,
435 .mid = 0x95,
436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
437 };
438
439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
440 { .name = "Neutral",
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
444 },
445 { .name = "Female2Male",
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
449 },
450 { .name = "Male2Female",
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
454 },
455 { .name = "ScrappyKid",
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
459 },
460 { .name = "Elderly",
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
464 },
465 { .name = "Orc",
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
469 },
470 { .name = "Elf",
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
474 },
475 { .name = "Dwarf",
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
479 },
480 { .name = "AlienBrute",
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
484 },
485 { .name = "Robot",
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
489 },
490 { .name = "Marine",
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
494 },
495 { .name = "Emo",
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
499 },
500 { .name = "DeepVoice",
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
504 },
505 { .name = "Munchkin",
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
509 }
510 };
511
512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
513
514 #define EQ_PRESET_MAX_PARAM_COUNT 11
515
516 struct ct_eq {
517 const char *name;
518 hda_nid_t nid;
519 int mid;
520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
521 };
522
523 struct ct_eq_preset {
524 const char *name; /*preset name*/
525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
526 };
527
528 static const struct ct_eq ca0132_alt_eq_enum = {
529 .name = "FX: Equalizer Preset Switch",
530 .nid = EQ_PRESET_ENUM,
531 .mid = 0x96,
532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
533 };
534
535
536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
537 { .name = "Flat",
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
542 },
543 { .name = "Acoustic",
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
548 },
549 { .name = "Classical",
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
554 },
555 { .name = "Country",
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
560 },
561 { .name = "Dance",
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
566 },
567 { .name = "Jazz",
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
572 },
573 { .name = "New Age",
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
578 },
579 { .name = "Pop",
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
584 },
585 { .name = "Rock",
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
590 },
591 { .name = "Vocal",
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
596 }
597 };
598
599 /*
600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
601 * set as not being full range, and bass redirection is enabled, all
602 * frequencies below the crossover frequency are redirected to the LFE
603 * channel. If the surround configuration has no LFE channel, this can't be
604 * enabled. X-Bass must be disabled when using these.
605 */
606 enum speaker_range_reqs {
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
615 };
616
617 /*
618 * Definitions for the DSP req's to handle speaker tuning. These all belong to
619 * module ID 0x96, the output effects module.
620 */
621 enum speaker_tuning_reqs {
622 /*
623 * Currently, this value is always set to 0.0f. However, on Windows,
624 * when selecting certain headphone profiles on the new Sound Blaster
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
626 * sent. This gets the speaker EQ address area, which is then used to
627 * send over (presumably) an equalizer profile for the specific
628 * headphone setup. It is sent using the same method the DSP
629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
630 * file exists in linux firmware tree but goes unused. It would also
631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
633 * set to 1.0f.
634 */
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
645 /*
646 * Inversion is used when setting headphone virtualization to line
647 * out. Not sure why this is, but it's the only place it's ever used.
648 */
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
657 /* Delay is used when setting surround speaker distance in Windows. */
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
666 /* Of these two, only mute seems to ever be used. */
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
669 };
670
671 /* Surround output channel count configuration structures. */
672 #define SPEAKER_CHANNEL_CFG_COUNT 5
673 enum {
674 SPEAKER_CHANNELS_2_0,
675 SPEAKER_CHANNELS_2_1,
676 SPEAKER_CHANNELS_4_0,
677 SPEAKER_CHANNELS_4_1,
678 SPEAKER_CHANNELS_5_1,
679 };
680
681 struct ca0132_alt_speaker_channel_cfg {
682 const char *name;
683 unsigned int val;
684 };
685
686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
687 { .name = "2.0",
688 .val = FLOAT_ONE
689 },
690 { .name = "2.1",
691 .val = FLOAT_TWO
692 },
693 { .name = "4.0",
694 .val = FLOAT_FIVE
695 },
696 { .name = "4.1",
697 .val = FLOAT_SIX
698 },
699 { .name = "5.1",
700 .val = FLOAT_EIGHT
701 }
702 };
703
704 /*
705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
706 * and I don't know what the third req is, but it's always zero. I assume it's
707 * some sort of update or set command to tell the DSP there's new volume info.
708 */
709 #define DSP_VOL_OUT 0
710 #define DSP_VOL_IN 1
711
712 struct ct_dsp_volume_ctl {
713 hda_nid_t vnid;
714 int mid; /* module ID*/
715 unsigned int reqs[3]; /* scp req ID */
716 };
717
718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
719 { .vnid = VNID_SPK,
720 .mid = 0x32,
721 .reqs = {3, 4, 2}
722 },
723 { .vnid = VNID_MIC,
724 .mid = 0x37,
725 .reqs = {2, 3, 1}
726 }
727 };
728
729 /* Values for ca0113_mmio_command_set for selecting output. */
730 #define AE_CA0113_OUT_SET_COMMANDS 6
731 struct ae_ca0113_output_set {
732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
735 };
736
737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
740 /* Speakers. */
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
742 /* Headphones. */
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
744 };
745
746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
749 /* Speakers. */
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
751 /* Headphones. */
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
753 };
754
755 /* ae5 ca0113 command sequences to set headphone gain levels. */
756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
757 struct ae5_headphone_gain_set {
758 const char *name;
759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
760 };
761
762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
763 { .name = "Low (16-31",
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
765 },
766 { .name = "Medium (32-149",
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
768 },
769 { .name = "High (150-600",
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
771 }
772 };
773
774 struct ae5_filter_set {
775 const char *name;
776 unsigned int val;
777 };
778
779 static const struct ae5_filter_set ae5_filter_presets[] = {
780 { .name = "Slow Roll Off",
781 .val = 0xa0
782 },
783 { .name = "Minimum Phase",
784 .val = 0xc0
785 },
786 { .name = "Fast Roll Off",
787 .val = 0x80
788 }
789 };
790
791 /*
792 * Data structures for storing audio router remapping data. These are used to
793 * remap a currently active streams ports.
794 */
795 struct chipio_stream_remap_data {
796 unsigned int stream_id;
797 unsigned int count;
798
799 unsigned int offset[16];
800 unsigned int value[16];
801 };
802
803 static const struct chipio_stream_remap_data stream_remap_data[] = {
804 { .stream_id = 0x14,
805 .count = 0x04,
806 .offset = { 0x00, 0x04, 0x08, 0x0c },
807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
808 },
809 { .stream_id = 0x0c,
810 .count = 0x0c,
811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
812 0x20, 0x24, 0x28, 0x2c },
813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
816 },
817 { .stream_id = 0x0c,
818 .count = 0x08,
819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
822 }
823 };
824
825 enum hda_cmd_vendor_io {
826 /* for DspIO node */
827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
829
830 VENDOR_DSPIO_STATUS = 0xF01,
831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
833 VENDOR_DSPIO_DSP_INIT = 0x703,
834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
836
837 /* for ChipIO node */
838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
841 VENDOR_CHIPIO_DATA_LOW = 0x300,
842 VENDOR_CHIPIO_DATA_HIGH = 0x400,
843
844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
846
847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
848 VENDOR_CHIPIO_STATUS = 0xF01,
849 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
851
852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
857
858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
860
861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
865 VENDOR_CHIPIO_FLAG_SET = 0x70F,
866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
867 VENDOR_CHIPIO_PARAM_SET = 0x710,
868 VENDOR_CHIPIO_PARAM_GET = 0xF10,
869
870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
874
875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
879
880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
886
887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
888 };
889
890 /*
891 * Control flag IDs
892 */
893 enum control_flag_id {
894 /* Connection manager stream setup is bypassed/enabled */
895 CONTROL_FLAG_C_MGR = 0,
896 /* DSP DMA is bypassed/enabled */
897 CONTROL_FLAG_DMA = 1,
898 /* 8051 'idle' mode is disabled/enabled */
899 CONTROL_FLAG_IDLE_ENABLE = 2,
900 /* Tracker for the SPDIF-in path is bypassed/enabled */
901 CONTROL_FLAG_TRACKER = 3,
902 /* DigitalOut to Spdif2Out connection is disabled/enabled */
903 CONTROL_FLAG_SPDIF2OUT = 4,
904 /* Digital Microphone is disabled/enabled */
905 CONTROL_FLAG_DMIC = 5,
906 /* ADC_B rate is 48 kHz/96 kHz */
907 CONTROL_FLAG_ADC_B_96KHZ = 6,
908 /* ADC_C rate is 48 kHz/96 kHz */
909 CONTROL_FLAG_ADC_C_96KHZ = 7,
910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
911 CONTROL_FLAG_DAC_96KHZ = 8,
912 /* DSP rate is 48 kHz/96 kHz */
913 CONTROL_FLAG_DSP_96KHZ = 9,
914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
917 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
919 CONTROL_FLAG_DECODE_LOOP = 12,
920 /* De-emphasis filter on DAC-1 disabled/enabled */
921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
922 /* De-emphasis filter on DAC-2 disabled/enabled */
923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
924 /* De-emphasis filter on DAC-3 disabled/enabled */
925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
926 /* High-pass filter on ADC_B disabled/enabled */
927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
928 /* High-pass filter on ADC_C disabled/enabled */
929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
930 /* Common mode on Port_A disabled/enabled */
931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
932 /* Common mode on Port_D disabled/enabled */
933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
938 /* ASI rate is 48kHz/96kHz */
939 CONTROL_FLAG_ASI_96KHZ = 22,
940 /* DAC power settings able to control attached ports no/yes */
941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
942 /* Clock Stop OK reporting is disabled/enabled */
943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
944 /* Number of control flags */
945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
946 };
947
948 /*
949 * Control parameter IDs
950 */
951 enum control_param_id {
952 /* 0: None, 1: Mic1In*/
953 CONTROL_PARAM_VIP_SOURCE = 1,
954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
955 CONTROL_PARAM_SPDIF1_SOURCE = 2,
956 /* Port A output stage gain setting to use when 16 Ohm output
957 * impedance is selected*/
958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
959 /* Port D output stage gain setting to use when 16 Ohm output
960 * impedance is selected*/
961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
962
963 /*
964 * This control param name was found in the 8051 memory, and makes
965 * sense given the fact the AE-5 uses it and has the ASI flag set.
966 */
967 CONTROL_PARAM_ASI = 23,
968
969 /* Stream Control */
970
971 /* Select stream with the given ID */
972 CONTROL_PARAM_STREAM_ID = 24,
973 /* Source connection point for the selected stream */
974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
975 /* Destination connection point for the selected stream */
976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
977 /* Number of audio channels in the selected stream */
978 CONTROL_PARAM_STREAMS_CHANNELS = 27,
979 /*Enable control for the selected stream */
980 CONTROL_PARAM_STREAM_CONTROL = 28,
981
982 /* Connection Point Control */
983
984 /* Select connection point with the given ID */
985 CONTROL_PARAM_CONN_POINT_ID = 29,
986 /* Connection point sample rate */
987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
988
989 /* Node Control */
990
991 /* Select HDA node with the given ID */
992 CONTROL_PARAM_NODE_ID = 31
993 };
994
995 /*
996 * Dsp Io Status codes
997 */
998 enum hda_vendor_status_dspio {
999 /* Success */
1000 VENDOR_STATUS_DSPIO_OK = 0x00,
1001 /* Busy, unable to accept new command, the host must retry */
1002 VENDOR_STATUS_DSPIO_BUSY = 0x01,
1003 /* SCP command queue is full */
1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
1005 /* SCP response queue is empty */
1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1007 };
1008
1009 /*
1010 * Chip Io Status codes
1011 */
1012 enum hda_vendor_status_chipio {
1013 /* Success */
1014 VENDOR_STATUS_CHIPIO_OK = 0x00,
1015 /* Busy, unable to accept new command, the host must retry */
1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01
1017 };
1018
1019 /*
1020 * CA0132 sample rate
1021 */
1022 enum ca0132_sample_rate {
1023 SR_6_000 = 0x00,
1024 SR_8_000 = 0x01,
1025 SR_9_600 = 0x02,
1026 SR_11_025 = 0x03,
1027 SR_16_000 = 0x04,
1028 SR_22_050 = 0x05,
1029 SR_24_000 = 0x06,
1030 SR_32_000 = 0x07,
1031 SR_44_100 = 0x08,
1032 SR_48_000 = 0x09,
1033 SR_88_200 = 0x0A,
1034 SR_96_000 = 0x0B,
1035 SR_144_000 = 0x0C,
1036 SR_176_400 = 0x0D,
1037 SR_192_000 = 0x0E,
1038 SR_384_000 = 0x0F,
1039
1040 SR_COUNT = 0x10,
1041
1042 SR_RATE_UNKNOWN = 0x1F
1043 };
1044
1045 enum dsp_download_state {
1046 DSP_DOWNLOAD_FAILED = -1,
1047 DSP_DOWNLOAD_INIT = 0,
1048 DSP_DOWNLOADING = 1,
1049 DSP_DOWNLOADED = 2
1050 };
1051
1052 /* retrieve parameters from hda format */
1053 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1057
1058 /*
1059 * CA0132 specific
1060 */
1061
1062 struct ca0132_spec {
1063 const struct snd_kcontrol_new *mixers[5];
1064 unsigned int num_mixers;
1065 const struct hda_verb *base_init_verbs;
1066 const struct hda_verb *base_exit_verbs;
1067 const struct hda_verb *chip_init_verbs;
1068 const struct hda_verb *desktop_init_verbs;
1069 struct hda_verb *spec_init_verbs;
1070 struct auto_pin_cfg autocfg;
1071
1072 /* Nodes configurations */
1073 struct hda_multi_out multiout;
1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1076 unsigned int num_outputs;
1077 hda_nid_t input_pins[AUTO_PIN_LAST];
1078 hda_nid_t adcs[AUTO_PIN_LAST];
1079 hda_nid_t dig_out;
1080 hda_nid_t dig_in;
1081 unsigned int num_inputs;
1082 hda_nid_t shared_mic_nid;
1083 hda_nid_t shared_out_nid;
1084 hda_nid_t unsol_tag_hp;
1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1086 hda_nid_t unsol_tag_amic1;
1087
1088 /* chip access */
1089 struct mutex chipio_mutex; /* chip access mutex */
1090 u32 curr_chip_addx;
1091
1092 /* DSP download related */
1093 enum dsp_download_state dsp_state;
1094 unsigned int dsp_stream_id;
1095 unsigned int wait_scp;
1096 unsigned int wait_scp_header;
1097 unsigned int wait_num_data;
1098 unsigned int scp_resp_header;
1099 unsigned int scp_resp_data[4];
1100 unsigned int scp_resp_count;
1101 bool startup_check_entered;
1102 bool dsp_reload;
1103
1104 /* mixer and effects related */
1105 unsigned char dmic_ctl;
1106 int cur_out_type;
1107 int cur_mic_type;
1108 long vnode_lvol[VNODES_COUNT];
1109 long vnode_rvol[VNODES_COUNT];
1110 long vnode_lswitch[VNODES_COUNT];
1111 long vnode_rswitch[VNODES_COUNT];
1112 long effects_switch[EFFECTS_COUNT];
1113 long voicefx_val;
1114 long cur_mic_boost;
1115 /* ca0132_alt control related values */
1116 unsigned char in_enum_val;
1117 unsigned char out_enum_val;
1118 unsigned char channel_cfg_val;
1119 unsigned char speaker_range_val[2];
1120 unsigned char mic_boost_enum_val;
1121 unsigned char smart_volume_setting;
1122 unsigned char bass_redirection_val;
1123 long bass_redirect_xover_freq;
1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1125 long xbass_xover_freq;
1126 long eq_preset_val;
1127 unsigned int tlv[4];
1128 struct hda_vmaster_mute_hook vmaster_mute;
1129 /* AE-5 Control values */
1130 unsigned char ae5_headphone_gain_val;
1131 unsigned char ae5_filter_val;
1132 /* ZxR Control Values */
1133 unsigned char zxr_gain_set;
1134
1135 struct hda_codec *codec;
1136 struct delayed_work unsol_hp_work;
1137
1138 #ifdef ENABLE_TUNING_CONTROLS
1139 long cur_ctl_vals[TUNING_CTLS_COUNT];
1140 #endif
1141 /*
1142 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1143 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1144 * things.
1145 */
1146 bool use_pci_mmio;
1147 void __iomem *mem_base;
1148
1149 /*
1150 * Whether or not to use the alt functions like alt_select_out,
1151 * alt_select_in, etc. Only used on desktop codecs for now, because of
1152 * surround sound support.
1153 */
1154 bool use_alt_functions;
1155
1156 /*
1157 * Whether or not to use alt controls: volume effect sliders, EQ
1158 * presets, smart volume presets, and new control names with FX prefix.
1159 * Renames PlayEnhancement and CrystalVoice too.
1160 */
1161 bool use_alt_controls;
1162 };
1163
1164 /*
1165 * CA0132 quirks table
1166 */
1167 enum {
1168 QUIRK_ALIENWARE,
1169 QUIRK_ALIENWARE_M17XR4,
1170 QUIRK_SBZ,
1171 QUIRK_ZXR,
1172 QUIRK_ZXR_DBPRO,
1173 QUIRK_R3DI,
1174 QUIRK_R3D,
1175 QUIRK_AE5,
1176 QUIRK_AE7,
1177 QUIRK_NONE = HDA_FIXUP_ID_NOT_SET,
1178 };
1179
1180 #ifdef CONFIG_PCI
1181 #define ca0132_quirk(spec) ((spec)->codec->fixup_id)
1182 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1183 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1184 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1185 #else
1186 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1187 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1188 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1189 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1190 #endif
1191
1192 static const struct hda_pintbl alienware_pincfgs[] = {
1193 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1194 { 0x0c, 0x411111f0 }, /* N/A */
1195 { 0x0d, 0x411111f0 }, /* N/A */
1196 { 0x0e, 0x411111f0 }, /* N/A */
1197 { 0x0f, 0x0321101f }, /* HP */
1198 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1199 { 0x11, 0x03a11021 }, /* Mic */
1200 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1201 { 0x13, 0x411111f0 }, /* N/A */
1202 { 0x18, 0x411111f0 }, /* N/A */
1203 {}
1204 };
1205
1206 /* Sound Blaster Z pin configs taken from Windows Driver */
1207 static const struct hda_pintbl sbz_pincfgs[] = {
1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1210 { 0x0d, 0x014510f0 }, /* Digital Out */
1211 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1216 { 0x13, 0x908700f0 }, /* What U Hear In*/
1217 { 0x18, 0x50d000f0 }, /* N/A */
1218 {}
1219 };
1220
1221 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1222 static const struct hda_pintbl zxr_pincfgs[] = {
1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1225 { 0x0d, 0x014510f0 }, /* Digital Out */
1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1231 { 0x13, 0x908700f0 }, /* What U Hear In*/
1232 { 0x18, 0x50d000f0 }, /* N/A */
1233 {}
1234 };
1235
1236 /* Recon3D pin configs taken from Windows Driver */
1237 static const struct hda_pintbl r3d_pincfgs[] = {
1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1240 { 0x0d, 0x014510f0 }, /* Digital Out */
1241 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1246 { 0x13, 0x908700f0 }, /* What U Hear In*/
1247 { 0x18, 0x50d000f0 }, /* N/A */
1248 {}
1249 };
1250
1251 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1252 static const struct hda_pintbl ae5_pincfgs[] = {
1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1255 { 0x0d, 0x014510f0 }, /* Digital Out */
1256 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1261 { 0x13, 0x908700f0 }, /* What U Hear In*/
1262 { 0x18, 0x50d000f0 }, /* N/A */
1263 {}
1264 };
1265
1266 /* Recon3D integrated pin configs taken from Windows Driver */
1267 static const struct hda_pintbl r3di_pincfgs[] = {
1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1270 { 0x0d, 0x014510f0 }, /* Digital Out */
1271 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1276 { 0x13, 0x908700f0 }, /* What U Hear In*/
1277 { 0x18, 0x500000f0 }, /* N/A */
1278 {}
1279 };
1280
1281 static const struct hda_pintbl ae7_pincfgs[] = {
1282 { 0x0b, 0x01017010 },
1283 { 0x0c, 0x014510f0 },
1284 { 0x0d, 0x414510f0 },
1285 { 0x0e, 0x01c520f0 },
1286 { 0x0f, 0x01017114 },
1287 { 0x10, 0x01017011 },
1288 { 0x11, 0x018170ff },
1289 { 0x12, 0x01a170f0 },
1290 { 0x13, 0x908700f0 },
1291 { 0x18, 0x500000f0 },
1292 {}
1293 };
1294
1295 static const struct hda_quirk ca0132_quirks[] = {
1296 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1297 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1298 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1299 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1300 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1301 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1302 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1303 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1304 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1305 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1307 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1308 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1315 {}
1316 };
1317
1318 static const struct hda_model_fixup ca0132_quirk_models[] = {
1319 { .id = QUIRK_ALIENWARE, .name = "alienware" },
1320 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" },
1321 { .id = QUIRK_SBZ, .name = "sbz" },
1322 { .id = QUIRK_ZXR, .name = "zxr" },
1323 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" },
1324 { .id = QUIRK_R3DI, .name = "r3di" },
1325 { .id = QUIRK_R3D, .name = "r3d" },
1326 { .id = QUIRK_AE5, .name = "ae5" },
1327 { .id = QUIRK_AE7, .name = "ae7" },
1328 {}
1329 };
1330
1331 /* Output selection quirk info structures. */
1332 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1333 #define MAX_QUIRK_SCP_SET_VALS 2
1334 struct ca0132_alt_out_set_info {
1335 unsigned int dac2port; /* ParamID 0x0d value. */
1336
1337 bool has_hda_gpio;
1338 char hda_gpio_pin;
1339 char hda_gpio_set;
1340
1341 unsigned int mmio_gpio_count;
1342 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1343 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1344
1345 unsigned int scp_cmds_count;
1346 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1347 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1348 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1349
1350 bool has_chipio_write;
1351 unsigned int chipio_write_addr;
1352 unsigned int chipio_write_data;
1353 };
1354
1355 struct ca0132_alt_out_set_quirk_data {
1356 int quirk_id;
1357
1358 bool has_headphone_gain;
1359 bool is_ae_series;
1360
1361 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1362 };
1363
1364 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1365 { .quirk_id = QUIRK_R3DI,
1366 .has_headphone_gain = false,
1367 .is_ae_series = false,
1368 .out_set_info = {
1369 /* Speakers. */
1370 { .dac2port = 0x24,
1371 .has_hda_gpio = true,
1372 .hda_gpio_pin = 2,
1373 .hda_gpio_set = 1,
1374 .mmio_gpio_count = 0,
1375 .scp_cmds_count = 0,
1376 .has_chipio_write = false,
1377 },
1378 /* Headphones. */
1379 { .dac2port = 0x21,
1380 .has_hda_gpio = true,
1381 .hda_gpio_pin = 2,
1382 .hda_gpio_set = 0,
1383 .mmio_gpio_count = 0,
1384 .scp_cmds_count = 0,
1385 .has_chipio_write = false,
1386 } },
1387 },
1388 { .quirk_id = QUIRK_R3D,
1389 .has_headphone_gain = false,
1390 .is_ae_series = false,
1391 .out_set_info = {
1392 /* Speakers. */
1393 { .dac2port = 0x24,
1394 .has_hda_gpio = false,
1395 .mmio_gpio_count = 1,
1396 .mmio_gpio_pin = { 1 },
1397 .mmio_gpio_set = { 1 },
1398 .scp_cmds_count = 0,
1399 .has_chipio_write = false,
1400 },
1401 /* Headphones. */
1402 { .dac2port = 0x21,
1403 .has_hda_gpio = false,
1404 .mmio_gpio_count = 1,
1405 .mmio_gpio_pin = { 1 },
1406 .mmio_gpio_set = { 0 },
1407 .scp_cmds_count = 0,
1408 .has_chipio_write = false,
1409 } },
1410 },
1411 { .quirk_id = QUIRK_SBZ,
1412 .has_headphone_gain = false,
1413 .is_ae_series = false,
1414 .out_set_info = {
1415 /* Speakers. */
1416 { .dac2port = 0x18,
1417 .has_hda_gpio = false,
1418 .mmio_gpio_count = 3,
1419 .mmio_gpio_pin = { 7, 4, 1 },
1420 .mmio_gpio_set = { 0, 1, 1 },
1421 .scp_cmds_count = 0,
1422 .has_chipio_write = false, },
1423 /* Headphones. */
1424 { .dac2port = 0x12,
1425 .has_hda_gpio = false,
1426 .mmio_gpio_count = 3,
1427 .mmio_gpio_pin = { 7, 4, 1 },
1428 .mmio_gpio_set = { 1, 1, 0 },
1429 .scp_cmds_count = 0,
1430 .has_chipio_write = false,
1431 } },
1432 },
1433 { .quirk_id = QUIRK_ZXR,
1434 .has_headphone_gain = true,
1435 .is_ae_series = false,
1436 .out_set_info = {
1437 /* Speakers. */
1438 { .dac2port = 0x24,
1439 .has_hda_gpio = false,
1440 .mmio_gpio_count = 3,
1441 .mmio_gpio_pin = { 2, 3, 5 },
1442 .mmio_gpio_set = { 1, 1, 0 },
1443 .scp_cmds_count = 0,
1444 .has_chipio_write = false,
1445 },
1446 /* Headphones. */
1447 { .dac2port = 0x21,
1448 .has_hda_gpio = false,
1449 .mmio_gpio_count = 3,
1450 .mmio_gpio_pin = { 2, 3, 5 },
1451 .mmio_gpio_set = { 0, 1, 1 },
1452 .scp_cmds_count = 0,
1453 .has_chipio_write = false,
1454 } },
1455 },
1456 { .quirk_id = QUIRK_AE5,
1457 .has_headphone_gain = true,
1458 .is_ae_series = true,
1459 .out_set_info = {
1460 /* Speakers. */
1461 { .dac2port = 0xa4,
1462 .has_hda_gpio = false,
1463 .mmio_gpio_count = 0,
1464 .scp_cmds_count = 2,
1465 .scp_cmd_mid = { 0x96, 0x96 },
1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1468 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1469 .has_chipio_write = true,
1470 .chipio_write_addr = 0x0018b03c,
1471 .chipio_write_data = 0x00000012
1472 },
1473 /* Headphones. */
1474 { .dac2port = 0xa1,
1475 .has_hda_gpio = false,
1476 .mmio_gpio_count = 0,
1477 .scp_cmds_count = 2,
1478 .scp_cmd_mid = { 0x96, 0x96 },
1479 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1480 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1481 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1482 .has_chipio_write = true,
1483 .chipio_write_addr = 0x0018b03c,
1484 .chipio_write_data = 0x00000012
1485 } },
1486 },
1487 { .quirk_id = QUIRK_AE7,
1488 .has_headphone_gain = true,
1489 .is_ae_series = true,
1490 .out_set_info = {
1491 /* Speakers. */
1492 { .dac2port = 0x58,
1493 .has_hda_gpio = false,
1494 .mmio_gpio_count = 1,
1495 .mmio_gpio_pin = { 0 },
1496 .mmio_gpio_set = { 1 },
1497 .scp_cmds_count = 2,
1498 .scp_cmd_mid = { 0x96, 0x96 },
1499 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1500 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1501 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1502 .has_chipio_write = true,
1503 .chipio_write_addr = 0x0018b03c,
1504 .chipio_write_data = 0x00000000
1505 },
1506 /* Headphones. */
1507 { .dac2port = 0x58,
1508 .has_hda_gpio = false,
1509 .mmio_gpio_count = 1,
1510 .mmio_gpio_pin = { 0 },
1511 .mmio_gpio_set = { 1 },
1512 .scp_cmds_count = 2,
1513 .scp_cmd_mid = { 0x96, 0x96 },
1514 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1515 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1516 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1517 .has_chipio_write = true,
1518 .chipio_write_addr = 0x0018b03c,
1519 .chipio_write_data = 0x00000010
1520 } },
1521 }
1522 };
1523
1524 /*
1525 * CA0132 codec access
1526 */
codec_send_command(struct hda_codec * codec,hda_nid_t nid,unsigned int verb,unsigned int parm,unsigned int * res)1527 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1528 unsigned int verb, unsigned int parm, unsigned int *res)
1529 {
1530 unsigned int response;
1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1532 *res = response;
1533
1534 return ((response == -1) ? -1 : 0);
1535 }
1536
codec_set_converter_format(struct hda_codec * codec,hda_nid_t nid,unsigned short converter_format,unsigned int * res)1537 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1538 unsigned short converter_format, unsigned int *res)
1539 {
1540 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1541 converter_format & 0xffff, res);
1542 }
1543
codec_set_converter_stream_channel(struct hda_codec * codec,hda_nid_t nid,unsigned char stream,unsigned char channel,unsigned int * res)1544 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1545 hda_nid_t nid, unsigned char stream,
1546 unsigned char channel, unsigned int *res)
1547 {
1548 unsigned char converter_stream_channel = 0;
1549
1550 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1551 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1552 converter_stream_channel, res);
1553 }
1554
1555 /* Chip access helper function */
chipio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1556 static int chipio_send(struct hda_codec *codec,
1557 unsigned int reg,
1558 unsigned int data)
1559 {
1560 unsigned int res;
1561 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1562
1563 /* send bits of data specified by reg */
1564 do {
1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1566 reg, data);
1567 if (res == VENDOR_STATUS_CHIPIO_OK)
1568 return 0;
1569 msleep(20);
1570 } while (time_before(jiffies, timeout));
1571
1572 return -EIO;
1573 }
1574
1575 /*
1576 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1577 */
chipio_write_address(struct hda_codec * codec,unsigned int chip_addx)1578 static int chipio_write_address(struct hda_codec *codec,
1579 unsigned int chip_addx)
1580 {
1581 struct ca0132_spec *spec = codec->spec;
1582 int res;
1583
1584 if (spec->curr_chip_addx == chip_addx)
1585 return 0;
1586
1587 /* send low 16 bits of the address */
1588 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1589 chip_addx & 0xffff);
1590
1591 if (res != -EIO) {
1592 /* send high 16 bits of the address */
1593 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1594 chip_addx >> 16);
1595 }
1596
1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1598
1599 return res;
1600 }
1601
1602 /*
1603 * Write data through the vendor widget -- NOT protected by the Mutex!
1604 */
chipio_write_data(struct hda_codec * codec,unsigned int data)1605 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1606 {
1607 struct ca0132_spec *spec = codec->spec;
1608 int res;
1609
1610 /* send low 16 bits of the data */
1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1612
1613 if (res != -EIO) {
1614 /* send high 16 bits of the data */
1615 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1616 data >> 16);
1617 }
1618
1619 /*If no error encountered, automatically increment the address
1620 as per chip behaviour*/
1621 spec->curr_chip_addx = (res != -EIO) ?
1622 (spec->curr_chip_addx + 4) : ~0U;
1623 return res;
1624 }
1625
1626 /*
1627 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1628 */
chipio_write_data_multiple(struct hda_codec * codec,const u32 * data,unsigned int count)1629 static int chipio_write_data_multiple(struct hda_codec *codec,
1630 const u32 *data,
1631 unsigned int count)
1632 {
1633 int status = 0;
1634
1635 if (data == NULL) {
1636 codec_dbg(codec, "chipio_write_data null ptr\n");
1637 return -EINVAL;
1638 }
1639
1640 while ((count-- != 0) && (status == 0))
1641 status = chipio_write_data(codec, *data++);
1642
1643 return status;
1644 }
1645
1646
1647 /*
1648 * Read data through the vendor widget -- NOT protected by the Mutex!
1649 */
chipio_read_data(struct hda_codec * codec,unsigned int * data)1650 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1651 {
1652 struct ca0132_spec *spec = codec->spec;
1653 int res;
1654
1655 /* post read */
1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1657
1658 if (res != -EIO) {
1659 /* read status */
1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1661 }
1662
1663 if (res != -EIO) {
1664 /* read data */
1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1666 VENDOR_CHIPIO_HIC_READ_DATA,
1667 0);
1668 }
1669
1670 /*If no error encountered, automatically increment the address
1671 as per chip behaviour*/
1672 spec->curr_chip_addx = (res != -EIO) ?
1673 (spec->curr_chip_addx + 4) : ~0U;
1674 return res;
1675 }
1676
1677 /*
1678 * Write given value to the given address through the chip I/O widget.
1679 * protected by the Mutex
1680 */
chipio_write(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1681 static int chipio_write(struct hda_codec *codec,
1682 unsigned int chip_addx, const unsigned int data)
1683 {
1684 struct ca0132_spec *spec = codec->spec;
1685 int err;
1686
1687 mutex_lock(&spec->chipio_mutex);
1688
1689 /* write the address, and if successful proceed to write data */
1690 err = chipio_write_address(codec, chip_addx);
1691 if (err < 0)
1692 goto exit;
1693
1694 err = chipio_write_data(codec, data);
1695 if (err < 0)
1696 goto exit;
1697
1698 exit:
1699 mutex_unlock(&spec->chipio_mutex);
1700 return err;
1701 }
1702
1703 /*
1704 * Write given value to the given address through the chip I/O widget.
1705 * not protected by the Mutex
1706 */
chipio_write_no_mutex(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1707 static int chipio_write_no_mutex(struct hda_codec *codec,
1708 unsigned int chip_addx, const unsigned int data)
1709 {
1710 int err;
1711
1712
1713 /* write the address, and if successful proceed to write data */
1714 err = chipio_write_address(codec, chip_addx);
1715 if (err < 0)
1716 goto exit;
1717
1718 err = chipio_write_data(codec, data);
1719 if (err < 0)
1720 goto exit;
1721
1722 exit:
1723 return err;
1724 }
1725
1726 /*
1727 * Write multiple values to the given address through the chip I/O widget.
1728 * protected by the Mutex
1729 */
chipio_write_multiple(struct hda_codec * codec,u32 chip_addx,const u32 * data,unsigned int count)1730 static int chipio_write_multiple(struct hda_codec *codec,
1731 u32 chip_addx,
1732 const u32 *data,
1733 unsigned int count)
1734 {
1735 struct ca0132_spec *spec = codec->spec;
1736 int status;
1737
1738 mutex_lock(&spec->chipio_mutex);
1739 status = chipio_write_address(codec, chip_addx);
1740 if (status < 0)
1741 goto error;
1742
1743 status = chipio_write_data_multiple(codec, data, count);
1744 error:
1745 mutex_unlock(&spec->chipio_mutex);
1746
1747 return status;
1748 }
1749
1750 /*
1751 * Read the given address through the chip I/O widget
1752 * protected by the Mutex
1753 */
chipio_read(struct hda_codec * codec,unsigned int chip_addx,unsigned int * data)1754 static int chipio_read(struct hda_codec *codec,
1755 unsigned int chip_addx, unsigned int *data)
1756 {
1757 struct ca0132_spec *spec = codec->spec;
1758 int err;
1759
1760 mutex_lock(&spec->chipio_mutex);
1761
1762 /* write the address, and if successful proceed to write data */
1763 err = chipio_write_address(codec, chip_addx);
1764 if (err < 0)
1765 goto exit;
1766
1767 err = chipio_read_data(codec, data);
1768 if (err < 0)
1769 goto exit;
1770
1771 exit:
1772 mutex_unlock(&spec->chipio_mutex);
1773 return err;
1774 }
1775
1776 /*
1777 * Set chip control flags through the chip I/O widget.
1778 */
chipio_set_control_flag(struct hda_codec * codec,enum control_flag_id flag_id,bool flag_state)1779 static void chipio_set_control_flag(struct hda_codec *codec,
1780 enum control_flag_id flag_id,
1781 bool flag_state)
1782 {
1783 unsigned int val;
1784 unsigned int flag_bit;
1785
1786 flag_bit = (flag_state ? 1 : 0);
1787 val = (flag_bit << 7) | (flag_id);
1788 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1789 VENDOR_CHIPIO_FLAG_SET, val);
1790 }
1791
1792 /*
1793 * Set chip parameters through the chip I/O widget.
1794 */
chipio_set_control_param(struct hda_codec * codec,enum control_param_id param_id,int param_val)1795 static void chipio_set_control_param(struct hda_codec *codec,
1796 enum control_param_id param_id, int param_val)
1797 {
1798 struct ca0132_spec *spec = codec->spec;
1799 int val;
1800
1801 if ((param_id < 32) && (param_val < 8)) {
1802 val = (param_val << 5) | (param_id);
1803 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1804 VENDOR_CHIPIO_PARAM_SET, val);
1805 } else {
1806 mutex_lock(&spec->chipio_mutex);
1807 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1808 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1809 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1810 param_id);
1811 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1812 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1813 param_val);
1814 }
1815 mutex_unlock(&spec->chipio_mutex);
1816 }
1817 }
1818
1819 /*
1820 * Set chip parameters through the chip I/O widget. NO MUTEX.
1821 */
chipio_set_control_param_no_mutex(struct hda_codec * codec,enum control_param_id param_id,int param_val)1822 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1823 enum control_param_id param_id, int param_val)
1824 {
1825 int val;
1826
1827 if ((param_id < 32) && (param_val < 8)) {
1828 val = (param_val << 5) | (param_id);
1829 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1830 VENDOR_CHIPIO_PARAM_SET, val);
1831 } else {
1832 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1833 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1834 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1835 param_id);
1836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1837 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1838 param_val);
1839 }
1840 }
1841 }
1842 /*
1843 * Connect stream to a source point, and then connect
1844 * that source point to a destination point.
1845 */
chipio_set_stream_source_dest(struct hda_codec * codec,int streamid,int source_point,int dest_point)1846 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1847 int streamid, int source_point, int dest_point)
1848 {
1849 chipio_set_control_param_no_mutex(codec,
1850 CONTROL_PARAM_STREAM_ID, streamid);
1851 chipio_set_control_param_no_mutex(codec,
1852 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1853 chipio_set_control_param_no_mutex(codec,
1854 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1855 }
1856
1857 /*
1858 * Set number of channels in the selected stream.
1859 */
chipio_set_stream_channels(struct hda_codec * codec,int streamid,unsigned int channels)1860 static void chipio_set_stream_channels(struct hda_codec *codec,
1861 int streamid, unsigned int channels)
1862 {
1863 chipio_set_control_param_no_mutex(codec,
1864 CONTROL_PARAM_STREAM_ID, streamid);
1865 chipio_set_control_param_no_mutex(codec,
1866 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1867 }
1868
1869 /*
1870 * Enable/Disable audio stream.
1871 */
chipio_set_stream_control(struct hda_codec * codec,int streamid,int enable)1872 static void chipio_set_stream_control(struct hda_codec *codec,
1873 int streamid, int enable)
1874 {
1875 chipio_set_control_param_no_mutex(codec,
1876 CONTROL_PARAM_STREAM_ID, streamid);
1877 chipio_set_control_param_no_mutex(codec,
1878 CONTROL_PARAM_STREAM_CONTROL, enable);
1879 }
1880
1881 /*
1882 * Get ChipIO audio stream's status.
1883 */
chipio_get_stream_control(struct hda_codec * codec,int streamid,unsigned int * enable)1884 static void chipio_get_stream_control(struct hda_codec *codec,
1885 int streamid, unsigned int *enable)
1886 {
1887 chipio_set_control_param_no_mutex(codec,
1888 CONTROL_PARAM_STREAM_ID, streamid);
1889 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1890 VENDOR_CHIPIO_PARAM_GET,
1891 CONTROL_PARAM_STREAM_CONTROL);
1892 }
1893
1894 /*
1895 * Set sampling rate of the connection point. NO MUTEX.
1896 */
chipio_set_conn_rate_no_mutex(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1897 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1898 int connid, enum ca0132_sample_rate rate)
1899 {
1900 chipio_set_control_param_no_mutex(codec,
1901 CONTROL_PARAM_CONN_POINT_ID, connid);
1902 chipio_set_control_param_no_mutex(codec,
1903 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1904 }
1905
1906 /*
1907 * Set sampling rate of the connection point.
1908 */
chipio_set_conn_rate(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1909 static void chipio_set_conn_rate(struct hda_codec *codec,
1910 int connid, enum ca0132_sample_rate rate)
1911 {
1912 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1913 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1914 rate);
1915 }
1916
1917 /*
1918 * Writes to the 8051's internal address space directly instead of indirectly,
1919 * giving access to the special function registers located at addresses
1920 * 0x80-0xFF.
1921 */
chipio_8051_write_direct(struct hda_codec * codec,unsigned int addr,unsigned int data)1922 static void chipio_8051_write_direct(struct hda_codec *codec,
1923 unsigned int addr, unsigned int data)
1924 {
1925 unsigned int verb;
1926
1927 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1929 }
1930
1931 /*
1932 * Writes to the 8051's exram, which has 16-bits of address space.
1933 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1934 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1935 * setting the pmem bank selection SFR.
1936 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1937 * being writable.
1938 */
chipio_8051_set_address(struct hda_codec * codec,unsigned int addr)1939 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1940 {
1941 unsigned int tmp;
1942
1943 /* Lower 8-bits. */
1944 tmp = addr & 0xff;
1945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1946 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1947
1948 /* Upper 8-bits. */
1949 tmp = (addr >> 8) & 0xff;
1950 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1951 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1952 }
1953
chipio_8051_set_data(struct hda_codec * codec,unsigned int data)1954 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1955 {
1956 /* 8-bits of data. */
1957 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1958 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1959 }
1960
chipio_8051_get_data(struct hda_codec * codec)1961 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1962 {
1963 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1964 VENDOR_CHIPIO_8051_DATA_READ, 0);
1965 }
1966
1967 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */
chipio_8051_set_data_pll(struct hda_codec * codec,unsigned int data)1968 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1969 {
1970 /* 8-bits of data. */
1971 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1972 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1973 }
1974
chipio_8051_write_exram(struct hda_codec * codec,unsigned int addr,unsigned int data)1975 static void chipio_8051_write_exram(struct hda_codec *codec,
1976 unsigned int addr, unsigned int data)
1977 {
1978 struct ca0132_spec *spec = codec->spec;
1979
1980 mutex_lock(&spec->chipio_mutex);
1981
1982 chipio_8051_set_address(codec, addr);
1983 chipio_8051_set_data(codec, data);
1984
1985 mutex_unlock(&spec->chipio_mutex);
1986 }
1987
chipio_8051_write_exram_no_mutex(struct hda_codec * codec,unsigned int addr,unsigned int data)1988 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1989 unsigned int addr, unsigned int data)
1990 {
1991 chipio_8051_set_address(codec, addr);
1992 chipio_8051_set_data(codec, data);
1993 }
1994
1995 /* Readback data from the 8051's exram. No mutex. */
chipio_8051_read_exram(struct hda_codec * codec,unsigned int addr,unsigned int * data)1996 static void chipio_8051_read_exram(struct hda_codec *codec,
1997 unsigned int addr, unsigned int *data)
1998 {
1999 chipio_8051_set_address(codec, addr);
2000 *data = chipio_8051_get_data(codec);
2001 }
2002
chipio_8051_write_pll_pmu(struct hda_codec * codec,unsigned int addr,unsigned int data)2003 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
2004 unsigned int addr, unsigned int data)
2005 {
2006 struct ca0132_spec *spec = codec->spec;
2007
2008 mutex_lock(&spec->chipio_mutex);
2009
2010 chipio_8051_set_address(codec, addr & 0xff);
2011 chipio_8051_set_data_pll(codec, data);
2012
2013 mutex_unlock(&spec->chipio_mutex);
2014 }
2015
chipio_8051_write_pll_pmu_no_mutex(struct hda_codec * codec,unsigned int addr,unsigned int data)2016 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
2017 unsigned int addr, unsigned int data)
2018 {
2019 chipio_8051_set_address(codec, addr & 0xff);
2020 chipio_8051_set_data_pll(codec, data);
2021 }
2022
2023 /*
2024 * Enable clocks.
2025 */
chipio_enable_clocks(struct hda_codec * codec)2026 static void chipio_enable_clocks(struct hda_codec *codec)
2027 {
2028 struct ca0132_spec *spec = codec->spec;
2029
2030 mutex_lock(&spec->chipio_mutex);
2031
2032 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2033 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2034 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2035
2036 mutex_unlock(&spec->chipio_mutex);
2037 }
2038
2039 /*
2040 * CA0132 DSP IO stuffs
2041 */
dspio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)2042 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2043 unsigned int data)
2044 {
2045 int res;
2046 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2047
2048 /* send bits of data specified by reg to dsp */
2049 do {
2050 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2051 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2052 return res;
2053 msleep(20);
2054 } while (time_before(jiffies, timeout));
2055
2056 return -EIO;
2057 }
2058
2059 /*
2060 * Wait for DSP to be ready for commands
2061 */
dspio_write_wait(struct hda_codec * codec)2062 static void dspio_write_wait(struct hda_codec *codec)
2063 {
2064 int status;
2065 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2066
2067 do {
2068 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2069 VENDOR_DSPIO_STATUS, 0);
2070 if ((status == VENDOR_STATUS_DSPIO_OK) ||
2071 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2072 break;
2073 msleep(1);
2074 } while (time_before(jiffies, timeout));
2075 }
2076
2077 /*
2078 * Write SCP data to DSP
2079 */
dspio_write(struct hda_codec * codec,unsigned int scp_data)2080 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2081 {
2082 struct ca0132_spec *spec = codec->spec;
2083 int status;
2084
2085 dspio_write_wait(codec);
2086
2087 mutex_lock(&spec->chipio_mutex);
2088 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2089 scp_data & 0xffff);
2090 if (status < 0)
2091 goto error;
2092
2093 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2094 scp_data >> 16);
2095 if (status < 0)
2096 goto error;
2097
2098 /* OK, now check if the write itself has executed*/
2099 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2100 VENDOR_DSPIO_STATUS, 0);
2101 error:
2102 mutex_unlock(&spec->chipio_mutex);
2103
2104 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2105 -EIO : 0;
2106 }
2107
2108 /*
2109 * Write multiple SCP data to DSP
2110 */
dspio_write_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int size)2111 static int dspio_write_multiple(struct hda_codec *codec,
2112 unsigned int *buffer, unsigned int size)
2113 {
2114 int status = 0;
2115 unsigned int count;
2116
2117 if (buffer == NULL)
2118 return -EINVAL;
2119
2120 count = 0;
2121 while (count < size) {
2122 status = dspio_write(codec, *buffer++);
2123 if (status != 0)
2124 break;
2125 count++;
2126 }
2127
2128 return status;
2129 }
2130
dspio_read(struct hda_codec * codec,unsigned int * data)2131 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2132 {
2133 int status;
2134
2135 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2136 if (status == -EIO)
2137 return status;
2138
2139 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2140 if (status == -EIO ||
2141 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2142 return -EIO;
2143
2144 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2145 VENDOR_DSPIO_SCP_READ_DATA, 0);
2146
2147 return 0;
2148 }
2149
dspio_read_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int * buf_size,unsigned int size_count)2150 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2151 unsigned int *buf_size, unsigned int size_count)
2152 {
2153 int status = 0;
2154 unsigned int size = *buf_size;
2155 unsigned int count;
2156 unsigned int skip_count;
2157 unsigned int dummy;
2158
2159 if (buffer == NULL)
2160 return -1;
2161
2162 count = 0;
2163 while (count < size && count < size_count) {
2164 status = dspio_read(codec, buffer++);
2165 if (status != 0)
2166 break;
2167 count++;
2168 }
2169
2170 skip_count = count;
2171 if (status == 0) {
2172 while (skip_count < size) {
2173 status = dspio_read(codec, &dummy);
2174 if (status != 0)
2175 break;
2176 skip_count++;
2177 }
2178 }
2179 *buf_size = count;
2180
2181 return status;
2182 }
2183
2184 /*
2185 * Construct the SCP header using corresponding fields
2186 */
2187 static inline unsigned int
make_scp_header(unsigned int target_id,unsigned int source_id,unsigned int get_flag,unsigned int req,unsigned int device_flag,unsigned int resp_flag,unsigned int error_flag,unsigned int data_size)2188 make_scp_header(unsigned int target_id, unsigned int source_id,
2189 unsigned int get_flag, unsigned int req,
2190 unsigned int device_flag, unsigned int resp_flag,
2191 unsigned int error_flag, unsigned int data_size)
2192 {
2193 unsigned int header = 0;
2194
2195 header = (data_size & 0x1f) << 27;
2196 header |= (error_flag & 0x01) << 26;
2197 header |= (resp_flag & 0x01) << 25;
2198 header |= (device_flag & 0x01) << 24;
2199 header |= (req & 0x7f) << 17;
2200 header |= (get_flag & 0x01) << 16;
2201 header |= (source_id & 0xff) << 8;
2202 header |= target_id & 0xff;
2203
2204 return header;
2205 }
2206
2207 /*
2208 * Extract corresponding fields from SCP header
2209 */
2210 static inline void
extract_scp_header(unsigned int header,unsigned int * target_id,unsigned int * source_id,unsigned int * get_flag,unsigned int * req,unsigned int * device_flag,unsigned int * resp_flag,unsigned int * error_flag,unsigned int * data_size)2211 extract_scp_header(unsigned int header,
2212 unsigned int *target_id, unsigned int *source_id,
2213 unsigned int *get_flag, unsigned int *req,
2214 unsigned int *device_flag, unsigned int *resp_flag,
2215 unsigned int *error_flag, unsigned int *data_size)
2216 {
2217 if (data_size)
2218 *data_size = (header >> 27) & 0x1f;
2219 if (error_flag)
2220 *error_flag = (header >> 26) & 0x01;
2221 if (resp_flag)
2222 *resp_flag = (header >> 25) & 0x01;
2223 if (device_flag)
2224 *device_flag = (header >> 24) & 0x01;
2225 if (req)
2226 *req = (header >> 17) & 0x7f;
2227 if (get_flag)
2228 *get_flag = (header >> 16) & 0x01;
2229 if (source_id)
2230 *source_id = (header >> 8) & 0xff;
2231 if (target_id)
2232 *target_id = header & 0xff;
2233 }
2234
2235 #define SCP_MAX_DATA_WORDS (16)
2236
2237 /* Structure to contain any SCP message */
2238 struct scp_msg {
2239 unsigned int hdr;
2240 unsigned int data[SCP_MAX_DATA_WORDS];
2241 };
2242
dspio_clear_response_queue(struct hda_codec * codec)2243 static void dspio_clear_response_queue(struct hda_codec *codec)
2244 {
2245 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2246 unsigned int dummy = 0;
2247 int status;
2248
2249 /* clear all from the response queue */
2250 do {
2251 status = dspio_read(codec, &dummy);
2252 } while (status == 0 && time_before(jiffies, timeout));
2253 }
2254
dspio_get_response_data(struct hda_codec * codec)2255 static int dspio_get_response_data(struct hda_codec *codec)
2256 {
2257 struct ca0132_spec *spec = codec->spec;
2258 unsigned int data = 0;
2259 unsigned int count;
2260
2261 if (dspio_read(codec, &data) < 0)
2262 return -EIO;
2263
2264 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2265 spec->scp_resp_header = data;
2266 spec->scp_resp_count = data >> 27;
2267 count = spec->wait_num_data;
2268 dspio_read_multiple(codec, spec->scp_resp_data,
2269 &spec->scp_resp_count, count);
2270 return 0;
2271 }
2272
2273 return -EIO;
2274 }
2275
2276 /*
2277 * Send SCP message to DSP
2278 */
dspio_send_scp_message(struct hda_codec * codec,unsigned char * send_buf,unsigned int send_buf_size,unsigned char * return_buf,unsigned int return_buf_size,unsigned int * bytes_returned)2279 static int dspio_send_scp_message(struct hda_codec *codec,
2280 unsigned char *send_buf,
2281 unsigned int send_buf_size,
2282 unsigned char *return_buf,
2283 unsigned int return_buf_size,
2284 unsigned int *bytes_returned)
2285 {
2286 struct ca0132_spec *spec = codec->spec;
2287 int status;
2288 unsigned int scp_send_size = 0;
2289 unsigned int total_size;
2290 bool waiting_for_resp = false;
2291 unsigned int header;
2292 struct scp_msg *ret_msg;
2293 unsigned int resp_src_id, resp_target_id;
2294 unsigned int data_size, src_id, target_id, get_flag, device_flag;
2295
2296 if (bytes_returned)
2297 *bytes_returned = 0;
2298
2299 /* get scp header from buffer */
2300 header = *((unsigned int *)send_buf);
2301 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2302 &device_flag, NULL, NULL, &data_size);
2303 scp_send_size = data_size + 1;
2304 total_size = (scp_send_size * 4);
2305
2306 if (send_buf_size < total_size)
2307 return -EINVAL;
2308
2309 if (get_flag || device_flag) {
2310 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2311 return -EINVAL;
2312
2313 spec->wait_scp_header = *((unsigned int *)send_buf);
2314
2315 /* swap source id with target id */
2316 resp_target_id = src_id;
2317 resp_src_id = target_id;
2318 spec->wait_scp_header &= 0xffff0000;
2319 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2320 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2321 spec->wait_scp = 1;
2322 waiting_for_resp = true;
2323 }
2324
2325 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2326 scp_send_size);
2327 if (status < 0) {
2328 spec->wait_scp = 0;
2329 return status;
2330 }
2331
2332 if (waiting_for_resp) {
2333 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2334 memset(return_buf, 0, return_buf_size);
2335 do {
2336 msleep(20);
2337 } while (spec->wait_scp && time_before(jiffies, timeout));
2338 waiting_for_resp = false;
2339 if (!spec->wait_scp) {
2340 ret_msg = (struct scp_msg *)return_buf;
2341 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2342 memcpy(&ret_msg->data, spec->scp_resp_data,
2343 spec->wait_num_data);
2344 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2345 status = 0;
2346 } else {
2347 status = -EIO;
2348 }
2349 spec->wait_scp = 0;
2350 }
2351
2352 return status;
2353 }
2354
2355 /**
2356 * dspio_scp - Prepare and send the SCP message to DSP
2357 * @codec: the HDA codec
2358 * @mod_id: ID of the DSP module to send the command
2359 * @src_id: ID of the source
2360 * @req: ID of request to send to the DSP module
2361 * @dir: SET or GET
2362 * @data: pointer to the data to send with the request, request specific
2363 * @len: length of the data, in bytes
2364 * @reply: point to the buffer to hold data returned for a reply
2365 * @reply_len: length of the reply buffer returned from GET
2366 *
2367 * Returns zero or a negative error code.
2368 */
dspio_scp(struct hda_codec * codec,int mod_id,int src_id,int req,int dir,const void * data,unsigned int len,void * reply,unsigned int * reply_len)2369 static int dspio_scp(struct hda_codec *codec,
2370 int mod_id, int src_id, int req, int dir, const void *data,
2371 unsigned int len, void *reply, unsigned int *reply_len)
2372 {
2373 int status = 0;
2374 struct scp_msg scp_send, scp_reply;
2375 unsigned int ret_bytes, send_size, ret_size;
2376 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2377 unsigned int reply_data_size;
2378
2379 memset(&scp_send, 0, sizeof(scp_send));
2380 memset(&scp_reply, 0, sizeof(scp_reply));
2381
2382 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2383 return -EINVAL;
2384
2385 if (dir == SCP_GET && reply == NULL) {
2386 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2387 return -EINVAL;
2388 }
2389
2390 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2391 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2392 return -EINVAL;
2393 }
2394
2395 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2396 0, 0, 0, len/sizeof(unsigned int));
2397 if (data != NULL && len > 0) {
2398 len = min((unsigned int)(sizeof(scp_send.data)), len);
2399 memcpy(scp_send.data, data, len);
2400 }
2401
2402 ret_bytes = 0;
2403 send_size = sizeof(unsigned int) + len;
2404 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2405 send_size, (unsigned char *)&scp_reply,
2406 sizeof(scp_reply), &ret_bytes);
2407
2408 if (status < 0) {
2409 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2410 return status;
2411 }
2412
2413 /* extract send and reply headers members */
2414 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2415 NULL, NULL, NULL, NULL, NULL);
2416 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2417 &reply_resp_flag, &reply_error_flag,
2418 &reply_data_size);
2419
2420 if (!send_get_flag)
2421 return 0;
2422
2423 if (reply_resp_flag && !reply_error_flag) {
2424 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2425 / sizeof(unsigned int);
2426
2427 if (*reply_len < ret_size*sizeof(unsigned int)) {
2428 codec_dbg(codec, "reply too long for buf\n");
2429 return -EINVAL;
2430 } else if (ret_size != reply_data_size) {
2431 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2432 return -EINVAL;
2433 } else if (!reply) {
2434 codec_dbg(codec, "NULL reply\n");
2435 return -EINVAL;
2436 } else {
2437 *reply_len = ret_size*sizeof(unsigned int);
2438 memcpy(reply, scp_reply.data, *reply_len);
2439 }
2440 } else {
2441 codec_dbg(codec, "reply ill-formed or errflag set\n");
2442 return -EIO;
2443 }
2444
2445 return status;
2446 }
2447
2448 /*
2449 * Set DSP parameters
2450 */
dspio_set_param(struct hda_codec * codec,int mod_id,int src_id,int req,const void * data,unsigned int len)2451 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2452 int src_id, int req, const void *data, unsigned int len)
2453 {
2454 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2455 NULL);
2456 }
2457
dspio_set_uint_param(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2458 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2459 int req, const unsigned int data)
2460 {
2461 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2462 sizeof(unsigned int));
2463 }
2464
2465 /*
2466 * Allocate a DSP DMA channel via an SCP message
2467 */
dspio_alloc_dma_chan(struct hda_codec * codec,unsigned int * dma_chan)2468 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2469 {
2470 int status = 0;
2471 unsigned int size = sizeof(*dma_chan);
2472
2473 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2474 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2475 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2476 dma_chan, &size);
2477
2478 if (status < 0) {
2479 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2480 return status;
2481 }
2482
2483 if ((*dma_chan + 1) == 0) {
2484 codec_dbg(codec, "no free dma channels to allocate\n");
2485 return -EBUSY;
2486 }
2487
2488 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2489 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2490
2491 return status;
2492 }
2493
2494 /*
2495 * Free a DSP DMA via an SCP message
2496 */
dspio_free_dma_chan(struct hda_codec * codec,unsigned int dma_chan)2497 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2498 {
2499 int status = 0;
2500 unsigned int dummy = 0;
2501
2502 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2503 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2504
2505 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2506 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2507 sizeof(dma_chan), NULL, &dummy);
2508
2509 if (status < 0) {
2510 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2511 return status;
2512 }
2513
2514 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2515
2516 return status;
2517 }
2518
2519 /*
2520 * (Re)start the DSP
2521 */
dsp_set_run_state(struct hda_codec * codec)2522 static int dsp_set_run_state(struct hda_codec *codec)
2523 {
2524 unsigned int dbg_ctrl_reg;
2525 unsigned int halt_state;
2526 int err;
2527
2528 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2529 if (err < 0)
2530 return err;
2531
2532 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2533 DSP_DBGCNTL_STATE_LOBIT;
2534
2535 if (halt_state != 0) {
2536 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2537 DSP_DBGCNTL_SS_MASK);
2538 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2539 dbg_ctrl_reg);
2540 if (err < 0)
2541 return err;
2542
2543 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2544 DSP_DBGCNTL_EXEC_MASK;
2545 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2546 dbg_ctrl_reg);
2547 if (err < 0)
2548 return err;
2549 }
2550
2551 return 0;
2552 }
2553
2554 /*
2555 * Reset the DSP
2556 */
dsp_reset(struct hda_codec * codec)2557 static int dsp_reset(struct hda_codec *codec)
2558 {
2559 unsigned int res;
2560 int retry = 20;
2561
2562 codec_dbg(codec, "dsp_reset\n");
2563 do {
2564 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2565 retry--;
2566 } while (res == -EIO && retry);
2567
2568 if (!retry) {
2569 codec_dbg(codec, "dsp_reset timeout\n");
2570 return -EIO;
2571 }
2572
2573 return 0;
2574 }
2575
2576 /*
2577 * Convert chip address to DSP address
2578 */
dsp_chip_to_dsp_addx(unsigned int chip_addx,bool * code,bool * yram)2579 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2580 bool *code, bool *yram)
2581 {
2582 *code = *yram = false;
2583
2584 if (UC_RANGE(chip_addx, 1)) {
2585 *code = true;
2586 return UC_OFF(chip_addx);
2587 } else if (X_RANGE_ALL(chip_addx, 1)) {
2588 return X_OFF(chip_addx);
2589 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2590 *yram = true;
2591 return Y_OFF(chip_addx);
2592 }
2593
2594 return INVALID_CHIP_ADDRESS;
2595 }
2596
2597 /*
2598 * Check if the DSP DMA is active
2599 */
dsp_is_dma_active(struct hda_codec * codec,unsigned int dma_chan)2600 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2601 {
2602 unsigned int dma_chnlstart_reg;
2603
2604 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2605
2606 return ((dma_chnlstart_reg & (1 <<
2607 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2608 }
2609
dsp_dma_setup_common(struct hda_codec * codec,unsigned int chip_addx,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)2610 static int dsp_dma_setup_common(struct hda_codec *codec,
2611 unsigned int chip_addx,
2612 unsigned int dma_chan,
2613 unsigned int port_map_mask,
2614 bool ovly)
2615 {
2616 int status = 0;
2617 unsigned int chnl_prop;
2618 unsigned int dsp_addx;
2619 unsigned int active;
2620 bool code, yram;
2621
2622 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2623
2624 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2625 codec_dbg(codec, "dma chan num invalid\n");
2626 return -EINVAL;
2627 }
2628
2629 if (dsp_is_dma_active(codec, dma_chan)) {
2630 codec_dbg(codec, "dma already active\n");
2631 return -EBUSY;
2632 }
2633
2634 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2635
2636 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2637 codec_dbg(codec, "invalid chip addr\n");
2638 return -ENXIO;
2639 }
2640
2641 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2642 active = 0;
2643
2644 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2645
2646 if (ovly) {
2647 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2648 &chnl_prop);
2649
2650 if (status < 0) {
2651 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2652 return status;
2653 }
2654 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2655 }
2656
2657 if (!code)
2658 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2659 else
2660 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2661
2662 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2663
2664 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2665 if (status < 0) {
2666 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2667 return status;
2668 }
2669 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2670
2671 if (ovly) {
2672 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2673 &active);
2674
2675 if (status < 0) {
2676 codec_dbg(codec, "read ACTIVE Reg fail\n");
2677 return status;
2678 }
2679 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2680 }
2681
2682 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2683 DSPDMAC_ACTIVE_AAR_MASK;
2684
2685 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2686 if (status < 0) {
2687 codec_dbg(codec, "write ACTIVE Reg fail\n");
2688 return status;
2689 }
2690
2691 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2692
2693 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2694 port_map_mask);
2695 if (status < 0) {
2696 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2697 return status;
2698 }
2699 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2700
2701 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2702 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2703 if (status < 0) {
2704 codec_dbg(codec, "write IRQCNT Reg fail\n");
2705 return status;
2706 }
2707 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2708
2709 codec_dbg(codec,
2710 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2711 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2712 chip_addx, dsp_addx, dma_chan,
2713 port_map_mask, chnl_prop, active);
2714
2715 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2716
2717 return 0;
2718 }
2719
2720 /*
2721 * Setup the DSP DMA per-transfer-specific registers
2722 */
dsp_dma_setup(struct hda_codec * codec,unsigned int chip_addx,unsigned int count,unsigned int dma_chan)2723 static int dsp_dma_setup(struct hda_codec *codec,
2724 unsigned int chip_addx,
2725 unsigned int count,
2726 unsigned int dma_chan)
2727 {
2728 int status = 0;
2729 bool code, yram;
2730 unsigned int dsp_addx;
2731 unsigned int addr_field;
2732 unsigned int incr_field;
2733 unsigned int base_cnt;
2734 unsigned int cur_cnt;
2735 unsigned int dma_cfg = 0;
2736 unsigned int adr_ofs = 0;
2737 unsigned int xfr_cnt = 0;
2738 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2739 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2740
2741 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2742
2743 if (count > max_dma_count) {
2744 codec_dbg(codec, "count too big\n");
2745 return -EINVAL;
2746 }
2747
2748 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2749 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2750 codec_dbg(codec, "invalid chip addr\n");
2751 return -ENXIO;
2752 }
2753
2754 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2755
2756 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2757 incr_field = 0;
2758
2759 if (!code) {
2760 addr_field <<= 1;
2761 if (yram)
2762 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2763
2764 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2765 }
2766
2767 dma_cfg = addr_field + incr_field;
2768 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2769 dma_cfg);
2770 if (status < 0) {
2771 codec_dbg(codec, "write DMACFG Reg fail\n");
2772 return status;
2773 }
2774 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2775
2776 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2777 (code ? 0 : 1));
2778
2779 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2780 adr_ofs);
2781 if (status < 0) {
2782 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2783 return status;
2784 }
2785 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2786
2787 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2788
2789 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2790
2791 xfr_cnt = base_cnt | cur_cnt;
2792
2793 status = chipio_write(codec,
2794 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2795 if (status < 0) {
2796 codec_dbg(codec, "write XFRCNT Reg fail\n");
2797 return status;
2798 }
2799 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2800
2801 codec_dbg(codec,
2802 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2803 "ADROFS=0x%x, XFRCNT=0x%x\n",
2804 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2805
2806 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2807
2808 return 0;
2809 }
2810
2811 /*
2812 * Start the DSP DMA
2813 */
dsp_dma_start(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2814 static int dsp_dma_start(struct hda_codec *codec,
2815 unsigned int dma_chan, bool ovly)
2816 {
2817 unsigned int reg = 0;
2818 int status = 0;
2819
2820 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2821
2822 if (ovly) {
2823 status = chipio_read(codec,
2824 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2825
2826 if (status < 0) {
2827 codec_dbg(codec, "read CHNLSTART reg fail\n");
2828 return status;
2829 }
2830 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2831
2832 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2833 DSPDMAC_CHNLSTART_DIS_MASK);
2834 }
2835
2836 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2837 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2838 if (status < 0) {
2839 codec_dbg(codec, "write CHNLSTART reg fail\n");
2840 return status;
2841 }
2842 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2843
2844 return status;
2845 }
2846
2847 /*
2848 * Stop the DSP DMA
2849 */
dsp_dma_stop(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2850 static int dsp_dma_stop(struct hda_codec *codec,
2851 unsigned int dma_chan, bool ovly)
2852 {
2853 unsigned int reg = 0;
2854 int status = 0;
2855
2856 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2857
2858 if (ovly) {
2859 status = chipio_read(codec,
2860 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2861
2862 if (status < 0) {
2863 codec_dbg(codec, "read CHNLSTART reg fail\n");
2864 return status;
2865 }
2866 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2867 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2868 DSPDMAC_CHNLSTART_DIS_MASK);
2869 }
2870
2871 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2872 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2873 if (status < 0) {
2874 codec_dbg(codec, "write CHNLSTART reg fail\n");
2875 return status;
2876 }
2877 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2878
2879 return status;
2880 }
2881
2882 /**
2883 * dsp_allocate_router_ports - Allocate router ports
2884 *
2885 * @codec: the HDA codec
2886 * @num_chans: number of channels in the stream
2887 * @ports_per_channel: number of ports per channel
2888 * @start_device: start device
2889 * @port_map: pointer to the port list to hold the allocated ports
2890 *
2891 * Returns zero or a negative error code.
2892 */
dsp_allocate_router_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int ports_per_channel,unsigned int start_device,unsigned int * port_map)2893 static int dsp_allocate_router_ports(struct hda_codec *codec,
2894 unsigned int num_chans,
2895 unsigned int ports_per_channel,
2896 unsigned int start_device,
2897 unsigned int *port_map)
2898 {
2899 int status = 0;
2900 int res;
2901 u8 val;
2902
2903 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2904 if (status < 0)
2905 return status;
2906
2907 val = start_device << 6;
2908 val |= (ports_per_channel - 1) << 4;
2909 val |= num_chans - 1;
2910
2911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2912 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2913 val);
2914
2915 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2916 VENDOR_CHIPIO_PORT_ALLOC_SET,
2917 MEM_CONNID_DSP);
2918
2919 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2920 if (status < 0)
2921 return status;
2922
2923 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2924 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2925
2926 *port_map = res;
2927
2928 return (res < 0) ? res : 0;
2929 }
2930
2931 /*
2932 * Free router ports
2933 */
dsp_free_router_ports(struct hda_codec * codec)2934 static int dsp_free_router_ports(struct hda_codec *codec)
2935 {
2936 int status = 0;
2937
2938 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2939 if (status < 0)
2940 return status;
2941
2942 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2943 VENDOR_CHIPIO_PORT_FREE_SET,
2944 MEM_CONNID_DSP);
2945
2946 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2947
2948 return status;
2949 }
2950
2951 /*
2952 * Allocate DSP ports for the download stream
2953 */
dsp_allocate_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int rate_multi,unsigned int * port_map)2954 static int dsp_allocate_ports(struct hda_codec *codec,
2955 unsigned int num_chans,
2956 unsigned int rate_multi, unsigned int *port_map)
2957 {
2958 int status;
2959
2960 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2961
2962 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2963 codec_dbg(codec, "bad rate multiple\n");
2964 return -EINVAL;
2965 }
2966
2967 status = dsp_allocate_router_ports(codec, num_chans,
2968 rate_multi, 0, port_map);
2969
2970 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2971
2972 return status;
2973 }
2974
dsp_allocate_ports_format(struct hda_codec * codec,const unsigned short fmt,unsigned int * port_map)2975 static int dsp_allocate_ports_format(struct hda_codec *codec,
2976 const unsigned short fmt,
2977 unsigned int *port_map)
2978 {
2979 unsigned int num_chans;
2980
2981 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2982 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2983 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2984
2985 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2986 codec_dbg(codec, "bad rate multiple\n");
2987 return -EINVAL;
2988 }
2989
2990 num_chans = get_hdafmt_chs(fmt) + 1;
2991
2992 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2993 }
2994
2995 /*
2996 * free DSP ports
2997 */
dsp_free_ports(struct hda_codec * codec)2998 static int dsp_free_ports(struct hda_codec *codec)
2999 {
3000 int status;
3001
3002 codec_dbg(codec, " dsp_free_ports() -- begin\n");
3003
3004 status = dsp_free_router_ports(codec);
3005 if (status < 0) {
3006 codec_dbg(codec, "free router ports fail\n");
3007 return status;
3008 }
3009 codec_dbg(codec, " dsp_free_ports() -- complete\n");
3010
3011 return status;
3012 }
3013
3014 /*
3015 * HDA DMA engine stuffs for DSP code download
3016 */
3017 struct dma_engine {
3018 struct hda_codec *codec;
3019 unsigned short m_converter_format;
3020 struct snd_dma_buffer *dmab;
3021 unsigned int buf_size;
3022 };
3023
3024
3025 enum dma_state {
3026 DMA_STATE_STOP = 0,
3027 DMA_STATE_RUN = 1
3028 };
3029
dma_convert_to_hda_format(struct hda_codec * codec,unsigned int sample_rate,unsigned short channels,unsigned short * hda_format)3030 static int dma_convert_to_hda_format(struct hda_codec *codec,
3031 unsigned int sample_rate,
3032 unsigned short channels,
3033 unsigned short *hda_format)
3034 {
3035 unsigned int format_val;
3036
3037 format_val = snd_hdac_stream_format(channels, 32, sample_rate);
3038
3039 if (hda_format)
3040 *hda_format = (unsigned short)format_val;
3041
3042 return 0;
3043 }
3044
3045 /*
3046 * Reset DMA for DSP download
3047 */
dma_reset(struct dma_engine * dma)3048 static int dma_reset(struct dma_engine *dma)
3049 {
3050 struct hda_codec *codec = dma->codec;
3051 struct ca0132_spec *spec = codec->spec;
3052 int status;
3053
3054 if (dma->dmab->area)
3055 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3056
3057 status = snd_hda_codec_load_dsp_prepare(codec,
3058 dma->m_converter_format,
3059 dma->buf_size,
3060 dma->dmab);
3061 if (status < 0)
3062 return status;
3063 spec->dsp_stream_id = status;
3064 return 0;
3065 }
3066
dma_set_state(struct dma_engine * dma,enum dma_state state)3067 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3068 {
3069 bool cmd;
3070
3071 switch (state) {
3072 case DMA_STATE_STOP:
3073 cmd = false;
3074 break;
3075 case DMA_STATE_RUN:
3076 cmd = true;
3077 break;
3078 default:
3079 return 0;
3080 }
3081
3082 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3083 return 0;
3084 }
3085
dma_get_buffer_size(struct dma_engine * dma)3086 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3087 {
3088 return dma->dmab->bytes;
3089 }
3090
dma_get_buffer_addr(struct dma_engine * dma)3091 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3092 {
3093 return dma->dmab->area;
3094 }
3095
dma_xfer(struct dma_engine * dma,const unsigned int * data,unsigned int count)3096 static int dma_xfer(struct dma_engine *dma,
3097 const unsigned int *data,
3098 unsigned int count)
3099 {
3100 memcpy(dma->dmab->area, data, count);
3101 return 0;
3102 }
3103
dma_get_converter_format(struct dma_engine * dma,unsigned short * format)3104 static void dma_get_converter_format(
3105 struct dma_engine *dma,
3106 unsigned short *format)
3107 {
3108 if (format)
3109 *format = dma->m_converter_format;
3110 }
3111
dma_get_stream_id(struct dma_engine * dma)3112 static unsigned int dma_get_stream_id(struct dma_engine *dma)
3113 {
3114 struct ca0132_spec *spec = dma->codec->spec;
3115
3116 return spec->dsp_stream_id;
3117 }
3118
3119 struct dsp_image_seg {
3120 u32 magic;
3121 u32 chip_addr;
3122 u32 count;
3123 u32 data[];
3124 };
3125
3126 static const u32 g_magic_value = 0x4c46584d;
3127 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3128
is_valid(const struct dsp_image_seg * p)3129 static bool is_valid(const struct dsp_image_seg *p)
3130 {
3131 return p->magic == g_magic_value;
3132 }
3133
is_hci_prog_list_seg(const struct dsp_image_seg * p)3134 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3135 {
3136 return g_chip_addr_magic_value == p->chip_addr;
3137 }
3138
is_last(const struct dsp_image_seg * p)3139 static bool is_last(const struct dsp_image_seg *p)
3140 {
3141 return p->count == 0;
3142 }
3143
dsp_sizeof(const struct dsp_image_seg * p)3144 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3145 {
3146 return struct_size(p, data, p->count);
3147 }
3148
get_next_seg_ptr(const struct dsp_image_seg * p)3149 static const struct dsp_image_seg *get_next_seg_ptr(
3150 const struct dsp_image_seg *p)
3151 {
3152 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3153 }
3154
3155 /*
3156 * CA0132 chip DSP transfer stuffs. For DSP download.
3157 */
3158 #define INVALID_DMA_CHANNEL (~0U)
3159
3160 /*
3161 * Program a list of address/data pairs via the ChipIO widget.
3162 * The segment data is in the format of successive pairs of words.
3163 * These are repeated as indicated by the segment's count field.
3164 */
dspxfr_hci_write(struct hda_codec * codec,const struct dsp_image_seg * fls)3165 static int dspxfr_hci_write(struct hda_codec *codec,
3166 const struct dsp_image_seg *fls)
3167 {
3168 int status;
3169 const u32 *data;
3170 unsigned int count;
3171
3172 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3173 codec_dbg(codec, "hci_write invalid params\n");
3174 return -EINVAL;
3175 }
3176
3177 count = fls->count;
3178 data = (u32 *)(fls->data);
3179 while (count >= 2) {
3180 status = chipio_write(codec, data[0], data[1]);
3181 if (status < 0) {
3182 codec_dbg(codec, "hci_write chipio failed\n");
3183 return status;
3184 }
3185 count -= 2;
3186 data += 2;
3187 }
3188 return 0;
3189 }
3190
3191 /**
3192 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3193 *
3194 * @codec: the HDA codec
3195 * @fls: pointer to a fast load image
3196 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3197 * no relocation
3198 * @dma_engine: pointer to DMA engine to be used for DSP download
3199 * @dma_chan: The number of DMA channels used for DSP download
3200 * @port_map_mask: port mapping
3201 * @ovly: TRUE if overlay format is required
3202 *
3203 * Returns zero or a negative error code.
3204 */
dspxfr_one_seg(struct hda_codec * codec,const struct dsp_image_seg * fls,unsigned int reloc,struct dma_engine * dma_engine,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)3205 static int dspxfr_one_seg(struct hda_codec *codec,
3206 const struct dsp_image_seg *fls,
3207 unsigned int reloc,
3208 struct dma_engine *dma_engine,
3209 unsigned int dma_chan,
3210 unsigned int port_map_mask,
3211 bool ovly)
3212 {
3213 int status = 0;
3214 bool comm_dma_setup_done = false;
3215 const unsigned int *data;
3216 unsigned int chip_addx;
3217 unsigned int words_to_write;
3218 unsigned int buffer_size_words;
3219 unsigned char *buffer_addx;
3220 unsigned short hda_format;
3221 unsigned int sample_rate_div;
3222 unsigned int sample_rate_mul;
3223 unsigned int num_chans;
3224 unsigned int hda_frame_size_words;
3225 unsigned int remainder_words;
3226 const u32 *data_remainder;
3227 u32 chip_addx_remainder;
3228 unsigned int run_size_words;
3229 const struct dsp_image_seg *hci_write = NULL;
3230 unsigned long timeout;
3231 bool dma_active;
3232
3233 if (fls == NULL)
3234 return -EINVAL;
3235 if (is_hci_prog_list_seg(fls)) {
3236 hci_write = fls;
3237 fls = get_next_seg_ptr(fls);
3238 }
3239
3240 if (hci_write && (!fls || is_last(fls))) {
3241 codec_dbg(codec, "hci_write\n");
3242 return dspxfr_hci_write(codec, hci_write);
3243 }
3244
3245 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3246 codec_dbg(codec, "Invalid Params\n");
3247 return -EINVAL;
3248 }
3249
3250 data = fls->data;
3251 chip_addx = fls->chip_addr;
3252 words_to_write = fls->count;
3253
3254 if (!words_to_write)
3255 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3256 if (reloc)
3257 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3258
3259 if (!UC_RANGE(chip_addx, words_to_write) &&
3260 !X_RANGE_ALL(chip_addx, words_to_write) &&
3261 !Y_RANGE_ALL(chip_addx, words_to_write)) {
3262 codec_dbg(codec, "Invalid chip_addx Params\n");
3263 return -EINVAL;
3264 }
3265
3266 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3267 sizeof(u32);
3268
3269 buffer_addx = dma_get_buffer_addr(dma_engine);
3270
3271 if (buffer_addx == NULL) {
3272 codec_dbg(codec, "dma_engine buffer NULL\n");
3273 return -EINVAL;
3274 }
3275
3276 dma_get_converter_format(dma_engine, &hda_format);
3277 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3278 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3279 num_chans = get_hdafmt_chs(hda_format) + 1;
3280
3281 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3282 (num_chans * sample_rate_mul / sample_rate_div));
3283
3284 if (hda_frame_size_words == 0) {
3285 codec_dbg(codec, "frmsz zero\n");
3286 return -EINVAL;
3287 }
3288
3289 buffer_size_words = min(buffer_size_words,
3290 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3291 65536 : 32768));
3292 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3293 codec_dbg(codec,
3294 "chpadr=0x%08x frmsz=%u nchan=%u "
3295 "rate_mul=%u div=%u bufsz=%u\n",
3296 chip_addx, hda_frame_size_words, num_chans,
3297 sample_rate_mul, sample_rate_div, buffer_size_words);
3298
3299 if (buffer_size_words < hda_frame_size_words) {
3300 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3301 return -EINVAL;
3302 }
3303
3304 remainder_words = words_to_write % hda_frame_size_words;
3305 data_remainder = data;
3306 chip_addx_remainder = chip_addx;
3307
3308 data += remainder_words;
3309 chip_addx += remainder_words*sizeof(u32);
3310 words_to_write -= remainder_words;
3311
3312 while (words_to_write != 0) {
3313 run_size_words = min(buffer_size_words, words_to_write);
3314 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3315 words_to_write, run_size_words, remainder_words);
3316 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3317 if (!comm_dma_setup_done) {
3318 status = dsp_dma_stop(codec, dma_chan, ovly);
3319 if (status < 0)
3320 return status;
3321 status = dsp_dma_setup_common(codec, chip_addx,
3322 dma_chan, port_map_mask, ovly);
3323 if (status < 0)
3324 return status;
3325 comm_dma_setup_done = true;
3326 }
3327
3328 status = dsp_dma_setup(codec, chip_addx,
3329 run_size_words, dma_chan);
3330 if (status < 0)
3331 return status;
3332 status = dsp_dma_start(codec, dma_chan, ovly);
3333 if (status < 0)
3334 return status;
3335 if (!dsp_is_dma_active(codec, dma_chan)) {
3336 codec_dbg(codec, "dspxfr:DMA did not start\n");
3337 return -EIO;
3338 }
3339 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3340 if (status < 0)
3341 return status;
3342 if (remainder_words != 0) {
3343 status = chipio_write_multiple(codec,
3344 chip_addx_remainder,
3345 data_remainder,
3346 remainder_words);
3347 if (status < 0)
3348 return status;
3349 remainder_words = 0;
3350 }
3351 if (hci_write) {
3352 status = dspxfr_hci_write(codec, hci_write);
3353 if (status < 0)
3354 return status;
3355 hci_write = NULL;
3356 }
3357
3358 timeout = jiffies + msecs_to_jiffies(2000);
3359 do {
3360 dma_active = dsp_is_dma_active(codec, dma_chan);
3361 if (!dma_active)
3362 break;
3363 msleep(20);
3364 } while (time_before(jiffies, timeout));
3365 if (dma_active)
3366 break;
3367
3368 codec_dbg(codec, "+++++ DMA complete\n");
3369 dma_set_state(dma_engine, DMA_STATE_STOP);
3370 status = dma_reset(dma_engine);
3371
3372 if (status < 0)
3373 return status;
3374
3375 data += run_size_words;
3376 chip_addx += run_size_words*sizeof(u32);
3377 words_to_write -= run_size_words;
3378 }
3379
3380 if (remainder_words != 0) {
3381 status = chipio_write_multiple(codec, chip_addx_remainder,
3382 data_remainder, remainder_words);
3383 }
3384
3385 return status;
3386 }
3387
3388 /**
3389 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3390 *
3391 * @codec: the HDA codec
3392 * @fls_data: pointer to a fast load image
3393 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3394 * no relocation
3395 * @sample_rate: sampling rate of the stream used for DSP download
3396 * @channels: channels of the stream used for DSP download
3397 * @ovly: TRUE if overlay format is required
3398 *
3399 * Returns zero or a negative error code.
3400 */
dspxfr_image(struct hda_codec * codec,const struct dsp_image_seg * fls_data,unsigned int reloc,unsigned int sample_rate,unsigned short channels,bool ovly)3401 static int dspxfr_image(struct hda_codec *codec,
3402 const struct dsp_image_seg *fls_data,
3403 unsigned int reloc,
3404 unsigned int sample_rate,
3405 unsigned short channels,
3406 bool ovly)
3407 {
3408 struct ca0132_spec *spec = codec->spec;
3409 int status;
3410 unsigned short hda_format = 0;
3411 unsigned int response;
3412 unsigned char stream_id = 0;
3413 struct dma_engine *dma_engine;
3414 unsigned int dma_chan;
3415 unsigned int port_map_mask;
3416
3417 if (fls_data == NULL)
3418 return -EINVAL;
3419
3420 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3421 if (!dma_engine)
3422 return -ENOMEM;
3423
3424 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3425 if (!dma_engine->dmab) {
3426 kfree(dma_engine);
3427 return -ENOMEM;
3428 }
3429
3430 dma_engine->codec = codec;
3431 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3432 dma_engine->m_converter_format = hda_format;
3433 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3434 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3435
3436 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3437
3438 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3439 hda_format, &response);
3440
3441 if (status < 0) {
3442 codec_dbg(codec, "set converter format fail\n");
3443 goto exit;
3444 }
3445
3446 status = snd_hda_codec_load_dsp_prepare(codec,
3447 dma_engine->m_converter_format,
3448 dma_engine->buf_size,
3449 dma_engine->dmab);
3450 if (status < 0)
3451 goto exit;
3452 spec->dsp_stream_id = status;
3453
3454 if (ovly) {
3455 status = dspio_alloc_dma_chan(codec, &dma_chan);
3456 if (status < 0) {
3457 codec_dbg(codec, "alloc dmachan fail\n");
3458 dma_chan = INVALID_DMA_CHANNEL;
3459 goto exit;
3460 }
3461 }
3462
3463 port_map_mask = 0;
3464 status = dsp_allocate_ports_format(codec, hda_format,
3465 &port_map_mask);
3466 if (status < 0) {
3467 codec_dbg(codec, "alloc ports fail\n");
3468 goto exit;
3469 }
3470
3471 stream_id = dma_get_stream_id(dma_engine);
3472 status = codec_set_converter_stream_channel(codec,
3473 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3474 if (status < 0) {
3475 codec_dbg(codec, "set stream chan fail\n");
3476 goto exit;
3477 }
3478
3479 while ((fls_data != NULL) && !is_last(fls_data)) {
3480 if (!is_valid(fls_data)) {
3481 codec_dbg(codec, "FLS check fail\n");
3482 status = -EINVAL;
3483 goto exit;
3484 }
3485 status = dspxfr_one_seg(codec, fls_data, reloc,
3486 dma_engine, dma_chan,
3487 port_map_mask, ovly);
3488 if (status < 0)
3489 break;
3490
3491 if (is_hci_prog_list_seg(fls_data))
3492 fls_data = get_next_seg_ptr(fls_data);
3493
3494 if ((fls_data != NULL) && !is_last(fls_data))
3495 fls_data = get_next_seg_ptr(fls_data);
3496 }
3497
3498 if (port_map_mask != 0)
3499 status = dsp_free_ports(codec);
3500
3501 if (status < 0)
3502 goto exit;
3503
3504 status = codec_set_converter_stream_channel(codec,
3505 WIDGET_CHIP_CTRL, 0, 0, &response);
3506
3507 exit:
3508 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3509 dspio_free_dma_chan(codec, dma_chan);
3510
3511 if (dma_engine->dmab->area)
3512 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3513 kfree(dma_engine->dmab);
3514 kfree(dma_engine);
3515
3516 return status;
3517 }
3518
3519 /*
3520 * CA0132 DSP download stuffs.
3521 */
dspload_post_setup(struct hda_codec * codec)3522 static void dspload_post_setup(struct hda_codec *codec)
3523 {
3524 struct ca0132_spec *spec = codec->spec;
3525 codec_dbg(codec, "---- dspload_post_setup ------\n");
3526 if (!ca0132_use_alt_functions(spec)) {
3527 /*set DSP speaker to 2.0 configuration*/
3528 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3529 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3530
3531 /*update write pointer*/
3532 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3533 }
3534 }
3535
3536 /**
3537 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3538 *
3539 * @codec: the HDA codec
3540 * @fls: pointer to a fast load image
3541 * @ovly: TRUE if overlay format is required
3542 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3543 * no relocation
3544 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3545 * @router_chans: number of audio router channels to be allocated (0 means use
3546 * internal defaults; max is 32)
3547 *
3548 * Download DSP from a DSP Image Fast Load structure. This structure is a
3549 * linear, non-constant sized element array of structures, each of which
3550 * contain the count of the data to be loaded, the data itself, and the
3551 * corresponding starting chip address of the starting data location.
3552 * Returns zero or a negative error code.
3553 */
dspload_image(struct hda_codec * codec,const struct dsp_image_seg * fls,bool ovly,unsigned int reloc,bool autostart,int router_chans)3554 static int dspload_image(struct hda_codec *codec,
3555 const struct dsp_image_seg *fls,
3556 bool ovly,
3557 unsigned int reloc,
3558 bool autostart,
3559 int router_chans)
3560 {
3561 int status = 0;
3562 unsigned int sample_rate;
3563 unsigned short channels;
3564
3565 codec_dbg(codec, "---- dspload_image begin ------\n");
3566 if (router_chans == 0) {
3567 if (!ovly)
3568 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3569 else
3570 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3571 }
3572
3573 sample_rate = 48000;
3574 channels = (unsigned short)router_chans;
3575
3576 while (channels > 16) {
3577 sample_rate *= 2;
3578 channels /= 2;
3579 }
3580
3581 do {
3582 codec_dbg(codec, "Ready to program DMA\n");
3583 if (!ovly)
3584 status = dsp_reset(codec);
3585
3586 if (status < 0)
3587 break;
3588
3589 codec_dbg(codec, "dsp_reset() complete\n");
3590 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3591 ovly);
3592
3593 if (status < 0)
3594 break;
3595
3596 codec_dbg(codec, "dspxfr_image() complete\n");
3597 if (autostart && !ovly) {
3598 dspload_post_setup(codec);
3599 status = dsp_set_run_state(codec);
3600 }
3601
3602 codec_dbg(codec, "LOAD FINISHED\n");
3603 } while (0);
3604
3605 return status;
3606 }
3607
3608 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
dspload_is_loaded(struct hda_codec * codec)3609 static bool dspload_is_loaded(struct hda_codec *codec)
3610 {
3611 unsigned int data = 0;
3612 int status = 0;
3613
3614 status = chipio_read(codec, 0x40004, &data);
3615 if ((status < 0) || (data != 1))
3616 return false;
3617
3618 return true;
3619 }
3620 #else
3621 #define dspload_is_loaded(codec) false
3622 #endif
3623
dspload_wait_loaded(struct hda_codec * codec)3624 static bool dspload_wait_loaded(struct hda_codec *codec)
3625 {
3626 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3627
3628 do {
3629 if (dspload_is_loaded(codec)) {
3630 codec_info(codec, "ca0132 DSP downloaded and running\n");
3631 return true;
3632 }
3633 msleep(20);
3634 } while (time_before(jiffies, timeout));
3635
3636 codec_err(codec, "ca0132 failed to download DSP\n");
3637 return false;
3638 }
3639
3640 /*
3641 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3642 * based cards, and has a second mmio region, region2, that's used for special
3643 * commands.
3644 */
3645
3646 /*
3647 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3648 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3649 * The first eight bits are just the number of the pin. So far, I've only seen
3650 * this number go to 7.
3651 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3652 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3653 * then off to send that bit.
3654 */
ca0113_mmio_gpio_set(struct hda_codec * codec,unsigned int gpio_pin,bool enable)3655 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3656 bool enable)
3657 {
3658 struct ca0132_spec *spec = codec->spec;
3659 unsigned short gpio_data;
3660
3661 gpio_data = gpio_pin & 0xF;
3662 gpio_data |= ((enable << 8) & 0x100);
3663
3664 writew(gpio_data, spec->mem_base + 0x320);
3665 }
3666
3667 /*
3668 * Special pci region2 commands that are only used by the AE-5. They follow
3669 * a set format, and require reads at certain points to seemingly 'clear'
3670 * the response data. My first tests didn't do these reads, and would cause
3671 * the card to get locked up until the memory was read. These commands
3672 * seem to work with three distinct values that I've taken to calling group,
3673 * target-id, and value.
3674 */
ca0113_mmio_command_set(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3675 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3676 unsigned int target, unsigned int value)
3677 {
3678 struct ca0132_spec *spec = codec->spec;
3679 unsigned int write_val;
3680
3681 writel(0x0000007e, spec->mem_base + 0x210);
3682 readl(spec->mem_base + 0x210);
3683 writel(0x0000005a, spec->mem_base + 0x210);
3684 readl(spec->mem_base + 0x210);
3685 readl(spec->mem_base + 0x210);
3686
3687 writel(0x00800005, spec->mem_base + 0x20c);
3688 writel(group, spec->mem_base + 0x804);
3689
3690 writel(0x00800005, spec->mem_base + 0x20c);
3691 write_val = (target & 0xff);
3692 write_val |= (value << 8);
3693
3694
3695 writel(write_val, spec->mem_base + 0x204);
3696 /*
3697 * Need delay here or else it goes too fast and works inconsistently.
3698 */
3699 msleep(20);
3700
3701 readl(spec->mem_base + 0x860);
3702 readl(spec->mem_base + 0x854);
3703 readl(spec->mem_base + 0x840);
3704
3705 writel(0x00800004, spec->mem_base + 0x20c);
3706 writel(0x00000000, spec->mem_base + 0x210);
3707 readl(spec->mem_base + 0x210);
3708 readl(spec->mem_base + 0x210);
3709 }
3710
3711 /*
3712 * This second type of command is used for setting the sound filter type.
3713 */
ca0113_mmio_command_set_type2(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3714 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3715 unsigned int group, unsigned int target, unsigned int value)
3716 {
3717 struct ca0132_spec *spec = codec->spec;
3718 unsigned int write_val;
3719
3720 writel(0x0000007e, spec->mem_base + 0x210);
3721 readl(spec->mem_base + 0x210);
3722 writel(0x0000005a, spec->mem_base + 0x210);
3723 readl(spec->mem_base + 0x210);
3724 readl(spec->mem_base + 0x210);
3725
3726 writel(0x00800003, spec->mem_base + 0x20c);
3727 writel(group, spec->mem_base + 0x804);
3728
3729 writel(0x00800005, spec->mem_base + 0x20c);
3730 write_val = (target & 0xff);
3731 write_val |= (value << 8);
3732
3733
3734 writel(write_val, spec->mem_base + 0x204);
3735 msleep(20);
3736 readl(spec->mem_base + 0x860);
3737 readl(spec->mem_base + 0x854);
3738 readl(spec->mem_base + 0x840);
3739
3740 writel(0x00800004, spec->mem_base + 0x20c);
3741 writel(0x00000000, spec->mem_base + 0x210);
3742 readl(spec->mem_base + 0x210);
3743 readl(spec->mem_base + 0x210);
3744 }
3745
3746 /*
3747 * Setup GPIO for the other variants of Core3D.
3748 */
3749
3750 /*
3751 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3752 * the card shows as having no GPIO pins.
3753 */
ca0132_gpio_init(struct hda_codec * codec)3754 static void ca0132_gpio_init(struct hda_codec *codec)
3755 {
3756 struct ca0132_spec *spec = codec->spec;
3757
3758 switch (ca0132_quirk(spec)) {
3759 case QUIRK_SBZ:
3760 case QUIRK_AE5:
3761 case QUIRK_AE7:
3762 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3763 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3764 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3765 break;
3766 case QUIRK_R3DI:
3767 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3768 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3769 break;
3770 default:
3771 break;
3772 }
3773
3774 }
3775
3776 /* Sets the GPIO for audio output. */
ca0132_gpio_setup(struct hda_codec * codec)3777 static void ca0132_gpio_setup(struct hda_codec *codec)
3778 {
3779 struct ca0132_spec *spec = codec->spec;
3780
3781 switch (ca0132_quirk(spec)) {
3782 case QUIRK_SBZ:
3783 snd_hda_codec_write(codec, 0x01, 0,
3784 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3785 snd_hda_codec_write(codec, 0x01, 0,
3786 AC_VERB_SET_GPIO_MASK, 0x07);
3787 snd_hda_codec_write(codec, 0x01, 0,
3788 AC_VERB_SET_GPIO_DATA, 0x04);
3789 snd_hda_codec_write(codec, 0x01, 0,
3790 AC_VERB_SET_GPIO_DATA, 0x06);
3791 break;
3792 case QUIRK_R3DI:
3793 snd_hda_codec_write(codec, 0x01, 0,
3794 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3795 snd_hda_codec_write(codec, 0x01, 0,
3796 AC_VERB_SET_GPIO_MASK, 0x1F);
3797 snd_hda_codec_write(codec, 0x01, 0,
3798 AC_VERB_SET_GPIO_DATA, 0x0C);
3799 break;
3800 default:
3801 break;
3802 }
3803 }
3804
3805 /*
3806 * GPIO control functions for the Recon3D integrated.
3807 */
3808
3809 enum r3di_gpio_bit {
3810 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3811 R3DI_MIC_SELECT_BIT = 1,
3812 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3813 R3DI_OUT_SELECT_BIT = 2,
3814 /*
3815 * I dunno what this actually does, but it stays on until the dsp
3816 * is downloaded.
3817 */
3818 R3DI_GPIO_DSP_DOWNLOADING = 3,
3819 /*
3820 * Same as above, no clue what it does, but it comes on after the dsp
3821 * is downloaded.
3822 */
3823 R3DI_GPIO_DSP_DOWNLOADED = 4
3824 };
3825
3826 enum r3di_mic_select {
3827 /* Set GPIO bit 1 to 0 for rear mic */
3828 R3DI_REAR_MIC = 0,
3829 /* Set GPIO bit 1 to 1 for front microphone*/
3830 R3DI_FRONT_MIC = 1
3831 };
3832
3833 enum r3di_out_select {
3834 /* Set GPIO bit 2 to 0 for headphone */
3835 R3DI_HEADPHONE_OUT = 0,
3836 /* Set GPIO bit 2 to 1 for speaker */
3837 R3DI_LINE_OUT = 1
3838 };
3839 enum r3di_dsp_status {
3840 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3841 R3DI_DSP_DOWNLOADING = 0,
3842 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3843 R3DI_DSP_DOWNLOADED = 1
3844 };
3845
3846
r3di_gpio_mic_set(struct hda_codec * codec,enum r3di_mic_select cur_mic)3847 static void r3di_gpio_mic_set(struct hda_codec *codec,
3848 enum r3di_mic_select cur_mic)
3849 {
3850 unsigned int cur_gpio;
3851
3852 /* Get the current GPIO Data setup */
3853 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3854
3855 switch (cur_mic) {
3856 case R3DI_REAR_MIC:
3857 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3858 break;
3859 case R3DI_FRONT_MIC:
3860 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3861 break;
3862 }
3863 snd_hda_codec_write(codec, codec->core.afg, 0,
3864 AC_VERB_SET_GPIO_DATA, cur_gpio);
3865 }
3866
r3di_gpio_dsp_status_set(struct hda_codec * codec,enum r3di_dsp_status dsp_status)3867 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3868 enum r3di_dsp_status dsp_status)
3869 {
3870 unsigned int cur_gpio;
3871
3872 /* Get the current GPIO Data setup */
3873 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3874
3875 switch (dsp_status) {
3876 case R3DI_DSP_DOWNLOADING:
3877 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3878 snd_hda_codec_write(codec, codec->core.afg, 0,
3879 AC_VERB_SET_GPIO_DATA, cur_gpio);
3880 break;
3881 case R3DI_DSP_DOWNLOADED:
3882 /* Set DOWNLOADING bit to 0. */
3883 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3884
3885 snd_hda_codec_write(codec, codec->core.afg, 0,
3886 AC_VERB_SET_GPIO_DATA, cur_gpio);
3887
3888 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3889 break;
3890 }
3891
3892 snd_hda_codec_write(codec, codec->core.afg, 0,
3893 AC_VERB_SET_GPIO_DATA, cur_gpio);
3894 }
3895
3896 /*
3897 * PCM callbacks
3898 */
ca0132_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3899 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3900 struct hda_codec *codec,
3901 unsigned int stream_tag,
3902 unsigned int format,
3903 struct snd_pcm_substream *substream)
3904 {
3905 struct ca0132_spec *spec = codec->spec;
3906
3907 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3908
3909 return 0;
3910 }
3911
ca0132_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3912 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3913 struct hda_codec *codec,
3914 struct snd_pcm_substream *substream)
3915 {
3916 struct ca0132_spec *spec = codec->spec;
3917
3918 if (spec->dsp_state == DSP_DOWNLOADING)
3919 return 0;
3920
3921 /*If Playback effects are on, allow stream some time to flush
3922 *effects tail*/
3923 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3924 msleep(50);
3925
3926 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3927
3928 return 0;
3929 }
3930
ca0132_playback_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3931 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3932 struct hda_codec *codec,
3933 struct snd_pcm_substream *substream)
3934 {
3935 struct ca0132_spec *spec = codec->spec;
3936 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3937 struct snd_pcm_runtime *runtime = substream->runtime;
3938
3939 if (spec->dsp_state != DSP_DOWNLOADED)
3940 return 0;
3941
3942 /* Add latency if playback enhancement and either effect is enabled. */
3943 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3944 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3945 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3946 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3947 }
3948
3949 /* Applying Speaker EQ adds latency as well. */
3950 if (spec->cur_out_type == SPEAKER_OUT)
3951 latency += DSP_SPEAKER_OUT_LATENCY;
3952
3953 return (latency * runtime->rate) / 1000;
3954 }
3955
3956 /*
3957 * Digital out
3958 */
ca0132_dig_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3959 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3960 struct hda_codec *codec,
3961 struct snd_pcm_substream *substream)
3962 {
3963 struct ca0132_spec *spec = codec->spec;
3964 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3965 }
3966
ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3967 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3968 struct hda_codec *codec,
3969 unsigned int stream_tag,
3970 unsigned int format,
3971 struct snd_pcm_substream *substream)
3972 {
3973 struct ca0132_spec *spec = codec->spec;
3974 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3975 stream_tag, format, substream);
3976 }
3977
ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3978 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3979 struct hda_codec *codec,
3980 struct snd_pcm_substream *substream)
3981 {
3982 struct ca0132_spec *spec = codec->spec;
3983 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3984 }
3985
ca0132_dig_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3986 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3987 struct hda_codec *codec,
3988 struct snd_pcm_substream *substream)
3989 {
3990 struct ca0132_spec *spec = codec->spec;
3991 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3992 }
3993
3994 /*
3995 * Analog capture
3996 */
ca0132_capture_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3997 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3998 struct hda_codec *codec,
3999 unsigned int stream_tag,
4000 unsigned int format,
4001 struct snd_pcm_substream *substream)
4002 {
4003 snd_hda_codec_setup_stream(codec, hinfo->nid,
4004 stream_tag, 0, format);
4005
4006 return 0;
4007 }
4008
ca0132_capture_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)4009 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
4010 struct hda_codec *codec,
4011 struct snd_pcm_substream *substream)
4012 {
4013 struct ca0132_spec *spec = codec->spec;
4014
4015 if (spec->dsp_state == DSP_DOWNLOADING)
4016 return 0;
4017
4018 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
4019 return 0;
4020 }
4021
ca0132_capture_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)4022 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
4023 struct hda_codec *codec,
4024 struct snd_pcm_substream *substream)
4025 {
4026 struct ca0132_spec *spec = codec->spec;
4027 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4028 struct snd_pcm_runtime *runtime = substream->runtime;
4029
4030 if (spec->dsp_state != DSP_DOWNLOADED)
4031 return 0;
4032
4033 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4034 latency += DSP_CRYSTAL_VOICE_LATENCY;
4035
4036 return (latency * runtime->rate) / 1000;
4037 }
4038
4039 /*
4040 * Controls stuffs.
4041 */
4042
4043 /*
4044 * Mixer controls helpers.
4045 */
4046 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4047 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4048 .name = xname, \
4049 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4050 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4051 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4052 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4053 .info = ca0132_volume_info, \
4054 .get = ca0132_volume_get, \
4055 .put = ca0132_volume_put, \
4056 .tlv = { .c = ca0132_volume_tlv }, \
4057 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4058
4059 /*
4060 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4061 * volume put, which is used for setting the DSP volume. This was done because
4062 * the ca0132 functions were taking too much time and causing lag.
4063 */
4064 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4065 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4066 .name = xname, \
4067 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4068 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4069 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4070 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4071 .info = snd_hda_mixer_amp_volume_info, \
4072 .get = snd_hda_mixer_amp_volume_get, \
4073 .put = ca0132_alt_volume_put, \
4074 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4075 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4076
4077 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4078 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4079 .name = xname, \
4080 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4081 .info = snd_hda_mixer_amp_switch_info, \
4082 .get = ca0132_switch_get, \
4083 .put = ca0132_switch_put, \
4084 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4085
4086 /* stereo */
4087 #define CA0132_CODEC_VOL(xname, nid, dir) \
4088 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4089 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4090 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4091 #define CA0132_CODEC_MUTE(xname, nid, dir) \
4092 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4093
4094 /* lookup tables */
4095 /*
4096 * Lookup table with decibel values for the DSP. When volume is changed in
4097 * Windows, the DSP is also sent the dB value in floating point. In Windows,
4098 * these values have decimal points, probably because the Windows driver
4099 * actually uses floating point. We can't here, so I made a lookup table of
4100 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4101 * DAC's, and 9 is the maximum.
4102 */
4103 static const unsigned int float_vol_db_lookup[] = {
4104 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4105 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4106 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4107 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4108 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4109 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4110 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4111 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4112 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4113 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4114 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4115 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4116 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4117 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4118 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4119 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4120 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4121 };
4122
4123 /*
4124 * This table counts from float 0 to 1 in increments of .01, which is
4125 * useful for a few different sliders.
4126 */
4127 static const unsigned int float_zero_to_one_lookup[] = {
4128 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4129 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4130 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4131 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4132 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4133 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4134 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4135 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4136 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4137 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4138 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4139 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4140 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4141 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4142 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4143 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4144 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4145 };
4146
4147 /*
4148 * This table counts from float 10 to 1000, which is the range of the x-bass
4149 * crossover slider in Windows.
4150 */
4151 static const unsigned int float_xbass_xover_lookup[] = {
4152 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4153 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4154 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4155 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4156 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4157 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4158 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4159 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4160 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4161 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4162 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4163 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4164 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4165 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4166 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4167 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4168 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4169 };
4170
4171 /* The following are for tuning of products */
4172 #ifdef ENABLE_TUNING_CONTROLS
4173
4174 static const unsigned int voice_focus_vals_lookup[] = {
4175 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4176 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4177 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4178 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4179 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4180 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4181 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4182 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4183 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4184 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4185 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4186 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4187 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4188 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4189 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4190 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4191 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4192 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4193 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4194 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4195 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4196 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4197 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4198 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4199 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4200 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4201 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4202 };
4203
4204 static const unsigned int mic_svm_vals_lookup[] = {
4205 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4206 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4207 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4208 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4209 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4210 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4211 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4212 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4213 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4214 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4215 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4216 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4217 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4218 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4219 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4220 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4221 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4222 };
4223
4224 static const unsigned int equalizer_vals_lookup[] = {
4225 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4226 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4227 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4228 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4229 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4230 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4231 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4232 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4233 0x41C00000
4234 };
4235
tuning_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)4236 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4237 const unsigned int *lookup, int idx)
4238 {
4239 int i = 0;
4240
4241 for (i = 0; i < TUNING_CTLS_COUNT; i++)
4242 if (nid == ca0132_tuning_ctls[i].nid)
4243 goto found;
4244
4245 return -EINVAL;
4246 found:
4247 snd_hda_power_up(codec);
4248 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4249 ca0132_tuning_ctls[i].req,
4250 &(lookup[idx]), sizeof(unsigned int));
4251 snd_hda_power_down(codec);
4252
4253 return 1;
4254 }
4255
tuning_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4256 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4257 struct snd_ctl_elem_value *ucontrol)
4258 {
4259 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4260 struct ca0132_spec *spec = codec->spec;
4261 hda_nid_t nid = get_amp_nid(kcontrol);
4262 long *valp = ucontrol->value.integer.value;
4263 int idx = nid - TUNING_CTL_START_NID;
4264
4265 *valp = spec->cur_ctl_vals[idx];
4266 return 0;
4267 }
4268
voice_focus_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4269 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4270 struct snd_ctl_elem_info *uinfo)
4271 {
4272 int chs = get_amp_channels(kcontrol);
4273 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4274 uinfo->count = chs == 3 ? 2 : 1;
4275 uinfo->value.integer.min = 20;
4276 uinfo->value.integer.max = 180;
4277 uinfo->value.integer.step = 1;
4278
4279 return 0;
4280 }
4281
voice_focus_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4282 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4283 struct snd_ctl_elem_value *ucontrol)
4284 {
4285 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4286 struct ca0132_spec *spec = codec->spec;
4287 hda_nid_t nid = get_amp_nid(kcontrol);
4288 long *valp = ucontrol->value.integer.value;
4289 int idx;
4290
4291 idx = nid - TUNING_CTL_START_NID;
4292 /* any change? */
4293 if (spec->cur_ctl_vals[idx] == *valp)
4294 return 0;
4295
4296 spec->cur_ctl_vals[idx] = *valp;
4297
4298 idx = *valp - 20;
4299 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4300
4301 return 1;
4302 }
4303
mic_svm_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4304 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4305 struct snd_ctl_elem_info *uinfo)
4306 {
4307 int chs = get_amp_channels(kcontrol);
4308 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4309 uinfo->count = chs == 3 ? 2 : 1;
4310 uinfo->value.integer.min = 0;
4311 uinfo->value.integer.max = 100;
4312 uinfo->value.integer.step = 1;
4313
4314 return 0;
4315 }
4316
mic_svm_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4317 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4318 struct snd_ctl_elem_value *ucontrol)
4319 {
4320 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4321 struct ca0132_spec *spec = codec->spec;
4322 hda_nid_t nid = get_amp_nid(kcontrol);
4323 long *valp = ucontrol->value.integer.value;
4324 int idx;
4325
4326 idx = nid - TUNING_CTL_START_NID;
4327 /* any change? */
4328 if (spec->cur_ctl_vals[idx] == *valp)
4329 return 0;
4330
4331 spec->cur_ctl_vals[idx] = *valp;
4332
4333 idx = *valp;
4334 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4335
4336 return 0;
4337 }
4338
equalizer_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4339 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4340 struct snd_ctl_elem_info *uinfo)
4341 {
4342 int chs = get_amp_channels(kcontrol);
4343 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4344 uinfo->count = chs == 3 ? 2 : 1;
4345 uinfo->value.integer.min = 0;
4346 uinfo->value.integer.max = 48;
4347 uinfo->value.integer.step = 1;
4348
4349 return 0;
4350 }
4351
equalizer_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4352 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4353 struct snd_ctl_elem_value *ucontrol)
4354 {
4355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4356 struct ca0132_spec *spec = codec->spec;
4357 hda_nid_t nid = get_amp_nid(kcontrol);
4358 long *valp = ucontrol->value.integer.value;
4359 int idx;
4360
4361 idx = nid - TUNING_CTL_START_NID;
4362 /* any change? */
4363 if (spec->cur_ctl_vals[idx] == *valp)
4364 return 0;
4365
4366 spec->cur_ctl_vals[idx] = *valp;
4367
4368 idx = *valp;
4369 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4370
4371 return 1;
4372 }
4373
4374 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4375 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4376
add_tuning_control(struct hda_codec * codec,hda_nid_t pnid,hda_nid_t nid,const char * name,int dir)4377 static int add_tuning_control(struct hda_codec *codec,
4378 hda_nid_t pnid, hda_nid_t nid,
4379 const char *name, int dir)
4380 {
4381 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4382 int type = dir ? HDA_INPUT : HDA_OUTPUT;
4383 struct snd_kcontrol_new knew =
4384 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4385
4386 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4387 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4388 knew.tlv.c = NULL;
4389 knew.tlv.p = NULL;
4390 switch (pnid) {
4391 case VOICE_FOCUS:
4392 knew.info = voice_focus_ctl_info;
4393 knew.get = tuning_ctl_get;
4394 knew.put = voice_focus_ctl_put;
4395 knew.tlv.p = voice_focus_db_scale;
4396 break;
4397 case MIC_SVM:
4398 knew.info = mic_svm_ctl_info;
4399 knew.get = tuning_ctl_get;
4400 knew.put = mic_svm_ctl_put;
4401 break;
4402 case EQUALIZER:
4403 knew.info = equalizer_ctl_info;
4404 knew.get = tuning_ctl_get;
4405 knew.put = equalizer_ctl_put;
4406 knew.tlv.p = eq_db_scale;
4407 break;
4408 default:
4409 return 0;
4410 }
4411 knew.private_value =
4412 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4413 snprintf(namestr, sizeof(namestr), "%s %s Volume", name, dirstr[dir]);
4414 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4415 }
4416
add_tuning_ctls(struct hda_codec * codec)4417 static int add_tuning_ctls(struct hda_codec *codec)
4418 {
4419 int i;
4420 int err;
4421
4422 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4423 err = add_tuning_control(codec,
4424 ca0132_tuning_ctls[i].parent_nid,
4425 ca0132_tuning_ctls[i].nid,
4426 ca0132_tuning_ctls[i].name,
4427 ca0132_tuning_ctls[i].direct);
4428 if (err < 0)
4429 return err;
4430 }
4431
4432 return 0;
4433 }
4434
ca0132_init_tuning_defaults(struct hda_codec * codec)4435 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4436 {
4437 struct ca0132_spec *spec = codec->spec;
4438 int i;
4439
4440 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4441 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4442 /* SVM level defaults to 0.74. */
4443 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4444
4445 /* EQ defaults to 0dB. */
4446 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4447 spec->cur_ctl_vals[i] = 24;
4448 }
4449 #endif /*ENABLE_TUNING_CONTROLS*/
4450
4451 /*
4452 * Select the active output.
4453 * If autodetect is enabled, output will be selected based on jack detection.
4454 * If jack inserted, headphone will be selected, else built-in speakers
4455 * If autodetect is disabled, output will be selected based on selection.
4456 */
ca0132_select_out(struct hda_codec * codec)4457 static int ca0132_select_out(struct hda_codec *codec)
4458 {
4459 struct ca0132_spec *spec = codec->spec;
4460 unsigned int pin_ctl;
4461 int jack_present;
4462 int auto_jack;
4463 unsigned int tmp;
4464 int err;
4465
4466 codec_dbg(codec, "ca0132_select_out\n");
4467
4468 snd_hda_power_up_pm(codec);
4469
4470 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4471
4472 if (auto_jack)
4473 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4474 else
4475 jack_present =
4476 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4477
4478 if (jack_present)
4479 spec->cur_out_type = HEADPHONE_OUT;
4480 else
4481 spec->cur_out_type = SPEAKER_OUT;
4482
4483 if (spec->cur_out_type == SPEAKER_OUT) {
4484 codec_dbg(codec, "ca0132_select_out speaker\n");
4485 /*speaker out config*/
4486 tmp = FLOAT_ONE;
4487 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4488 if (err < 0)
4489 goto exit;
4490 /*enable speaker EQ*/
4491 tmp = FLOAT_ONE;
4492 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4493 if (err < 0)
4494 goto exit;
4495
4496 /* Setup EAPD */
4497 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4498 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4499 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4500 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4501 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4502 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4503 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4504 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4505
4506 /* disable headphone node */
4507 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4508 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4509 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4510 pin_ctl & ~PIN_HP);
4511 /* enable speaker node */
4512 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4513 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4514 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4515 pin_ctl | PIN_OUT);
4516 } else {
4517 codec_dbg(codec, "ca0132_select_out hp\n");
4518 /*headphone out config*/
4519 tmp = FLOAT_ZERO;
4520 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4521 if (err < 0)
4522 goto exit;
4523 /*disable speaker EQ*/
4524 tmp = FLOAT_ZERO;
4525 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4526 if (err < 0)
4527 goto exit;
4528
4529 /* Setup EAPD */
4530 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4531 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4532 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4533 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4534 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4535 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4536 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4537 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4538
4539 /* disable speaker*/
4540 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4541 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4542 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4543 pin_ctl & ~PIN_HP);
4544 /* enable headphone*/
4545 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4546 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4547 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4548 pin_ctl | PIN_HP);
4549 }
4550
4551 exit:
4552 snd_hda_power_down_pm(codec);
4553
4554 return err < 0 ? err : 0;
4555 }
4556
4557 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4558 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4559 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4560
ae5_mmio_select_out(struct hda_codec * codec)4561 static void ae5_mmio_select_out(struct hda_codec *codec)
4562 {
4563 struct ca0132_spec *spec = codec->spec;
4564 const struct ae_ca0113_output_set *out_cmds;
4565 unsigned int i;
4566
4567 if (ca0132_quirk(spec) == QUIRK_AE5)
4568 out_cmds = &ae5_ca0113_output_presets;
4569 else
4570 out_cmds = &ae7_ca0113_output_presets;
4571
4572 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4573 ca0113_mmio_command_set(codec, out_cmds->group[i],
4574 out_cmds->target[i],
4575 out_cmds->vals[spec->cur_out_type][i]);
4576 }
4577
ca0132_alt_set_full_range_speaker(struct hda_codec * codec)4578 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4579 {
4580 struct ca0132_spec *spec = codec->spec;
4581 int quirk = ca0132_quirk(spec);
4582 unsigned int tmp;
4583 int err;
4584
4585 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4586 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4587 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4588 return 0;
4589
4590 /* Set front L/R full range. Zero for full-range, one for redirection. */
4591 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4592 err = dspio_set_uint_param(codec, 0x96,
4593 SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4594 if (err < 0)
4595 return err;
4596
4597 /* When setting full-range rear, both rear and center/lfe are set. */
4598 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4599 err = dspio_set_uint_param(codec, 0x96,
4600 SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4601 if (err < 0)
4602 return err;
4603
4604 err = dspio_set_uint_param(codec, 0x96,
4605 SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4606 if (err < 0)
4607 return err;
4608
4609 /*
4610 * Only the AE series cards set this value when setting full-range,
4611 * and it's always 1.0f.
4612 */
4613 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4614 err = dspio_set_uint_param(codec, 0x96,
4615 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4616 if (err < 0)
4617 return err;
4618 }
4619
4620 return 0;
4621 }
4622
ca0132_alt_surround_set_bass_redirection(struct hda_codec * codec,bool val)4623 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4624 bool val)
4625 {
4626 struct ca0132_spec *spec = codec->spec;
4627 unsigned int tmp;
4628 int err;
4629
4630 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4631 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4632 tmp = FLOAT_ONE;
4633 else
4634 tmp = FLOAT_ZERO;
4635
4636 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4637 if (err < 0)
4638 return err;
4639
4640 /* If it is enabled, make sure to set the crossover frequency. */
4641 if (tmp) {
4642 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4643 err = dspio_set_uint_param(codec, 0x96,
4644 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4645 if (err < 0)
4646 return err;
4647 }
4648
4649 return 0;
4650 }
4651
4652 /*
4653 * These are the commands needed to setup output on each of the different card
4654 * types.
4655 */
ca0132_alt_select_out_get_quirk_data(struct hda_codec * codec,const struct ca0132_alt_out_set_quirk_data ** quirk_data)4656 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4657 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4658 {
4659 struct ca0132_spec *spec = codec->spec;
4660 int quirk = ca0132_quirk(spec);
4661 unsigned int i;
4662
4663 *quirk_data = NULL;
4664 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4665 if (quirk_out_set_data[i].quirk_id == quirk) {
4666 *quirk_data = &quirk_out_set_data[i];
4667 return;
4668 }
4669 }
4670 }
4671
ca0132_alt_select_out_quirk_set(struct hda_codec * codec)4672 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4673 {
4674 const struct ca0132_alt_out_set_quirk_data *quirk_data;
4675 const struct ca0132_alt_out_set_info *out_info;
4676 struct ca0132_spec *spec = codec->spec;
4677 unsigned int i, gpio_data;
4678 int err;
4679
4680 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4681 if (!quirk_data)
4682 return 0;
4683
4684 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4685 if (quirk_data->is_ae_series)
4686 ae5_mmio_select_out(codec);
4687
4688 if (out_info->has_hda_gpio) {
4689 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4690 AC_VERB_GET_GPIO_DATA, 0);
4691
4692 if (out_info->hda_gpio_set)
4693 gpio_data |= (1 << out_info->hda_gpio_pin);
4694 else
4695 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4696
4697 snd_hda_codec_write(codec, codec->core.afg, 0,
4698 AC_VERB_SET_GPIO_DATA, gpio_data);
4699 }
4700
4701 if (out_info->mmio_gpio_count) {
4702 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4703 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4704 out_info->mmio_gpio_set[i]);
4705 }
4706 }
4707
4708 if (out_info->scp_cmds_count) {
4709 for (i = 0; i < out_info->scp_cmds_count; i++) {
4710 err = dspio_set_uint_param(codec,
4711 out_info->scp_cmd_mid[i],
4712 out_info->scp_cmd_req[i],
4713 out_info->scp_cmd_val[i]);
4714 if (err < 0)
4715 return err;
4716 }
4717 }
4718
4719 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4720
4721 if (out_info->has_chipio_write) {
4722 chipio_write(codec, out_info->chipio_write_addr,
4723 out_info->chipio_write_data);
4724 }
4725
4726 if (quirk_data->has_headphone_gain) {
4727 if (spec->cur_out_type != HEADPHONE_OUT) {
4728 if (quirk_data->is_ae_series)
4729 ae5_headphone_gain_set(codec, 2);
4730 else
4731 zxr_headphone_gain_set(codec, 0);
4732 } else {
4733 if (quirk_data->is_ae_series)
4734 ae5_headphone_gain_set(codec,
4735 spec->ae5_headphone_gain_val);
4736 else
4737 zxr_headphone_gain_set(codec,
4738 spec->zxr_gain_set);
4739 }
4740 }
4741
4742 return 0;
4743 }
4744
ca0132_set_out_node_pincfg(struct hda_codec * codec,hda_nid_t nid,bool out_enable,bool hp_enable)4745 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4746 bool out_enable, bool hp_enable)
4747 {
4748 unsigned int pin_ctl;
4749
4750 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4751 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4752
4753 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4754 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4755 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4756 }
4757
4758 /*
4759 * This function behaves similarly to the ca0132_select_out funciton above,
4760 * except with a few differences. It adds the ability to select the current
4761 * output with an enumerated control "output source" if the auto detect
4762 * mute switch is set to off. If the auto detect mute switch is enabled, it
4763 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4764 * It also adds the ability to auto-detect the front headphone port.
4765 */
ca0132_alt_select_out(struct hda_codec * codec)4766 static int ca0132_alt_select_out(struct hda_codec *codec)
4767 {
4768 struct ca0132_spec *spec = codec->spec;
4769 unsigned int tmp, outfx_set;
4770 int jack_present;
4771 int auto_jack;
4772 int err;
4773 /* Default Headphone is rear headphone */
4774 hda_nid_t headphone_nid = spec->out_pins[1];
4775
4776 codec_dbg(codec, "%s\n", __func__);
4777
4778 snd_hda_power_up_pm(codec);
4779
4780 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4781
4782 /*
4783 * If headphone rear or front is plugged in, set to headphone.
4784 * If neither is plugged in, set to rear line out. Only if
4785 * hp/speaker auto detect is enabled.
4786 */
4787 if (auto_jack) {
4788 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4789 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4790
4791 if (jack_present)
4792 spec->cur_out_type = HEADPHONE_OUT;
4793 else
4794 spec->cur_out_type = SPEAKER_OUT;
4795 } else
4796 spec->cur_out_type = spec->out_enum_val;
4797
4798 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4799
4800 /* Begin DSP output switch, mute DSP volume. */
4801 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4802 if (err < 0)
4803 goto exit;
4804
4805 err = ca0132_alt_select_out_quirk_set(codec);
4806 if (err < 0)
4807 goto exit;
4808
4809 switch (spec->cur_out_type) {
4810 case SPEAKER_OUT:
4811 codec_dbg(codec, "%s speaker\n", __func__);
4812
4813 /* Enable EAPD */
4814 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4815 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4816
4817 /* Disable headphone node. */
4818 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4819 /* Set front L-R to output. */
4820 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4821 /* Set Center/LFE to output. */
4822 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4823 /* Set rear surround to output. */
4824 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4825
4826 /*
4827 * Without PlayEnhancement being enabled, if we've got a 2.0
4828 * setup, set it to floating point eight to disable any DSP
4829 * processing effects.
4830 */
4831 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4832 tmp = FLOAT_EIGHT;
4833 else
4834 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4835
4836 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4837 if (err < 0)
4838 goto exit;
4839
4840 break;
4841 case HEADPHONE_OUT:
4842 codec_dbg(codec, "%s hp\n", __func__);
4843 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4844 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4845
4846 /* Disable all speaker nodes. */
4847 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4848 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4849 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4850
4851 /* enable headphone, either front or rear */
4852 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4853 headphone_nid = spec->out_pins[2];
4854 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4855 headphone_nid = spec->out_pins[1];
4856
4857 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4858
4859 if (outfx_set)
4860 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4861 else
4862 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4863
4864 if (err < 0)
4865 goto exit;
4866 break;
4867 }
4868 /*
4869 * If output effects are enabled, set the X-Bass effect value again to
4870 * make sure that it's properly enabled/disabled for speaker
4871 * configurations with an LFE channel.
4872 */
4873 if (outfx_set)
4874 ca0132_effects_set(codec, X_BASS,
4875 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4876
4877 /* Set speaker EQ bypass attenuation to 0. */
4878 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4879 if (err < 0)
4880 goto exit;
4881
4882 /*
4883 * Although unused on all cards but the AE series, this is always set
4884 * to zero when setting the output.
4885 */
4886 err = dspio_set_uint_param(codec, 0x96,
4887 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4888 if (err < 0)
4889 goto exit;
4890
4891 if (spec->cur_out_type == SPEAKER_OUT)
4892 err = ca0132_alt_surround_set_bass_redirection(codec,
4893 spec->bass_redirection_val);
4894 else
4895 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4896 if (err < 0)
4897 goto exit;
4898
4899 /* Unmute DSP now that we're done with output selection. */
4900 err = dspio_set_uint_param(codec, 0x96,
4901 SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4902 if (err < 0)
4903 goto exit;
4904
4905 if (spec->cur_out_type == SPEAKER_OUT) {
4906 err = ca0132_alt_set_full_range_speaker(codec);
4907 if (err < 0)
4908 goto exit;
4909 }
4910
4911 exit:
4912 snd_hda_power_down_pm(codec);
4913
4914 return err < 0 ? err : 0;
4915 }
4916
ca0132_unsol_hp_delayed(struct work_struct * work)4917 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4918 {
4919 struct ca0132_spec *spec = container_of(
4920 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4921 struct hda_jack_tbl *jack;
4922
4923 if (ca0132_use_alt_functions(spec))
4924 ca0132_alt_select_out(spec->codec);
4925 else
4926 ca0132_select_out(spec->codec);
4927
4928 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4929 if (jack) {
4930 jack->block_report = 0;
4931 snd_hda_jack_report_sync(spec->codec);
4932 }
4933 }
4934
4935 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4936 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4937 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4938 static int stop_mic1(struct hda_codec *codec);
4939 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4940 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4941
4942 /*
4943 * Select the active VIP source
4944 */
ca0132_set_vipsource(struct hda_codec * codec,int val)4945 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4946 {
4947 struct ca0132_spec *spec = codec->spec;
4948 unsigned int tmp;
4949
4950 if (spec->dsp_state != DSP_DOWNLOADED)
4951 return 0;
4952
4953 /* if CrystalVoice if off, vipsource should be 0 */
4954 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4955 (val == 0)) {
4956 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4957 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4958 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4959 if (spec->cur_mic_type == DIGITAL_MIC)
4960 tmp = FLOAT_TWO;
4961 else
4962 tmp = FLOAT_ONE;
4963 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4964 tmp = FLOAT_ZERO;
4965 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4966 } else {
4967 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4968 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4969 if (spec->cur_mic_type == DIGITAL_MIC)
4970 tmp = FLOAT_TWO;
4971 else
4972 tmp = FLOAT_ONE;
4973 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4974 tmp = FLOAT_ONE;
4975 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4976 msleep(20);
4977 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4978 }
4979
4980 return 1;
4981 }
4982
ca0132_alt_set_vipsource(struct hda_codec * codec,int val)4983 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4984 {
4985 struct ca0132_spec *spec = codec->spec;
4986 unsigned int tmp;
4987
4988 if (spec->dsp_state != DSP_DOWNLOADED)
4989 return 0;
4990
4991 codec_dbg(codec, "%s\n", __func__);
4992
4993 chipio_set_stream_control(codec, 0x03, 0);
4994 chipio_set_stream_control(codec, 0x04, 0);
4995
4996 /* if CrystalVoice is off, vipsource should be 0 */
4997 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4998 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4999 codec_dbg(codec, "%s: off.", __func__);
5000 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
5001
5002 tmp = FLOAT_ZERO;
5003 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5004
5005 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5006 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5007 if (ca0132_quirk(spec) == QUIRK_R3DI)
5008 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5009
5010
5011 if (spec->in_enum_val == REAR_LINE_IN)
5012 tmp = FLOAT_ZERO;
5013 else {
5014 if (ca0132_quirk(spec) == QUIRK_SBZ)
5015 tmp = FLOAT_THREE;
5016 else
5017 tmp = FLOAT_ONE;
5018 }
5019
5020 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5021
5022 } else {
5023 codec_dbg(codec, "%s: on.", __func__);
5024 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
5025 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
5026 if (ca0132_quirk(spec) == QUIRK_R3DI)
5027 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5028
5029 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5030 tmp = FLOAT_TWO;
5031 else
5032 tmp = FLOAT_ONE;
5033 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5034
5035 tmp = FLOAT_ONE;
5036 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5037
5038 msleep(20);
5039 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5040 }
5041
5042 chipio_set_stream_control(codec, 0x03, 1);
5043 chipio_set_stream_control(codec, 0x04, 1);
5044
5045 return 1;
5046 }
5047
5048 /*
5049 * Select the active microphone.
5050 * If autodetect is enabled, mic will be selected based on jack detection.
5051 * If jack inserted, ext.mic will be selected, else built-in mic
5052 * If autodetect is disabled, mic will be selected based on selection.
5053 */
ca0132_select_mic(struct hda_codec * codec)5054 static int ca0132_select_mic(struct hda_codec *codec)
5055 {
5056 struct ca0132_spec *spec = codec->spec;
5057 int jack_present;
5058 int auto_jack;
5059
5060 codec_dbg(codec, "ca0132_select_mic\n");
5061
5062 snd_hda_power_up_pm(codec);
5063
5064 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5065
5066 if (auto_jack)
5067 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5068 else
5069 jack_present =
5070 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5071
5072 if (jack_present)
5073 spec->cur_mic_type = LINE_MIC_IN;
5074 else
5075 spec->cur_mic_type = DIGITAL_MIC;
5076
5077 if (spec->cur_mic_type == DIGITAL_MIC) {
5078 /* enable digital Mic */
5079 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5080 ca0132_set_dmic(codec, 1);
5081 ca0132_mic_boost_set(codec, 0);
5082 /* set voice focus */
5083 ca0132_effects_set(codec, VOICE_FOCUS,
5084 spec->effects_switch
5085 [VOICE_FOCUS - EFFECT_START_NID]);
5086 } else {
5087 /* disable digital Mic */
5088 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5089 ca0132_set_dmic(codec, 0);
5090 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5091 /* disable voice focus */
5092 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5093 }
5094
5095 snd_hda_power_down_pm(codec);
5096
5097 return 0;
5098 }
5099
5100 /*
5101 * Select the active input.
5102 * Mic detection isn't used, because it's kind of pointless on the SBZ.
5103 * The front mic has no jack-detection, so the only way to switch to it
5104 * is to do it manually in alsamixer.
5105 */
ca0132_alt_select_in(struct hda_codec * codec)5106 static int ca0132_alt_select_in(struct hda_codec *codec)
5107 {
5108 struct ca0132_spec *spec = codec->spec;
5109 unsigned int tmp;
5110
5111 codec_dbg(codec, "%s\n", __func__);
5112
5113 snd_hda_power_up_pm(codec);
5114
5115 chipio_set_stream_control(codec, 0x03, 0);
5116 chipio_set_stream_control(codec, 0x04, 0);
5117
5118 spec->cur_mic_type = spec->in_enum_val;
5119
5120 switch (spec->cur_mic_type) {
5121 case REAR_MIC:
5122 switch (ca0132_quirk(spec)) {
5123 case QUIRK_SBZ:
5124 case QUIRK_R3D:
5125 ca0113_mmio_gpio_set(codec, 0, false);
5126 tmp = FLOAT_THREE;
5127 break;
5128 case QUIRK_ZXR:
5129 tmp = FLOAT_THREE;
5130 break;
5131 case QUIRK_R3DI:
5132 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5133 tmp = FLOAT_ONE;
5134 break;
5135 case QUIRK_AE5:
5136 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5137 tmp = FLOAT_THREE;
5138 break;
5139 case QUIRK_AE7:
5140 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5141 tmp = FLOAT_THREE;
5142 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5143 SR_96_000);
5144 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5145 SR_96_000);
5146 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5147 break;
5148 default:
5149 tmp = FLOAT_ONE;
5150 break;
5151 }
5152
5153 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5154 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5155 if (ca0132_quirk(spec) == QUIRK_R3DI)
5156 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5157
5158 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5159
5160 chipio_set_stream_control(codec, 0x03, 1);
5161 chipio_set_stream_control(codec, 0x04, 1);
5162 switch (ca0132_quirk(spec)) {
5163 case QUIRK_SBZ:
5164 chipio_write(codec, 0x18B098, 0x0000000C);
5165 chipio_write(codec, 0x18B09C, 0x0000000C);
5166 break;
5167 case QUIRK_ZXR:
5168 chipio_write(codec, 0x18B098, 0x0000000C);
5169 chipio_write(codec, 0x18B09C, 0x000000CC);
5170 break;
5171 case QUIRK_AE5:
5172 chipio_write(codec, 0x18B098, 0x0000000C);
5173 chipio_write(codec, 0x18B09C, 0x0000004C);
5174 break;
5175 default:
5176 break;
5177 }
5178 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5179 break;
5180 case REAR_LINE_IN:
5181 ca0132_mic_boost_set(codec, 0);
5182 switch (ca0132_quirk(spec)) {
5183 case QUIRK_SBZ:
5184 case QUIRK_R3D:
5185 ca0113_mmio_gpio_set(codec, 0, false);
5186 break;
5187 case QUIRK_R3DI:
5188 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5189 break;
5190 case QUIRK_AE5:
5191 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5192 break;
5193 case QUIRK_AE7:
5194 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5195 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5196 SR_96_000);
5197 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5198 SR_96_000);
5199 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5200 break;
5201 default:
5202 break;
5203 }
5204
5205 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5206 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5207 if (ca0132_quirk(spec) == QUIRK_R3DI)
5208 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5209
5210 if (ca0132_quirk(spec) == QUIRK_AE7)
5211 tmp = FLOAT_THREE;
5212 else
5213 tmp = FLOAT_ZERO;
5214 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5215
5216 switch (ca0132_quirk(spec)) {
5217 case QUIRK_SBZ:
5218 case QUIRK_AE5:
5219 chipio_write(codec, 0x18B098, 0x00000000);
5220 chipio_write(codec, 0x18B09C, 0x00000000);
5221 break;
5222 default:
5223 break;
5224 }
5225 chipio_set_stream_control(codec, 0x03, 1);
5226 chipio_set_stream_control(codec, 0x04, 1);
5227 break;
5228 case FRONT_MIC:
5229 switch (ca0132_quirk(spec)) {
5230 case QUIRK_SBZ:
5231 case QUIRK_R3D:
5232 ca0113_mmio_gpio_set(codec, 0, true);
5233 ca0113_mmio_gpio_set(codec, 5, false);
5234 tmp = FLOAT_THREE;
5235 break;
5236 case QUIRK_R3DI:
5237 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5238 tmp = FLOAT_ONE;
5239 break;
5240 case QUIRK_AE5:
5241 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5242 tmp = FLOAT_THREE;
5243 break;
5244 default:
5245 tmp = FLOAT_ONE;
5246 break;
5247 }
5248
5249 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5250 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5251 if (ca0132_quirk(spec) == QUIRK_R3DI)
5252 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5253
5254 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5255
5256 chipio_set_stream_control(codec, 0x03, 1);
5257 chipio_set_stream_control(codec, 0x04, 1);
5258
5259 switch (ca0132_quirk(spec)) {
5260 case QUIRK_SBZ:
5261 chipio_write(codec, 0x18B098, 0x0000000C);
5262 chipio_write(codec, 0x18B09C, 0x000000CC);
5263 break;
5264 case QUIRK_AE5:
5265 chipio_write(codec, 0x18B098, 0x0000000C);
5266 chipio_write(codec, 0x18B09C, 0x0000004C);
5267 break;
5268 default:
5269 break;
5270 }
5271 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5272 break;
5273 }
5274 ca0132_cvoice_switch_set(codec);
5275
5276 snd_hda_power_down_pm(codec);
5277 return 0;
5278 }
5279
5280 /*
5281 * Check if VNODE settings take effect immediately.
5282 */
ca0132_is_vnode_effective(struct hda_codec * codec,hda_nid_t vnid,hda_nid_t * shared_nid)5283 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5284 hda_nid_t vnid,
5285 hda_nid_t *shared_nid)
5286 {
5287 struct ca0132_spec *spec = codec->spec;
5288 hda_nid_t nid;
5289
5290 switch (vnid) {
5291 case VNID_SPK:
5292 nid = spec->shared_out_nid;
5293 break;
5294 case VNID_MIC:
5295 nid = spec->shared_mic_nid;
5296 break;
5297 default:
5298 return false;
5299 }
5300
5301 if (shared_nid)
5302 *shared_nid = nid;
5303
5304 return true;
5305 }
5306
5307 /*
5308 * The following functions are control change helpers.
5309 * They return 0 if no changed. Return 1 if changed.
5310 */
ca0132_voicefx_set(struct hda_codec * codec,int enable)5311 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5312 {
5313 struct ca0132_spec *spec = codec->spec;
5314 unsigned int tmp;
5315
5316 /* based on CrystalVoice state to enable VoiceFX. */
5317 if (enable) {
5318 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5319 FLOAT_ONE : FLOAT_ZERO;
5320 } else {
5321 tmp = FLOAT_ZERO;
5322 }
5323
5324 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5325 ca0132_voicefx.reqs[0], tmp);
5326
5327 return 1;
5328 }
5329
5330 /*
5331 * Set the effects parameters
5332 */
ca0132_effects_set(struct hda_codec * codec,hda_nid_t nid,long val)5333 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5334 {
5335 struct ca0132_spec *spec = codec->spec;
5336 unsigned int on, tmp, channel_cfg;
5337 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5338 int err = 0;
5339 int idx = nid - EFFECT_START_NID;
5340
5341 if ((idx < 0) || (idx >= num_fx))
5342 return 0; /* no changed */
5343
5344 /* for out effect, qualify with PE */
5345 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5346 /* if PE if off, turn off out effects. */
5347 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5348 val = 0;
5349 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5350 channel_cfg = spec->channel_cfg_val;
5351 if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5352 channel_cfg != SPEAKER_CHANNELS_4_0)
5353 val = 0;
5354 }
5355 }
5356
5357 /* for in effect, qualify with CrystalVoice */
5358 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5359 /* if CrystalVoice if off, turn off in effects. */
5360 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5361 val = 0;
5362
5363 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5364 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5365 val = 0;
5366
5367 /* If Voice Focus on SBZ, set to two channel. */
5368 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5369 && (spec->cur_mic_type != REAR_LINE_IN)) {
5370 if (spec->effects_switch[CRYSTAL_VOICE -
5371 EFFECT_START_NID]) {
5372
5373 if (spec->effects_switch[VOICE_FOCUS -
5374 EFFECT_START_NID]) {
5375 tmp = FLOAT_TWO;
5376 val = 1;
5377 } else
5378 tmp = FLOAT_ONE;
5379
5380 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5381 }
5382 }
5383 /*
5384 * For SBZ noise reduction, there's an extra command
5385 * to module ID 0x47. No clue why.
5386 */
5387 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5388 && (spec->cur_mic_type != REAR_LINE_IN)) {
5389 if (spec->effects_switch[CRYSTAL_VOICE -
5390 EFFECT_START_NID]) {
5391 if (spec->effects_switch[NOISE_REDUCTION -
5392 EFFECT_START_NID])
5393 tmp = FLOAT_ONE;
5394 else
5395 tmp = FLOAT_ZERO;
5396 } else
5397 tmp = FLOAT_ZERO;
5398
5399 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5400 }
5401
5402 /* If rear line in disable effects. */
5403 if (ca0132_use_alt_functions(spec) &&
5404 spec->in_enum_val == REAR_LINE_IN)
5405 val = 0;
5406 }
5407
5408 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5409 nid, val);
5410
5411 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5412 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5413 ca0132_effects[idx].reqs[0], on);
5414
5415 if (err < 0)
5416 return 0; /* no changed */
5417
5418 return 1;
5419 }
5420
5421 /*
5422 * Turn on/off Playback Enhancements
5423 */
ca0132_pe_switch_set(struct hda_codec * codec)5424 static int ca0132_pe_switch_set(struct hda_codec *codec)
5425 {
5426 struct ca0132_spec *spec = codec->spec;
5427 hda_nid_t nid;
5428 int i, ret = 0;
5429
5430 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5431 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5432
5433 if (ca0132_use_alt_functions(spec))
5434 ca0132_alt_select_out(codec);
5435
5436 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5437 nid = OUT_EFFECT_START_NID;
5438 /* PE affects all out effects */
5439 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5440 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5441
5442 return ret;
5443 }
5444
5445 /* Check if Mic1 is streaming, if so, stop streaming */
stop_mic1(struct hda_codec * codec)5446 static int stop_mic1(struct hda_codec *codec)
5447 {
5448 struct ca0132_spec *spec = codec->spec;
5449 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5450 AC_VERB_GET_CONV, 0);
5451 if (oldval != 0)
5452 snd_hda_codec_write(codec, spec->adcs[0], 0,
5453 AC_VERB_SET_CHANNEL_STREAMID,
5454 0);
5455 return oldval;
5456 }
5457
5458 /* Resume Mic1 streaming if it was stopped. */
resume_mic1(struct hda_codec * codec,unsigned int oldval)5459 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5460 {
5461 struct ca0132_spec *spec = codec->spec;
5462 /* Restore the previous stream and channel */
5463 if (oldval != 0)
5464 snd_hda_codec_write(codec, spec->adcs[0], 0,
5465 AC_VERB_SET_CHANNEL_STREAMID,
5466 oldval);
5467 }
5468
5469 /*
5470 * Turn on/off CrystalVoice
5471 */
ca0132_cvoice_switch_set(struct hda_codec * codec)5472 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5473 {
5474 struct ca0132_spec *spec = codec->spec;
5475 hda_nid_t nid;
5476 int i, ret = 0;
5477 unsigned int oldval;
5478
5479 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5480 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5481
5482 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5483 nid = IN_EFFECT_START_NID;
5484 /* CrystalVoice affects all in effects */
5485 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5486 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5487
5488 /* including VoiceFX */
5489 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5490
5491 /* set correct vipsource */
5492 oldval = stop_mic1(codec);
5493 if (ca0132_use_alt_functions(spec))
5494 ret |= ca0132_alt_set_vipsource(codec, 1);
5495 else
5496 ret |= ca0132_set_vipsource(codec, 1);
5497 resume_mic1(codec, oldval);
5498 return ret;
5499 }
5500
ca0132_mic_boost_set(struct hda_codec * codec,long val)5501 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5502 {
5503 struct ca0132_spec *spec = codec->spec;
5504 int ret = 0;
5505
5506 if (val) /* on */
5507 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5508 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5509 else /* off */
5510 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5511 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5512
5513 return ret;
5514 }
5515
ca0132_alt_mic_boost_set(struct hda_codec * codec,long val)5516 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5517 {
5518 struct ca0132_spec *spec = codec->spec;
5519 int ret = 0;
5520
5521 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5522 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5523 return ret;
5524 }
5525
ae5_headphone_gain_set(struct hda_codec * codec,long val)5526 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5527 {
5528 unsigned int i;
5529
5530 for (i = 0; i < 4; i++)
5531 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5532 ae5_headphone_gain_presets[val].vals[i]);
5533 return 0;
5534 }
5535
5536 /*
5537 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5538 * amplifier to handle a 600 ohm load.
5539 */
zxr_headphone_gain_set(struct hda_codec * codec,long val)5540 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5541 {
5542 ca0113_mmio_gpio_set(codec, 1, val);
5543
5544 return 0;
5545 }
5546
ca0132_vnode_switch_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5547 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5548 struct snd_ctl_elem_value *ucontrol)
5549 {
5550 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5551 hda_nid_t nid = get_amp_nid(kcontrol);
5552 hda_nid_t shared_nid = 0;
5553 bool effective;
5554 int ret = 0;
5555 struct ca0132_spec *spec = codec->spec;
5556 int auto_jack;
5557
5558 if (nid == VNID_HP_SEL) {
5559 auto_jack =
5560 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5561 if (!auto_jack) {
5562 if (ca0132_use_alt_functions(spec))
5563 ca0132_alt_select_out(codec);
5564 else
5565 ca0132_select_out(codec);
5566 }
5567 return 1;
5568 }
5569
5570 if (nid == VNID_AMIC1_SEL) {
5571 auto_jack =
5572 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5573 if (!auto_jack)
5574 ca0132_select_mic(codec);
5575 return 1;
5576 }
5577
5578 if (nid == VNID_HP_ASEL) {
5579 if (ca0132_use_alt_functions(spec))
5580 ca0132_alt_select_out(codec);
5581 else
5582 ca0132_select_out(codec);
5583 return 1;
5584 }
5585
5586 if (nid == VNID_AMIC1_ASEL) {
5587 ca0132_select_mic(codec);
5588 return 1;
5589 }
5590
5591 /* if effective conditions, then update hw immediately. */
5592 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5593 if (effective) {
5594 int dir = get_amp_direction(kcontrol);
5595 int ch = get_amp_channels(kcontrol);
5596 unsigned long pval;
5597
5598 mutex_lock(&codec->control_mutex);
5599 pval = kcontrol->private_value;
5600 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5601 0, dir);
5602 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5603 kcontrol->private_value = pval;
5604 mutex_unlock(&codec->control_mutex);
5605 }
5606
5607 return ret;
5608 }
5609 /* End of control change helpers. */
5610
ca0132_alt_bass_redirection_xover_set(struct hda_codec * codec,long idx)5611 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5612 long idx)
5613 {
5614 snd_hda_power_up(codec);
5615
5616 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5617 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5618
5619 snd_hda_power_down(codec);
5620 }
5621
5622 /*
5623 * Below I've added controls to mess with the effect levels, I've only enabled
5624 * them on the Sound Blaster Z, but they would probably also work on the
5625 * Chromebook. I figured they were probably tuned specifically for it, and left
5626 * out for a reason.
5627 */
5628
5629 /* Sets DSP effect level from the sliders above the controls */
5630
ca0132_alt_slider_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)5631 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5632 const unsigned int *lookup, int idx)
5633 {
5634 int i = 0;
5635 unsigned int y;
5636 /*
5637 * For X_BASS, req 2 is actually crossover freq instead of
5638 * effect level
5639 */
5640 if (nid == X_BASS)
5641 y = 2;
5642 else
5643 y = 1;
5644
5645 snd_hda_power_up(codec);
5646 if (nid == XBASS_XOVER) {
5647 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5648 if (ca0132_effects[i].nid == X_BASS)
5649 break;
5650
5651 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5652 ca0132_effects[i].reqs[1],
5653 &(lookup[idx - 1]), sizeof(unsigned int));
5654 } else {
5655 /* Find the actual effect structure */
5656 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5657 if (nid == ca0132_effects[i].nid)
5658 break;
5659
5660 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5661 ca0132_effects[i].reqs[y],
5662 &(lookup[idx]), sizeof(unsigned int));
5663 }
5664
5665 snd_hda_power_down(codec);
5666
5667 return 0;
5668 }
5669
ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5670 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5671 struct snd_ctl_elem_value *ucontrol)
5672 {
5673 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5674 struct ca0132_spec *spec = codec->spec;
5675 long *valp = ucontrol->value.integer.value;
5676 hda_nid_t nid = get_amp_nid(kcontrol);
5677
5678 if (nid == BASS_REDIRECTION_XOVER)
5679 *valp = spec->bass_redirect_xover_freq;
5680 else
5681 *valp = spec->xbass_xover_freq;
5682
5683 return 0;
5684 }
5685
ca0132_alt_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5686 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5687 struct snd_ctl_elem_value *ucontrol)
5688 {
5689 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5690 struct ca0132_spec *spec = codec->spec;
5691 hda_nid_t nid = get_amp_nid(kcontrol);
5692 long *valp = ucontrol->value.integer.value;
5693 int idx = nid - OUT_EFFECT_START_NID;
5694
5695 *valp = spec->fx_ctl_val[idx];
5696 return 0;
5697 }
5698
5699 /*
5700 * The X-bass crossover starts at 10hz, so the min is 1. The
5701 * frequency is set in multiples of 10.
5702 */
ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5703 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5704 struct snd_ctl_elem_info *uinfo)
5705 {
5706 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5707 uinfo->count = 1;
5708 uinfo->value.integer.min = 1;
5709 uinfo->value.integer.max = 100;
5710 uinfo->value.integer.step = 1;
5711
5712 return 0;
5713 }
5714
ca0132_alt_effect_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5715 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5716 struct snd_ctl_elem_info *uinfo)
5717 {
5718 int chs = get_amp_channels(kcontrol);
5719
5720 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5721 uinfo->count = chs == 3 ? 2 : 1;
5722 uinfo->value.integer.min = 0;
5723 uinfo->value.integer.max = 100;
5724 uinfo->value.integer.step = 1;
5725
5726 return 0;
5727 }
5728
ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5729 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5730 struct snd_ctl_elem_value *ucontrol)
5731 {
5732 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5733 struct ca0132_spec *spec = codec->spec;
5734 hda_nid_t nid = get_amp_nid(kcontrol);
5735 long *valp = ucontrol->value.integer.value;
5736 long *cur_val;
5737 int idx;
5738
5739 if (nid == BASS_REDIRECTION_XOVER)
5740 cur_val = &spec->bass_redirect_xover_freq;
5741 else
5742 cur_val = &spec->xbass_xover_freq;
5743
5744 /* any change? */
5745 if (*cur_val == *valp)
5746 return 0;
5747
5748 *cur_val = *valp;
5749
5750 idx = *valp;
5751 if (nid == BASS_REDIRECTION_XOVER)
5752 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5753 else
5754 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5755
5756 return 0;
5757 }
5758
ca0132_alt_effect_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5759 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5760 struct snd_ctl_elem_value *ucontrol)
5761 {
5762 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5763 struct ca0132_spec *spec = codec->spec;
5764 hda_nid_t nid = get_amp_nid(kcontrol);
5765 long *valp = ucontrol->value.integer.value;
5766 int idx;
5767
5768 idx = nid - EFFECT_START_NID;
5769 /* any change? */
5770 if (spec->fx_ctl_val[idx] == *valp)
5771 return 0;
5772
5773 spec->fx_ctl_val[idx] = *valp;
5774
5775 idx = *valp;
5776 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5777
5778 return 0;
5779 }
5780
5781
5782 /*
5783 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5784 * only has off or full 30 dB, and didn't like making a volume slider that has
5785 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5786 */
5787 #define MIC_BOOST_NUM_OF_STEPS 4
5788 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5789
ca0132_alt_mic_boost_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5790 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5791 struct snd_ctl_elem_info *uinfo)
5792 {
5793 const char *sfx = "dB";
5794 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5795
5796 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5797 uinfo->count = 1;
5798 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5799 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5800 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5801 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5802 strscpy(uinfo->value.enumerated.name, namestr);
5803 return 0;
5804 }
5805
ca0132_alt_mic_boost_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5806 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5807 struct snd_ctl_elem_value *ucontrol)
5808 {
5809 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5810 struct ca0132_spec *spec = codec->spec;
5811
5812 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5813 return 0;
5814 }
5815
ca0132_alt_mic_boost_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5816 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5817 struct snd_ctl_elem_value *ucontrol)
5818 {
5819 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5820 struct ca0132_spec *spec = codec->spec;
5821 int sel = ucontrol->value.enumerated.item[0];
5822 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5823
5824 if (sel >= items)
5825 return 0;
5826
5827 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5828 sel);
5829
5830 spec->mic_boost_enum_val = sel;
5831
5832 if (spec->in_enum_val != REAR_LINE_IN)
5833 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5834
5835 return 1;
5836 }
5837
5838 /*
5839 * Sound BlasterX AE-5 Headphone Gain Controls.
5840 */
5841 #define AE5_HEADPHONE_GAIN_MAX 3
ae5_headphone_gain_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5842 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5843 struct snd_ctl_elem_info *uinfo)
5844 {
5845 const char *sfx = " Ohms)";
5846 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5847
5848 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5849 uinfo->count = 1;
5850 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5851 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5852 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5853 sprintf(namestr, "%s %s",
5854 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5855 sfx);
5856 strscpy(uinfo->value.enumerated.name, namestr);
5857 return 0;
5858 }
5859
ae5_headphone_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5860 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5861 struct snd_ctl_elem_value *ucontrol)
5862 {
5863 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5864 struct ca0132_spec *spec = codec->spec;
5865
5866 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5867 return 0;
5868 }
5869
ae5_headphone_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5870 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5871 struct snd_ctl_elem_value *ucontrol)
5872 {
5873 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5874 struct ca0132_spec *spec = codec->spec;
5875 int sel = ucontrol->value.enumerated.item[0];
5876 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5877
5878 if (sel >= items)
5879 return 0;
5880
5881 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5882 sel);
5883
5884 spec->ae5_headphone_gain_val = sel;
5885
5886 if (spec->out_enum_val == HEADPHONE_OUT)
5887 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5888
5889 return 1;
5890 }
5891
5892 /*
5893 * Sound BlasterX AE-5 sound filter enumerated control.
5894 */
5895 #define AE5_SOUND_FILTER_MAX 3
5896
ae5_sound_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5897 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5898 struct snd_ctl_elem_info *uinfo)
5899 {
5900 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5901
5902 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5903 uinfo->count = 1;
5904 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5905 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5906 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5907 sprintf(namestr, "%s",
5908 ae5_filter_presets[uinfo->value.enumerated.item].name);
5909 strscpy(uinfo->value.enumerated.name, namestr);
5910 return 0;
5911 }
5912
ae5_sound_filter_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5913 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5914 struct snd_ctl_elem_value *ucontrol)
5915 {
5916 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5917 struct ca0132_spec *spec = codec->spec;
5918
5919 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5920 return 0;
5921 }
5922
ae5_sound_filter_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5923 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5924 struct snd_ctl_elem_value *ucontrol)
5925 {
5926 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5927 struct ca0132_spec *spec = codec->spec;
5928 int sel = ucontrol->value.enumerated.item[0];
5929 unsigned int items = AE5_SOUND_FILTER_MAX;
5930
5931 if (sel >= items)
5932 return 0;
5933
5934 codec_dbg(codec, "ae5_sound_filter: %s\n",
5935 ae5_filter_presets[sel].name);
5936
5937 spec->ae5_filter_val = sel;
5938
5939 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5940 ae5_filter_presets[sel].val);
5941
5942 return 1;
5943 }
5944
5945 /*
5946 * Input Select Control for alternative ca0132 codecs. This exists because
5947 * front microphone has no auto-detect, and we need a way to set the rear
5948 * as line-in
5949 */
ca0132_alt_input_source_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5950 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5951 struct snd_ctl_elem_info *uinfo)
5952 {
5953 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5954 uinfo->count = 1;
5955 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5956 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5957 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5958 strscpy(uinfo->value.enumerated.name,
5959 in_src_str[uinfo->value.enumerated.item]);
5960 return 0;
5961 }
5962
ca0132_alt_input_source_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5963 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5964 struct snd_ctl_elem_value *ucontrol)
5965 {
5966 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5967 struct ca0132_spec *spec = codec->spec;
5968
5969 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5970 return 0;
5971 }
5972
ca0132_alt_input_source_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5973 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5974 struct snd_ctl_elem_value *ucontrol)
5975 {
5976 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5977 struct ca0132_spec *spec = codec->spec;
5978 int sel = ucontrol->value.enumerated.item[0];
5979 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5980
5981 /*
5982 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5983 * line-in.
5984 */
5985 if (ca0132_quirk(spec) == QUIRK_AE7)
5986 items = 2;
5987
5988 if (sel >= items)
5989 return 0;
5990
5991 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5992 sel, in_src_str[sel]);
5993
5994 spec->in_enum_val = sel;
5995
5996 ca0132_alt_select_in(codec);
5997
5998 return 1;
5999 }
6000
6001 /* Sound Blaster Z Output Select Control */
ca0132_alt_output_select_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6002 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
6003 struct snd_ctl_elem_info *uinfo)
6004 {
6005 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6006 uinfo->count = 1;
6007 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
6008 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
6009 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
6010 strscpy(uinfo->value.enumerated.name,
6011 out_type_str[uinfo->value.enumerated.item]);
6012 return 0;
6013 }
6014
ca0132_alt_output_select_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6015 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
6016 struct snd_ctl_elem_value *ucontrol)
6017 {
6018 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6019 struct ca0132_spec *spec = codec->spec;
6020
6021 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
6022 return 0;
6023 }
6024
ca0132_alt_output_select_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6025 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
6026 struct snd_ctl_elem_value *ucontrol)
6027 {
6028 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6029 struct ca0132_spec *spec = codec->spec;
6030 int sel = ucontrol->value.enumerated.item[0];
6031 unsigned int items = NUM_OF_OUTPUTS;
6032 unsigned int auto_jack;
6033
6034 if (sel >= items)
6035 return 0;
6036
6037 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
6038 sel, out_type_str[sel]);
6039
6040 spec->out_enum_val = sel;
6041
6042 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6043
6044 if (!auto_jack)
6045 ca0132_alt_select_out(codec);
6046
6047 return 1;
6048 }
6049
6050 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6051 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
6052 struct snd_ctl_elem_info *uinfo)
6053 {
6054 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6055
6056 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6057 uinfo->count = 1;
6058 uinfo->value.enumerated.items = items;
6059 if (uinfo->value.enumerated.item >= items)
6060 uinfo->value.enumerated.item = items - 1;
6061 strscpy(uinfo->value.enumerated.name,
6062 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6063 return 0;
6064 }
6065
ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6066 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
6067 struct snd_ctl_elem_value *ucontrol)
6068 {
6069 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6070 struct ca0132_spec *spec = codec->spec;
6071
6072 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6073 return 0;
6074 }
6075
ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6076 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
6077 struct snd_ctl_elem_value *ucontrol)
6078 {
6079 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6080 struct ca0132_spec *spec = codec->spec;
6081 int sel = ucontrol->value.enumerated.item[0];
6082 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6083
6084 if (sel >= items)
6085 return 0;
6086
6087 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6088 sel, speaker_channel_cfgs[sel].name);
6089
6090 spec->channel_cfg_val = sel;
6091
6092 if (spec->out_enum_val == SPEAKER_OUT)
6093 ca0132_alt_select_out(codec);
6094
6095 return 1;
6096 }
6097
6098 /*
6099 * Smart Volume output setting control. Three different settings, Normal,
6100 * which takes the value from the smart volume slider. The two others, loud
6101 * and night, disregard the slider value and have uneditable values.
6102 */
6103 #define NUM_OF_SVM_SETTINGS 3
6104 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
6105
ca0132_alt_svm_setting_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6106 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
6107 struct snd_ctl_elem_info *uinfo)
6108 {
6109 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6110 uinfo->count = 1;
6111 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6112 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6113 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6114 strscpy(uinfo->value.enumerated.name,
6115 out_svm_set_enum_str[uinfo->value.enumerated.item]);
6116 return 0;
6117 }
6118
ca0132_alt_svm_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6119 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
6120 struct snd_ctl_elem_value *ucontrol)
6121 {
6122 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6123 struct ca0132_spec *spec = codec->spec;
6124
6125 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6126 return 0;
6127 }
6128
ca0132_alt_svm_setting_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6129 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
6130 struct snd_ctl_elem_value *ucontrol)
6131 {
6132 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6133 struct ca0132_spec *spec = codec->spec;
6134 int sel = ucontrol->value.enumerated.item[0];
6135 unsigned int items = NUM_OF_SVM_SETTINGS;
6136 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6137 unsigned int tmp;
6138
6139 if (sel >= items)
6140 return 0;
6141
6142 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6143 sel, out_svm_set_enum_str[sel]);
6144
6145 spec->smart_volume_setting = sel;
6146
6147 switch (sel) {
6148 case 0:
6149 tmp = FLOAT_ZERO;
6150 break;
6151 case 1:
6152 tmp = FLOAT_ONE;
6153 break;
6154 case 2:
6155 tmp = FLOAT_TWO;
6156 break;
6157 default:
6158 tmp = FLOAT_ZERO;
6159 break;
6160 }
6161 /* Req 2 is the Smart Volume Setting req. */
6162 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6163 ca0132_effects[idx].reqs[2], tmp);
6164 return 1;
6165 }
6166
6167 /* Sound Blaster Z EQ preset controls */
ca0132_alt_eq_preset_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6168 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6169 struct snd_ctl_elem_info *uinfo)
6170 {
6171 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6172
6173 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6174 uinfo->count = 1;
6175 uinfo->value.enumerated.items = items;
6176 if (uinfo->value.enumerated.item >= items)
6177 uinfo->value.enumerated.item = items - 1;
6178 strscpy(uinfo->value.enumerated.name,
6179 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6180 return 0;
6181 }
6182
ca0132_alt_eq_preset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6183 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6184 struct snd_ctl_elem_value *ucontrol)
6185 {
6186 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6187 struct ca0132_spec *spec = codec->spec;
6188
6189 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6190 return 0;
6191 }
6192
ca0132_alt_eq_preset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6193 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6194 struct snd_ctl_elem_value *ucontrol)
6195 {
6196 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6197 struct ca0132_spec *spec = codec->spec;
6198 int i, err = 0;
6199 int sel = ucontrol->value.enumerated.item[0];
6200 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6201
6202 if (sel >= items)
6203 return 0;
6204
6205 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6206 ca0132_alt_eq_presets[sel].name);
6207 /*
6208 * Idx 0 is default.
6209 * Default needs to qualify with CrystalVoice state.
6210 */
6211 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6212 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6213 ca0132_alt_eq_enum.reqs[i],
6214 ca0132_alt_eq_presets[sel].vals[i]);
6215 if (err < 0)
6216 break;
6217 }
6218
6219 if (err >= 0)
6220 spec->eq_preset_val = sel;
6221
6222 return 1;
6223 }
6224
ca0132_voicefx_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6225 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6226 struct snd_ctl_elem_info *uinfo)
6227 {
6228 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6229
6230 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6231 uinfo->count = 1;
6232 uinfo->value.enumerated.items = items;
6233 if (uinfo->value.enumerated.item >= items)
6234 uinfo->value.enumerated.item = items - 1;
6235 strscpy(uinfo->value.enumerated.name,
6236 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6237 return 0;
6238 }
6239
ca0132_voicefx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6240 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6241 struct snd_ctl_elem_value *ucontrol)
6242 {
6243 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6244 struct ca0132_spec *spec = codec->spec;
6245
6246 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6247 return 0;
6248 }
6249
ca0132_voicefx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6250 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6251 struct snd_ctl_elem_value *ucontrol)
6252 {
6253 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6254 struct ca0132_spec *spec = codec->spec;
6255 int i, err = 0;
6256 int sel = ucontrol->value.enumerated.item[0];
6257
6258 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6259 return 0;
6260
6261 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6262 sel, ca0132_voicefx_presets[sel].name);
6263
6264 /*
6265 * Idx 0 is default.
6266 * Default needs to qualify with CrystalVoice state.
6267 */
6268 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6269 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6270 ca0132_voicefx.reqs[i],
6271 ca0132_voicefx_presets[sel].vals[i]);
6272 if (err < 0)
6273 break;
6274 }
6275
6276 if (err >= 0) {
6277 spec->voicefx_val = sel;
6278 /* enable voice fx */
6279 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6280 }
6281
6282 return 1;
6283 }
6284
ca0132_switch_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6285 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6286 struct snd_ctl_elem_value *ucontrol)
6287 {
6288 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6289 struct ca0132_spec *spec = codec->spec;
6290 hda_nid_t nid = get_amp_nid(kcontrol);
6291 int ch = get_amp_channels(kcontrol);
6292 long *valp = ucontrol->value.integer.value;
6293
6294 /* vnode */
6295 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6296 if (ch & 1) {
6297 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6298 valp++;
6299 }
6300 if (ch & 2) {
6301 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6302 valp++;
6303 }
6304 return 0;
6305 }
6306
6307 /* effects, include PE and CrystalVoice */
6308 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6309 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6310 return 0;
6311 }
6312
6313 /* mic boost */
6314 if (nid == spec->input_pins[0]) {
6315 *valp = spec->cur_mic_boost;
6316 return 0;
6317 }
6318
6319 if (nid == ZXR_HEADPHONE_GAIN) {
6320 *valp = spec->zxr_gain_set;
6321 return 0;
6322 }
6323
6324 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6325 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6326 return 0;
6327 }
6328
6329 if (nid == BASS_REDIRECTION) {
6330 *valp = spec->bass_redirection_val;
6331 return 0;
6332 }
6333
6334 return 0;
6335 }
6336
ca0132_switch_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6337 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6338 struct snd_ctl_elem_value *ucontrol)
6339 {
6340 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6341 struct ca0132_spec *spec = codec->spec;
6342 hda_nid_t nid = get_amp_nid(kcontrol);
6343 int ch = get_amp_channels(kcontrol);
6344 long *valp = ucontrol->value.integer.value;
6345 int changed = 1;
6346
6347 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6348 nid, *valp);
6349
6350 snd_hda_power_up(codec);
6351 /* vnode */
6352 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6353 if (ch & 1) {
6354 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6355 valp++;
6356 }
6357 if (ch & 2) {
6358 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6359 valp++;
6360 }
6361 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6362 goto exit;
6363 }
6364
6365 /* PE */
6366 if (nid == PLAY_ENHANCEMENT) {
6367 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6368 changed = ca0132_pe_switch_set(codec);
6369 goto exit;
6370 }
6371
6372 /* CrystalVoice */
6373 if (nid == CRYSTAL_VOICE) {
6374 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6375 changed = ca0132_cvoice_switch_set(codec);
6376 goto exit;
6377 }
6378
6379 /* out and in effects */
6380 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6381 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6382 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6383 changed = ca0132_effects_set(codec, nid, *valp);
6384 goto exit;
6385 }
6386
6387 /* mic boost */
6388 if (nid == spec->input_pins[0]) {
6389 spec->cur_mic_boost = *valp;
6390 if (ca0132_use_alt_functions(spec)) {
6391 if (spec->in_enum_val != REAR_LINE_IN)
6392 changed = ca0132_mic_boost_set(codec, *valp);
6393 } else {
6394 /* Mic boost does not apply to Digital Mic */
6395 if (spec->cur_mic_type != DIGITAL_MIC)
6396 changed = ca0132_mic_boost_set(codec, *valp);
6397 }
6398
6399 goto exit;
6400 }
6401
6402 if (nid == ZXR_HEADPHONE_GAIN) {
6403 spec->zxr_gain_set = *valp;
6404 if (spec->cur_out_type == HEADPHONE_OUT)
6405 changed = zxr_headphone_gain_set(codec, *valp);
6406 else
6407 changed = 0;
6408
6409 goto exit;
6410 }
6411
6412 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6413 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6414 if (spec->cur_out_type == SPEAKER_OUT)
6415 ca0132_alt_set_full_range_speaker(codec);
6416
6417 changed = 0;
6418 }
6419
6420 if (nid == BASS_REDIRECTION) {
6421 spec->bass_redirection_val = *valp;
6422 if (spec->cur_out_type == SPEAKER_OUT)
6423 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6424
6425 changed = 0;
6426 }
6427
6428 exit:
6429 snd_hda_power_down(codec);
6430 return changed;
6431 }
6432
6433 /*
6434 * Volume related
6435 */
6436 /*
6437 * Sets the internal DSP decibel level to match the DAC for output, and the
6438 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6439 * all alternative codecs set DSP playback volume.
6440 */
ca0132_alt_dsp_volume_put(struct hda_codec * codec,hda_nid_t nid)6441 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6442 {
6443 struct ca0132_spec *spec = codec->spec;
6444 unsigned int dsp_dir;
6445 unsigned int lookup_val;
6446
6447 if (nid == VNID_SPK)
6448 dsp_dir = DSP_VOL_OUT;
6449 else
6450 dsp_dir = DSP_VOL_IN;
6451
6452 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6453
6454 dspio_set_uint_param(codec,
6455 ca0132_alt_vol_ctls[dsp_dir].mid,
6456 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6457 float_vol_db_lookup[lookup_val]);
6458
6459 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6460
6461 dspio_set_uint_param(codec,
6462 ca0132_alt_vol_ctls[dsp_dir].mid,
6463 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6464 float_vol_db_lookup[lookup_val]);
6465
6466 dspio_set_uint_param(codec,
6467 ca0132_alt_vol_ctls[dsp_dir].mid,
6468 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6469 }
6470
ca0132_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6471 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6472 struct snd_ctl_elem_info *uinfo)
6473 {
6474 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6475 struct ca0132_spec *spec = codec->spec;
6476 hda_nid_t nid = get_amp_nid(kcontrol);
6477 int ch = get_amp_channels(kcontrol);
6478 int dir = get_amp_direction(kcontrol);
6479 unsigned long pval;
6480 int err;
6481
6482 switch (nid) {
6483 case VNID_SPK:
6484 /* follow shared_out info */
6485 nid = spec->shared_out_nid;
6486 mutex_lock(&codec->control_mutex);
6487 pval = kcontrol->private_value;
6488 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6489 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6490 kcontrol->private_value = pval;
6491 mutex_unlock(&codec->control_mutex);
6492 break;
6493 case VNID_MIC:
6494 /* follow shared_mic info */
6495 nid = spec->shared_mic_nid;
6496 mutex_lock(&codec->control_mutex);
6497 pval = kcontrol->private_value;
6498 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6499 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6500 kcontrol->private_value = pval;
6501 mutex_unlock(&codec->control_mutex);
6502 break;
6503 default:
6504 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6505 }
6506 return err;
6507 }
6508
ca0132_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6509 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6510 struct snd_ctl_elem_value *ucontrol)
6511 {
6512 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6513 struct ca0132_spec *spec = codec->spec;
6514 hda_nid_t nid = get_amp_nid(kcontrol);
6515 int ch = get_amp_channels(kcontrol);
6516 long *valp = ucontrol->value.integer.value;
6517
6518 /* store the left and right volume */
6519 if (ch & 1) {
6520 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6521 valp++;
6522 }
6523 if (ch & 2) {
6524 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6525 valp++;
6526 }
6527 return 0;
6528 }
6529
ca0132_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6530 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6531 struct snd_ctl_elem_value *ucontrol)
6532 {
6533 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6534 struct ca0132_spec *spec = codec->spec;
6535 hda_nid_t nid = get_amp_nid(kcontrol);
6536 int ch = get_amp_channels(kcontrol);
6537 long *valp = ucontrol->value.integer.value;
6538 hda_nid_t shared_nid = 0;
6539 bool effective;
6540 int changed = 1;
6541
6542 /* store the left and right volume */
6543 if (ch & 1) {
6544 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6545 valp++;
6546 }
6547 if (ch & 2) {
6548 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6549 valp++;
6550 }
6551
6552 /* if effective conditions, then update hw immediately. */
6553 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6554 if (effective) {
6555 int dir = get_amp_direction(kcontrol);
6556 unsigned long pval;
6557
6558 snd_hda_power_up(codec);
6559 mutex_lock(&codec->control_mutex);
6560 pval = kcontrol->private_value;
6561 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6562 0, dir);
6563 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6564 kcontrol->private_value = pval;
6565 mutex_unlock(&codec->control_mutex);
6566 snd_hda_power_down(codec);
6567 }
6568
6569 return changed;
6570 }
6571
6572 /*
6573 * This function is the same as the one above, because using an if statement
6574 * inside of the above volume control for the DSP volume would cause too much
6575 * lag. This is a lot more smooth.
6576 */
ca0132_alt_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6577 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6578 struct snd_ctl_elem_value *ucontrol)
6579 {
6580 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6581 struct ca0132_spec *spec = codec->spec;
6582 hda_nid_t nid = get_amp_nid(kcontrol);
6583 int ch = get_amp_channels(kcontrol);
6584 long *valp = ucontrol->value.integer.value;
6585 hda_nid_t vnid = 0;
6586 int changed;
6587
6588 switch (nid) {
6589 case 0x02:
6590 vnid = VNID_SPK;
6591 break;
6592 case 0x07:
6593 vnid = VNID_MIC;
6594 break;
6595 }
6596
6597 /* store the left and right volume */
6598 if (ch & 1) {
6599 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6600 valp++;
6601 }
6602 if (ch & 2) {
6603 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6604 valp++;
6605 }
6606
6607 snd_hda_power_up(codec);
6608 ca0132_alt_dsp_volume_put(codec, vnid);
6609 mutex_lock(&codec->control_mutex);
6610 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6611 mutex_unlock(&codec->control_mutex);
6612 snd_hda_power_down(codec);
6613
6614 return changed;
6615 }
6616
ca0132_volume_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)6617 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6618 unsigned int size, unsigned int __user *tlv)
6619 {
6620 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6621 struct ca0132_spec *spec = codec->spec;
6622 hda_nid_t nid = get_amp_nid(kcontrol);
6623 int ch = get_amp_channels(kcontrol);
6624 int dir = get_amp_direction(kcontrol);
6625 unsigned long pval;
6626 int err;
6627
6628 switch (nid) {
6629 case VNID_SPK:
6630 /* follow shared_out tlv */
6631 nid = spec->shared_out_nid;
6632 mutex_lock(&codec->control_mutex);
6633 pval = kcontrol->private_value;
6634 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6635 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6636 kcontrol->private_value = pval;
6637 mutex_unlock(&codec->control_mutex);
6638 break;
6639 case VNID_MIC:
6640 /* follow shared_mic tlv */
6641 nid = spec->shared_mic_nid;
6642 mutex_lock(&codec->control_mutex);
6643 pval = kcontrol->private_value;
6644 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6645 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6646 kcontrol->private_value = pval;
6647 mutex_unlock(&codec->control_mutex);
6648 break;
6649 default:
6650 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6651 }
6652 return err;
6653 }
6654
6655 /* Add volume slider control for effect level */
ca0132_alt_add_effect_slider(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6656 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6657 const char *pfx, int dir)
6658 {
6659 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6660 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6661 struct snd_kcontrol_new knew =
6662 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6663
6664 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6665
6666 knew.tlv.c = NULL;
6667
6668 switch (nid) {
6669 case XBASS_XOVER:
6670 knew.info = ca0132_alt_xbass_xover_slider_info;
6671 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6672 knew.put = ca0132_alt_xbass_xover_slider_put;
6673 break;
6674 default:
6675 knew.info = ca0132_alt_effect_slider_info;
6676 knew.get = ca0132_alt_slider_ctl_get;
6677 knew.put = ca0132_alt_effect_slider_put;
6678 knew.private_value =
6679 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6680 break;
6681 }
6682
6683 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6684 }
6685
6686 /*
6687 * Added FX: prefix for the alternative codecs, because otherwise the surround
6688 * effect would conflict with the Surround sound volume control. Also seems more
6689 * clear as to what the switches do. Left alone for others.
6690 */
add_fx_switch(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6691 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6692 const char *pfx, int dir)
6693 {
6694 struct ca0132_spec *spec = codec->spec;
6695 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6696 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6697 struct snd_kcontrol_new knew =
6698 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6699 /* If using alt_controls, add FX: prefix. But, don't add FX:
6700 * prefix to OutFX or InFX enable controls.
6701 */
6702 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6703 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6704 else
6705 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6706
6707 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6708 }
6709
add_voicefx(struct hda_codec * codec)6710 static int add_voicefx(struct hda_codec *codec)
6711 {
6712 struct snd_kcontrol_new knew =
6713 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6714 VOICEFX, 1, 0, HDA_INPUT);
6715 knew.info = ca0132_voicefx_info;
6716 knew.get = ca0132_voicefx_get;
6717 knew.put = ca0132_voicefx_put;
6718 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6719 }
6720
6721 /* Create the EQ Preset control */
add_ca0132_alt_eq_presets(struct hda_codec * codec)6722 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6723 {
6724 struct snd_kcontrol_new knew =
6725 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6726 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6727 knew.info = ca0132_alt_eq_preset_info;
6728 knew.get = ca0132_alt_eq_preset_get;
6729 knew.put = ca0132_alt_eq_preset_put;
6730 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6731 snd_ctl_new1(&knew, codec));
6732 }
6733
6734 /*
6735 * Add enumerated control for the three different settings of the smart volume
6736 * output effect. Normal just uses the slider value, and loud and night are
6737 * their own things that ignore that value.
6738 */
ca0132_alt_add_svm_enum(struct hda_codec * codec)6739 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6740 {
6741 struct snd_kcontrol_new knew =
6742 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6743 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6744 knew.info = ca0132_alt_svm_setting_info;
6745 knew.get = ca0132_alt_svm_setting_get;
6746 knew.put = ca0132_alt_svm_setting_put;
6747 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6748 snd_ctl_new1(&knew, codec));
6749
6750 }
6751
6752 /*
6753 * Create an Output Select enumerated control for codecs with surround
6754 * out capabilities.
6755 */
ca0132_alt_add_output_enum(struct hda_codec * codec)6756 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6757 {
6758 struct snd_kcontrol_new knew =
6759 HDA_CODEC_MUTE_MONO("Output Select",
6760 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6761 knew.info = ca0132_alt_output_select_get_info;
6762 knew.get = ca0132_alt_output_select_get;
6763 knew.put = ca0132_alt_output_select_put;
6764 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6765 snd_ctl_new1(&knew, codec));
6766 }
6767
6768 /*
6769 * Add a control for selecting channel count on speaker output. Setting this
6770 * allows the DSP to do bass redirection and channel upmixing on surround
6771 * configurations.
6772 */
ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec * codec)6773 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6774 {
6775 struct snd_kcontrol_new knew =
6776 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6777 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6778 knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6779 knew.get = ca0132_alt_speaker_channel_cfg_get;
6780 knew.put = ca0132_alt_speaker_channel_cfg_put;
6781 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6782 snd_ctl_new1(&knew, codec));
6783 }
6784
6785 /*
6786 * Full range front stereo and rear surround switches. When these are set to
6787 * full range, the lower frequencies from these channels are no longer
6788 * redirected to the LFE channel.
6789 */
ca0132_alt_add_front_full_range_switch(struct hda_codec * codec)6790 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6791 {
6792 struct snd_kcontrol_new knew =
6793 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6794 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6795
6796 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6797 snd_ctl_new1(&knew, codec));
6798 }
6799
ca0132_alt_add_rear_full_range_switch(struct hda_codec * codec)6800 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6801 {
6802 struct snd_kcontrol_new knew =
6803 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6804 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6805
6806 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6807 snd_ctl_new1(&knew, codec));
6808 }
6809
6810 /*
6811 * Bass redirection redirects audio below the crossover frequency to the LFE
6812 * channel on speakers that are set as not being full-range. On configurations
6813 * without an LFE channel, it does nothing. Bass redirection seems to be the
6814 * replacement for X-Bass on configurations with an LFE channel.
6815 */
ca0132_alt_add_bass_redirection_crossover(struct hda_codec * codec)6816 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6817 {
6818 const char *namestr = "Bass Redirection Crossover";
6819 struct snd_kcontrol_new knew =
6820 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6821 HDA_OUTPUT);
6822
6823 knew.tlv.c = NULL;
6824 knew.info = ca0132_alt_xbass_xover_slider_info;
6825 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6826 knew.put = ca0132_alt_xbass_xover_slider_put;
6827
6828 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6829 snd_ctl_new1(&knew, codec));
6830 }
6831
ca0132_alt_add_bass_redirection_switch(struct hda_codec * codec)6832 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6833 {
6834 const char *namestr = "Bass Redirection";
6835 struct snd_kcontrol_new knew =
6836 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6837 HDA_OUTPUT);
6838
6839 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6840 snd_ctl_new1(&knew, codec));
6841 }
6842
6843 /*
6844 * Create an Input Source enumerated control for the alternate ca0132 codecs
6845 * because the front microphone has no auto-detect, and Line-in has to be set
6846 * somehow.
6847 */
ca0132_alt_add_input_enum(struct hda_codec * codec)6848 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6849 {
6850 struct snd_kcontrol_new knew =
6851 HDA_CODEC_MUTE_MONO("Input Source",
6852 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6853 knew.info = ca0132_alt_input_source_info;
6854 knew.get = ca0132_alt_input_source_get;
6855 knew.put = ca0132_alt_input_source_put;
6856 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6857 snd_ctl_new1(&knew, codec));
6858 }
6859
6860 /*
6861 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6862 * more control than the original mic boost, which is either full 30dB or off.
6863 */
ca0132_alt_add_mic_boost_enum(struct hda_codec * codec)6864 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6865 {
6866 struct snd_kcontrol_new knew =
6867 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6868 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6869 knew.info = ca0132_alt_mic_boost_info;
6870 knew.get = ca0132_alt_mic_boost_get;
6871 knew.put = ca0132_alt_mic_boost_put;
6872 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6873 snd_ctl_new1(&knew, codec));
6874
6875 }
6876
6877 /*
6878 * Add headphone gain enumerated control for the AE-5. This switches between
6879 * three modes, low, medium, and high. When non-headphone outputs are selected,
6880 * it is automatically set to high. This is the same behavior as Windows.
6881 */
ae5_add_headphone_gain_enum(struct hda_codec * codec)6882 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6883 {
6884 struct snd_kcontrol_new knew =
6885 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6886 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6887 knew.info = ae5_headphone_gain_info;
6888 knew.get = ae5_headphone_gain_get;
6889 knew.put = ae5_headphone_gain_put;
6890 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6891 snd_ctl_new1(&knew, codec));
6892 }
6893
6894 /*
6895 * Add sound filter enumerated control for the AE-5. This adds three different
6896 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6897 * read into it, it changes the DAC's interpolation filter.
6898 */
ae5_add_sound_filter_enum(struct hda_codec * codec)6899 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6900 {
6901 struct snd_kcontrol_new knew =
6902 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6903 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6904 knew.info = ae5_sound_filter_info;
6905 knew.get = ae5_sound_filter_get;
6906 knew.put = ae5_sound_filter_put;
6907 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6908 snd_ctl_new1(&knew, codec));
6909 }
6910
zxr_add_headphone_gain_switch(struct hda_codec * codec)6911 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6912 {
6913 struct snd_kcontrol_new knew =
6914 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6915 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6916
6917 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6918 snd_ctl_new1(&knew, codec));
6919 }
6920
6921 /*
6922 * Need to create follower controls for the alternate codecs that have surround
6923 * capabilities.
6924 */
6925 static const char * const ca0132_alt_follower_pfxs[] = {
6926 "Front", "Surround", "Center", "LFE", NULL,
6927 };
6928
6929 /*
6930 * Also need special channel map, because the default one is incorrect.
6931 * I think this has to do with the pin for rear surround being 0x11,
6932 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6933 */
6934 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6935 { .channels = 2,
6936 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6937 { .channels = 4,
6938 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6939 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6940 { .channels = 6,
6941 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6942 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6943 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6944 { }
6945 };
6946
6947 /* Add the correct chmap for streams with 6 channels. */
ca0132_alt_add_chmap_ctls(struct hda_codec * codec)6948 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6949 {
6950 int err = 0;
6951 struct hda_pcm *pcm;
6952
6953 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6954 struct hda_pcm_stream *hinfo =
6955 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6956 struct snd_pcm_chmap *chmap;
6957 const struct snd_pcm_chmap_elem *elem;
6958
6959 elem = ca0132_alt_chmaps;
6960 if (hinfo->channels_max == 6) {
6961 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6962 SNDRV_PCM_STREAM_PLAYBACK,
6963 elem, hinfo->channels_max, 0, &chmap);
6964 if (err < 0)
6965 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6966 }
6967 }
6968 }
6969
6970 /*
6971 * When changing Node IDs for Mixer Controls below, make sure to update
6972 * Node IDs in ca0132_config() as well.
6973 */
6974 static const struct snd_kcontrol_new ca0132_mixer[] = {
6975 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6976 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6977 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6978 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6979 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6980 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6981 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6982 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6983 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6984 0x12, 1, HDA_INPUT),
6985 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6986 VNID_HP_SEL, 1, HDA_OUTPUT),
6987 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6988 VNID_AMIC1_SEL, 1, HDA_INPUT),
6989 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6990 VNID_HP_ASEL, 1, HDA_OUTPUT),
6991 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6992 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6993 { } /* end */
6994 };
6995
6996 /*
6997 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6998 * surround controls. Also sets both the Front Playback and Capture Volume
6999 * controls to alt so they set the DSP's decibel level.
7000 */
7001 static const struct snd_kcontrol_new desktop_mixer[] = {
7002 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7003 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
7004 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7005 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7006 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7007 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7008 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7009 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7010 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
7011 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7012 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7013 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7014 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7015 VNID_HP_ASEL, 1, HDA_OUTPUT),
7016 { } /* end */
7017 };
7018
7019 /*
7020 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
7021 * because it doesn't set decibel levels for the DSP for capture.
7022 */
7023 static const struct snd_kcontrol_new r3di_mixer[] = {
7024 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7025 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
7026 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7027 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7028 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7029 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7030 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7031 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7032 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
7033 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7034 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7035 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7036 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7037 VNID_HP_ASEL, 1, HDA_OUTPUT),
7038 { } /* end */
7039 };
7040
ca0132_build_controls(struct hda_codec * codec)7041 static int ca0132_build_controls(struct hda_codec *codec)
7042 {
7043 struct ca0132_spec *spec = codec->spec;
7044 int i, num_fx, num_sliders;
7045 int err = 0;
7046
7047 /* Add Mixer controls */
7048 for (i = 0; i < spec->num_mixers; i++) {
7049 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
7050 if (err < 0)
7051 return err;
7052 }
7053 /* Setup vmaster with surround followers for desktop ca0132 devices */
7054 if (ca0132_use_alt_functions(spec)) {
7055 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7056 spec->tlv);
7057 snd_hda_add_vmaster(codec, "Master Playback Volume",
7058 spec->tlv, ca0132_alt_follower_pfxs,
7059 "Playback Volume", 0);
7060 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7061 NULL, ca0132_alt_follower_pfxs,
7062 "Playback Switch",
7063 true, 0, &spec->vmaster_mute.sw_kctl);
7064 if (err < 0)
7065 return err;
7066 }
7067
7068 /* Add in and out effects controls.
7069 * VoiceFX, PE and CrystalVoice are added separately.
7070 */
7071 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7072 for (i = 0; i < num_fx; i++) {
7073 /* Desktop cards break if Echo Cancellation is used. */
7074 if (ca0132_use_pci_mmio(spec)) {
7075 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7076 OUT_EFFECTS_COUNT))
7077 continue;
7078 }
7079
7080 err = add_fx_switch(codec, ca0132_effects[i].nid,
7081 ca0132_effects[i].name,
7082 ca0132_effects[i].direct);
7083 if (err < 0)
7084 return err;
7085 }
7086 /*
7087 * If codec has use_alt_controls set to true, add effect level sliders,
7088 * EQ presets, and Smart Volume presets. Also, change names to add FX
7089 * prefix, and change PlayEnhancement and CrystalVoice to match.
7090 */
7091 if (ca0132_use_alt_controls(spec)) {
7092 err = ca0132_alt_add_svm_enum(codec);
7093 if (err < 0)
7094 return err;
7095
7096 err = add_ca0132_alt_eq_presets(codec);
7097 if (err < 0)
7098 return err;
7099
7100 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7101 "Enable OutFX", 0);
7102 if (err < 0)
7103 return err;
7104
7105 err = add_fx_switch(codec, CRYSTAL_VOICE,
7106 "Enable InFX", 1);
7107 if (err < 0)
7108 return err;
7109
7110 num_sliders = OUT_EFFECTS_COUNT - 1;
7111 for (i = 0; i < num_sliders; i++) {
7112 err = ca0132_alt_add_effect_slider(codec,
7113 ca0132_effects[i].nid,
7114 ca0132_effects[i].name,
7115 ca0132_effects[i].direct);
7116 if (err < 0)
7117 return err;
7118 }
7119
7120 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7121 "X-Bass Crossover", EFX_DIR_OUT);
7122
7123 if (err < 0)
7124 return err;
7125 } else {
7126 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7127 "PlayEnhancement", 0);
7128 if (err < 0)
7129 return err;
7130
7131 err = add_fx_switch(codec, CRYSTAL_VOICE,
7132 "CrystalVoice", 1);
7133 if (err < 0)
7134 return err;
7135 }
7136 err = add_voicefx(codec);
7137 if (err < 0)
7138 return err;
7139
7140 /*
7141 * If the codec uses alt_functions, you need the enumerated controls
7142 * to select the new outputs and inputs, plus add the new mic boost
7143 * setting control.
7144 */
7145 if (ca0132_use_alt_functions(spec)) {
7146 err = ca0132_alt_add_output_enum(codec);
7147 if (err < 0)
7148 return err;
7149 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7150 if (err < 0)
7151 return err;
7152 err = ca0132_alt_add_front_full_range_switch(codec);
7153 if (err < 0)
7154 return err;
7155 err = ca0132_alt_add_rear_full_range_switch(codec);
7156 if (err < 0)
7157 return err;
7158 err = ca0132_alt_add_bass_redirection_crossover(codec);
7159 if (err < 0)
7160 return err;
7161 err = ca0132_alt_add_bass_redirection_switch(codec);
7162 if (err < 0)
7163 return err;
7164 err = ca0132_alt_add_mic_boost_enum(codec);
7165 if (err < 0)
7166 return err;
7167 /*
7168 * ZxR only has microphone input, there is no front panel
7169 * header on the card, and aux-in is handled by the DBPro board.
7170 */
7171 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7172 err = ca0132_alt_add_input_enum(codec);
7173 if (err < 0)
7174 return err;
7175 }
7176 }
7177
7178 switch (ca0132_quirk(spec)) {
7179 case QUIRK_AE5:
7180 case QUIRK_AE7:
7181 err = ae5_add_headphone_gain_enum(codec);
7182 if (err < 0)
7183 return err;
7184 err = ae5_add_sound_filter_enum(codec);
7185 if (err < 0)
7186 return err;
7187 break;
7188 case QUIRK_ZXR:
7189 err = zxr_add_headphone_gain_switch(codec);
7190 if (err < 0)
7191 return err;
7192 break;
7193 default:
7194 break;
7195 }
7196
7197 #ifdef ENABLE_TUNING_CONTROLS
7198 add_tuning_ctls(codec);
7199 #endif
7200
7201 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7202 if (err < 0)
7203 return err;
7204
7205 if (spec->dig_out) {
7206 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7207 spec->dig_out);
7208 if (err < 0)
7209 return err;
7210 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7211 if (err < 0)
7212 return err;
7213 /* spec->multiout.share_spdif = 1; */
7214 }
7215
7216 if (spec->dig_in) {
7217 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7218 if (err < 0)
7219 return err;
7220 }
7221
7222 if (ca0132_use_alt_functions(spec))
7223 ca0132_alt_add_chmap_ctls(codec);
7224
7225 return 0;
7226 }
7227
dbpro_build_controls(struct hda_codec * codec)7228 static int dbpro_build_controls(struct hda_codec *codec)
7229 {
7230 struct ca0132_spec *spec = codec->spec;
7231 int err = 0;
7232
7233 if (spec->dig_out) {
7234 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7235 spec->dig_out);
7236 if (err < 0)
7237 return err;
7238 }
7239
7240 if (spec->dig_in) {
7241 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7242 if (err < 0)
7243 return err;
7244 }
7245
7246 return 0;
7247 }
7248
7249 /*
7250 * PCM
7251 */
7252 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7253 .substreams = 1,
7254 .channels_min = 2,
7255 .channels_max = 6,
7256 .ops = {
7257 .prepare = ca0132_playback_pcm_prepare,
7258 .cleanup = ca0132_playback_pcm_cleanup,
7259 .get_delay = ca0132_playback_pcm_delay,
7260 },
7261 };
7262
7263 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7264 .substreams = 1,
7265 .channels_min = 2,
7266 .channels_max = 2,
7267 .ops = {
7268 .prepare = ca0132_capture_pcm_prepare,
7269 .cleanup = ca0132_capture_pcm_cleanup,
7270 .get_delay = ca0132_capture_pcm_delay,
7271 },
7272 };
7273
7274 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7275 .substreams = 1,
7276 .channels_min = 2,
7277 .channels_max = 2,
7278 .ops = {
7279 .open = ca0132_dig_playback_pcm_open,
7280 .close = ca0132_dig_playback_pcm_close,
7281 .prepare = ca0132_dig_playback_pcm_prepare,
7282 .cleanup = ca0132_dig_playback_pcm_cleanup
7283 },
7284 };
7285
7286 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7287 .substreams = 1,
7288 .channels_min = 2,
7289 .channels_max = 2,
7290 };
7291
ca0132_build_pcms(struct hda_codec * codec)7292 static int ca0132_build_pcms(struct hda_codec *codec)
7293 {
7294 struct ca0132_spec *spec = codec->spec;
7295 struct hda_pcm *info;
7296
7297 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7298 if (!info)
7299 return -ENOMEM;
7300 if (ca0132_use_alt_functions(spec)) {
7301 info->own_chmap = true;
7302 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7303 = ca0132_alt_chmaps;
7304 }
7305 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7306 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7307 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7308 spec->multiout.max_channels;
7309 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7310 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7311 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7312
7313 /* With the DSP enabled, desktops don't use this ADC. */
7314 if (!ca0132_use_alt_functions(spec)) {
7315 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7316 if (!info)
7317 return -ENOMEM;
7318 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7319 ca0132_pcm_analog_capture;
7320 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7321 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7322 }
7323
7324 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7325 if (!info)
7326 return -ENOMEM;
7327 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7328 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7329 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7330
7331 if (!spec->dig_out && !spec->dig_in)
7332 return 0;
7333
7334 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7335 if (!info)
7336 return -ENOMEM;
7337 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7338 if (spec->dig_out) {
7339 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7340 ca0132_pcm_digital_playback;
7341 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7342 }
7343 if (spec->dig_in) {
7344 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7345 ca0132_pcm_digital_capture;
7346 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7347 }
7348
7349 return 0;
7350 }
7351
dbpro_build_pcms(struct hda_codec * codec)7352 static int dbpro_build_pcms(struct hda_codec *codec)
7353 {
7354 struct ca0132_spec *spec = codec->spec;
7355 struct hda_pcm *info;
7356
7357 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7358 if (!info)
7359 return -ENOMEM;
7360 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7361 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7362 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7363
7364
7365 if (!spec->dig_out && !spec->dig_in)
7366 return 0;
7367
7368 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7369 if (!info)
7370 return -ENOMEM;
7371 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7372 if (spec->dig_out) {
7373 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7374 ca0132_pcm_digital_playback;
7375 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7376 }
7377 if (spec->dig_in) {
7378 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7379 ca0132_pcm_digital_capture;
7380 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7381 }
7382
7383 return 0;
7384 }
7385
init_output(struct hda_codec * codec,hda_nid_t pin,hda_nid_t dac)7386 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7387 {
7388 if (pin) {
7389 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7390 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7391 snd_hda_codec_write(codec, pin, 0,
7392 AC_VERB_SET_AMP_GAIN_MUTE,
7393 AMP_OUT_UNMUTE);
7394 }
7395 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7396 snd_hda_codec_write(codec, dac, 0,
7397 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7398 }
7399
init_input(struct hda_codec * codec,hda_nid_t pin,hda_nid_t adc)7400 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7401 {
7402 if (pin) {
7403 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7404 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7405 snd_hda_codec_write(codec, pin, 0,
7406 AC_VERB_SET_AMP_GAIN_MUTE,
7407 AMP_IN_UNMUTE(0));
7408 }
7409 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7410 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7411 AMP_IN_UNMUTE(0));
7412
7413 /* init to 0 dB and unmute. */
7414 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7415 HDA_AMP_VOLMASK, 0x5a);
7416 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7417 HDA_AMP_MUTE, 0);
7418 }
7419 }
7420
refresh_amp_caps(struct hda_codec * codec,hda_nid_t nid,int dir)7421 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7422 {
7423 unsigned int caps;
7424
7425 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7426 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7427 snd_hda_override_amp_caps(codec, nid, dir, caps);
7428 }
7429
7430 /*
7431 * Switch between Digital built-in mic and analog mic.
7432 */
ca0132_set_dmic(struct hda_codec * codec,int enable)7433 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7434 {
7435 struct ca0132_spec *spec = codec->spec;
7436 unsigned int tmp;
7437 u8 val;
7438 unsigned int oldval;
7439
7440 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7441
7442 oldval = stop_mic1(codec);
7443 ca0132_set_vipsource(codec, 0);
7444 if (enable) {
7445 /* set DMic input as 2-ch */
7446 tmp = FLOAT_TWO;
7447 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7448
7449 val = spec->dmic_ctl;
7450 val |= 0x80;
7451 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7452 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7453
7454 if (!(spec->dmic_ctl & 0x20))
7455 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7456 } else {
7457 /* set AMic input as mono */
7458 tmp = FLOAT_ONE;
7459 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7460
7461 val = spec->dmic_ctl;
7462 /* clear bit7 and bit5 to disable dmic */
7463 val &= 0x5f;
7464 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7465 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7466
7467 if (!(spec->dmic_ctl & 0x20))
7468 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7469 }
7470 ca0132_set_vipsource(codec, 1);
7471 resume_mic1(codec, oldval);
7472 }
7473
7474 /*
7475 * Initialization for Digital Mic.
7476 */
ca0132_init_dmic(struct hda_codec * codec)7477 static void ca0132_init_dmic(struct hda_codec *codec)
7478 {
7479 struct ca0132_spec *spec = codec->spec;
7480 u8 val;
7481
7482 /* Setup Digital Mic here, but don't enable.
7483 * Enable based on jack detect.
7484 */
7485
7486 /* MCLK uses MPIO1, set to enable.
7487 * Bit 2-0: MPIO select
7488 * Bit 3: set to disable
7489 * Bit 7-4: reserved
7490 */
7491 val = 0x01;
7492 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7493 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7494
7495 /* Data1 uses MPIO3. Data2 not use
7496 * Bit 2-0: Data1 MPIO select
7497 * Bit 3: set disable Data1
7498 * Bit 6-4: Data2 MPIO select
7499 * Bit 7: set disable Data2
7500 */
7501 val = 0x83;
7502 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7503 VENDOR_CHIPIO_DMIC_PIN_SET, val);
7504
7505 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7506 * Bit 3-0: Channel mask
7507 * Bit 4: set for 48KHz, clear for 32KHz
7508 * Bit 5: mode
7509 * Bit 6: set to select Data2, clear for Data1
7510 * Bit 7: set to enable DMic, clear for AMic
7511 */
7512 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7513 val = 0x33;
7514 else
7515 val = 0x23;
7516 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7517 spec->dmic_ctl = val;
7518 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7519 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7520 }
7521
7522 /*
7523 * Initialization for Analog Mic 2
7524 */
ca0132_init_analog_mic2(struct hda_codec * codec)7525 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7526 {
7527 struct ca0132_spec *spec = codec->spec;
7528
7529 mutex_lock(&spec->chipio_mutex);
7530
7531 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7532 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7533
7534 mutex_unlock(&spec->chipio_mutex);
7535 }
7536
ca0132_refresh_widget_caps(struct hda_codec * codec)7537 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7538 {
7539 struct ca0132_spec *spec = codec->spec;
7540 int i;
7541
7542 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7543 snd_hda_codec_update_widgets(codec);
7544
7545 for (i = 0; i < spec->multiout.num_dacs; i++)
7546 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7547
7548 for (i = 0; i < spec->num_outputs; i++)
7549 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7550
7551 for (i = 0; i < spec->num_inputs; i++) {
7552 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7553 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7554 }
7555 }
7556
7557
7558 /* If there is an active channel for some reason, find it and free it. */
ca0132_alt_free_active_dma_channels(struct hda_codec * codec)7559 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7560 {
7561 unsigned int i, tmp;
7562 int status;
7563
7564 /* Read active DSPDMAC channel register. */
7565 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7566 if (status >= 0) {
7567 /* AND against 0xfff to get the active channel bits. */
7568 tmp = tmp & 0xfff;
7569
7570 /* If there are no active channels, nothing to free. */
7571 if (!tmp)
7572 return;
7573 } else {
7574 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7575 __func__);
7576 return;
7577 }
7578
7579 /*
7580 * Check each DSP DMA channel for activity, and if the channel is
7581 * active, free it.
7582 */
7583 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7584 if (dsp_is_dma_active(codec, i)) {
7585 status = dspio_free_dma_chan(codec, i);
7586 if (status < 0)
7587 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7588 __func__, i);
7589 }
7590 }
7591 }
7592
7593 /*
7594 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7595 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream.
7596 * Instead, audio is now routed through the DSP's DMA controllers, which
7597 * the DSP is tasked with setting up itself. Through debugging, it seems the
7598 * cause of most of the no-audio on startup issues were due to improperly
7599 * configured DSP DMA channels.
7600 *
7601 * Normally, the DSP configures these the first time an HDA audio stream is
7602 * started post DSP firmware download. That is why creating a 'dummy' stream
7603 * worked in fixing the audio in some cases. This works most of the time, but
7604 * sometimes if a stream is started/stopped before the DSP can setup the DMA
7605 * configuration registers, it ends up in a broken state. Issues can also
7606 * arise if streams are started in an unusual order, i.e the audio output dma
7607 * channel being sandwiched between the mic1 and mic2 dma channels.
7608 *
7609 * The solution to this is to make sure that the DSP has no DMA channels
7610 * in use post DSP firmware download, and then to manually start each default
7611 * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7612 * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7613 */
ca0132_alt_start_dsp_audio_streams(struct hda_codec * codec)7614 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7615 {
7616 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7617 struct ca0132_spec *spec = codec->spec;
7618 unsigned int i, tmp;
7619
7620 /*
7621 * Check if any of the default streams are active, and if they are,
7622 * stop them.
7623 */
7624 mutex_lock(&spec->chipio_mutex);
7625
7626 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7627 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7628
7629 if (tmp) {
7630 chipio_set_stream_control(codec,
7631 dsp_dma_stream_ids[i], 0);
7632 }
7633 }
7634
7635 mutex_unlock(&spec->chipio_mutex);
7636
7637 /*
7638 * If all DSP streams are inactive, there should be no active DSP DMA
7639 * channels. Check and make sure this is the case, and if it isn't,
7640 * free any active channels.
7641 */
7642 ca0132_alt_free_active_dma_channels(codec);
7643
7644 mutex_lock(&spec->chipio_mutex);
7645
7646 /* Make sure stream 0x0c is six channels. */
7647 chipio_set_stream_channels(codec, 0x0c, 6);
7648
7649 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7650 chipio_set_stream_control(codec,
7651 dsp_dma_stream_ids[i], 1);
7652
7653 /* Give the DSP some time to setup the DMA channel. */
7654 msleep(75);
7655 }
7656
7657 mutex_unlock(&spec->chipio_mutex);
7658 }
7659
7660 /*
7661 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7662 * router', where each entry represents a 48khz audio channel, with a format
7663 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7664 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7665 * and 3 if it's using Sample Rate Converter ports.
7666 * An example is:
7667 * 0x0001f8c0
7668 * In this case, f8 is the destination, and c0 is the source. The number value
7669 * is 1.
7670 * This region of memory is normally managed internally by the 8051, where
7671 * the region of exram memory from 0x1477-0x1575 has each byte represent an
7672 * entry within the 0x190000 range, and when a range of entries is in use, the
7673 * ending value is overwritten with 0xff.
7674 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7675 * streamID's, where each entry is a starting 0x190000 port offset.
7676 * 0x159d in exram is the same as 0x1578, except it contains the ending port
7677 * offset for the corresponding streamID.
7678 *
7679 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
7680 * the 8051, then manually overwritten to remap the ports to work with the
7681 * new DACs.
7682 *
7683 * Currently known portID's:
7684 * 0x00-0x1f: HDA audio stream input/output ports.
7685 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7686 * have the lower-nibble set to 0x1, 0x2, and 0x9.
7687 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7688 * 0xe0-0xff: DAC/ADC audio input/output ports.
7689 *
7690 * Currently known streamID's:
7691 * 0x03: Mic1 ADC to DSP.
7692 * 0x04: Mic2 ADC to DSP.
7693 * 0x05: HDA node 0x02 audio stream to DSP.
7694 * 0x0f: DSP Mic exit to HDA node 0x07.
7695 * 0x0c: DSP processed audio to DACs.
7696 * 0x14: DAC0, front L/R.
7697 *
7698 * It is possible to route the HDA audio streams directly to the DAC and
7699 * bypass the DSP entirely, with the only downside being that since the DSP
7700 * does volume control, the only volume control you'll get is through PCM on
7701 * the PC side, in the same way volume is handled for optical out. This may be
7702 * useful for debugging.
7703 */
chipio_remap_stream(struct hda_codec * codec,const struct chipio_stream_remap_data * remap_data)7704 static void chipio_remap_stream(struct hda_codec *codec,
7705 const struct chipio_stream_remap_data *remap_data)
7706 {
7707 unsigned int i, stream_offset;
7708
7709 /* Get the starting port for the stream to be remapped. */
7710 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7711 &stream_offset);
7712
7713 /*
7714 * Check if the stream's port value is 0xff, because the 8051 may not
7715 * have gotten around to setting up the stream yet. Wait until it's
7716 * setup to remap it's ports.
7717 */
7718 if (stream_offset == 0xff) {
7719 for (i = 0; i < 5; i++) {
7720 msleep(25);
7721
7722 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7723 &stream_offset);
7724
7725 if (stream_offset != 0xff)
7726 break;
7727 }
7728 }
7729
7730 if (stream_offset == 0xff) {
7731 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7732 __func__, remap_data->stream_id);
7733 return;
7734 }
7735
7736 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7737 stream_offset *= 0x04;
7738 stream_offset += 0x190000;
7739
7740 for (i = 0; i < remap_data->count; i++) {
7741 chipio_write_no_mutex(codec,
7742 stream_offset + remap_data->offset[i],
7743 remap_data->value[i]);
7744 }
7745
7746 /* Update stream map configuration. */
7747 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7748 }
7749
7750 /*
7751 * Default speaker tuning values setup for alternative codecs.
7752 */
7753 static const unsigned int sbz_default_delay_values[] = {
7754 /* Non-zero values are floating point 0.000198. */
7755 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7756 };
7757
7758 static const unsigned int zxr_default_delay_values[] = {
7759 /* Non-zero values are floating point 0.000220. */
7760 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7761 };
7762
7763 static const unsigned int ae5_default_delay_values[] = {
7764 /* Non-zero values are floating point 0.000100. */
7765 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7766 };
7767
7768 /*
7769 * If we never change these, probably only need them on initialization.
7770 */
ca0132_alt_init_speaker_tuning(struct hda_codec * codec)7771 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7772 {
7773 struct ca0132_spec *spec = codec->spec;
7774 unsigned int i, tmp, start_req, end_req;
7775 const unsigned int *values;
7776
7777 switch (ca0132_quirk(spec)) {
7778 case QUIRK_SBZ:
7779 values = sbz_default_delay_values;
7780 break;
7781 case QUIRK_ZXR:
7782 values = zxr_default_delay_values;
7783 break;
7784 case QUIRK_AE5:
7785 case QUIRK_AE7:
7786 values = ae5_default_delay_values;
7787 break;
7788 default:
7789 values = sbz_default_delay_values;
7790 break;
7791 }
7792
7793 tmp = FLOAT_ZERO;
7794 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7795
7796 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7797 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7798 for (i = start_req; i < end_req + 1; i++)
7799 dspio_set_uint_param(codec, 0x96, i, tmp);
7800
7801 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7802 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7803 for (i = start_req; i < end_req + 1; i++)
7804 dspio_set_uint_param(codec, 0x96, i, tmp);
7805
7806
7807 for (i = 0; i < 6; i++)
7808 dspio_set_uint_param(codec, 0x96,
7809 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7810 }
7811
7812 /*
7813 * Initialize mic for non-chromebook ca0132 implementations.
7814 */
ca0132_alt_init_analog_mics(struct hda_codec * codec)7815 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7816 {
7817 struct ca0132_spec *spec = codec->spec;
7818 unsigned int tmp;
7819
7820 /* Mic 1 Setup */
7821 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7822 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7823 if (ca0132_quirk(spec) == QUIRK_R3DI) {
7824 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7825 tmp = FLOAT_ONE;
7826 } else
7827 tmp = FLOAT_THREE;
7828 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7829
7830 /* Mic 2 setup (not present on desktop cards) */
7831 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7832 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7833 if (ca0132_quirk(spec) == QUIRK_R3DI)
7834 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7835 tmp = FLOAT_ZERO;
7836 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7837 }
7838
7839 /*
7840 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7841 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7842 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7843 * having an updated DAC, which changes the destination to that DAC.
7844 */
sbz_connect_streams(struct hda_codec * codec)7845 static void sbz_connect_streams(struct hda_codec *codec)
7846 {
7847 struct ca0132_spec *spec = codec->spec;
7848
7849 mutex_lock(&spec->chipio_mutex);
7850
7851 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7852
7853 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7854 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7855
7856 /* Setup stream 0x14 with it's source and destination points */
7857 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7858 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7859 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7860 chipio_set_stream_channels(codec, 0x14, 2);
7861 chipio_set_stream_control(codec, 0x14, 1);
7862
7863 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7864
7865 mutex_unlock(&spec->chipio_mutex);
7866 }
7867
7868 /*
7869 * Write data through ChipIO to setup proper stream destinations.
7870 * Not sure how it exactly works, but it seems to direct data
7871 * to different destinations. Example is f8 to c0, e0 to c0.
7872 * All I know is, if you don't set these, you get no sound.
7873 */
sbz_chipio_startup_data(struct hda_codec * codec)7874 static void sbz_chipio_startup_data(struct hda_codec *codec)
7875 {
7876 const struct chipio_stream_remap_data *dsp_out_remap_data;
7877 struct ca0132_spec *spec = codec->spec;
7878
7879 mutex_lock(&spec->chipio_mutex);
7880 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7881
7882 /* Remap DAC0's output ports. */
7883 chipio_remap_stream(codec, &stream_remap_data[0]);
7884
7885 /* Remap DSP audio output stream ports. */
7886 switch (ca0132_quirk(spec)) {
7887 case QUIRK_SBZ:
7888 dsp_out_remap_data = &stream_remap_data[1];
7889 break;
7890
7891 case QUIRK_ZXR:
7892 dsp_out_remap_data = &stream_remap_data[2];
7893 break;
7894
7895 default:
7896 dsp_out_remap_data = NULL;
7897 break;
7898 }
7899
7900 if (dsp_out_remap_data)
7901 chipio_remap_stream(codec, dsp_out_remap_data);
7902
7903 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7904 mutex_unlock(&spec->chipio_mutex);
7905 }
7906
ca0132_alt_dsp_initial_mic_setup(struct hda_codec * codec)7907 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7908 {
7909 struct ca0132_spec *spec = codec->spec;
7910 unsigned int tmp;
7911
7912 chipio_set_stream_control(codec, 0x03, 0);
7913 chipio_set_stream_control(codec, 0x04, 0);
7914
7915 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7916 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7917
7918 tmp = FLOAT_THREE;
7919 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7920
7921 chipio_set_stream_control(codec, 0x03, 1);
7922 chipio_set_stream_control(codec, 0x04, 1);
7923
7924 switch (ca0132_quirk(spec)) {
7925 case QUIRK_SBZ:
7926 chipio_write(codec, 0x18b098, 0x0000000c);
7927 chipio_write(codec, 0x18b09C, 0x0000000c);
7928 break;
7929 case QUIRK_AE5:
7930 chipio_write(codec, 0x18b098, 0x0000000c);
7931 chipio_write(codec, 0x18b09c, 0x0000004c);
7932 break;
7933 default:
7934 break;
7935 }
7936 }
7937
ae5_post_dsp_register_set(struct hda_codec * codec)7938 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7939 {
7940 struct ca0132_spec *spec = codec->spec;
7941
7942 chipio_8051_write_direct(codec, 0x93, 0x10);
7943 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7944
7945 writeb(0xff, spec->mem_base + 0x304);
7946 writeb(0xff, spec->mem_base + 0x304);
7947 writeb(0xff, spec->mem_base + 0x304);
7948 writeb(0xff, spec->mem_base + 0x304);
7949 writeb(0x00, spec->mem_base + 0x100);
7950 writeb(0xff, spec->mem_base + 0x304);
7951 writeb(0x00, spec->mem_base + 0x100);
7952 writeb(0xff, spec->mem_base + 0x304);
7953 writeb(0x00, spec->mem_base + 0x100);
7954 writeb(0xff, spec->mem_base + 0x304);
7955 writeb(0x00, spec->mem_base + 0x100);
7956 writeb(0xff, spec->mem_base + 0x304);
7957
7958 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7959 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7960 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7961 }
7962
ae5_post_dsp_param_setup(struct hda_codec * codec)7963 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7964 {
7965 /*
7966 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7967 * which seems to be 'multichannel'. This is also mentioned in the
7968 * AE-5's registry values in Windows.
7969 */
7970 chipio_set_control_param(codec, 3, 0);
7971 /*
7972 * I believe ASI is 'audio serial interface' and that it's used to
7973 * change colors on the external LED strip connected to the AE-5.
7974 */
7975 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7976
7977 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7978 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7979
7980 chipio_8051_write_exram(codec, 0xfa92, 0x22);
7981 }
7982
ae5_post_dsp_pll_setup(struct hda_codec * codec)7983 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7984 {
7985 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7986 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7987 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7988 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7989 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7990 }
7991
ae5_post_dsp_stream_setup(struct hda_codec * codec)7992 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7993 {
7994 struct ca0132_spec *spec = codec->spec;
7995
7996 mutex_lock(&spec->chipio_mutex);
7997
7998 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7999
8000 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8001
8002 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
8003
8004 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
8005 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8006 chipio_set_stream_channels(codec, 0x18, 6);
8007 chipio_set_stream_control(codec, 0x18, 1);
8008
8009 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8010
8011 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8012
8013 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
8014
8015 mutex_unlock(&spec->chipio_mutex);
8016 }
8017
ae5_post_dsp_startup_data(struct hda_codec * codec)8018 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
8019 {
8020 struct ca0132_spec *spec = codec->spec;
8021
8022 mutex_lock(&spec->chipio_mutex);
8023
8024 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8025 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8026 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8027 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8028
8029 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8030 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8031 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
8032 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
8033 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
8034 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8035 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8036 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8037 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8038 ca0113_mmio_gpio_set(codec, 0, true);
8039 ca0113_mmio_gpio_set(codec, 1, true);
8040 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
8041
8042 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
8043
8044 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8045 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8046
8047 mutex_unlock(&spec->chipio_mutex);
8048 }
8049
ae7_post_dsp_setup_ports(struct hda_codec * codec)8050 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
8051 {
8052 struct ca0132_spec *spec = codec->spec;
8053
8054 mutex_lock(&spec->chipio_mutex);
8055
8056 /* Seems to share the same port remapping as the SBZ. */
8057 chipio_remap_stream(codec, &stream_remap_data[1]);
8058
8059 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8060 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
8061 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
8062 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
8063 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
8064 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
8065 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
8066 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8067
8068 mutex_unlock(&spec->chipio_mutex);
8069 }
8070
ae7_post_dsp_asi_stream_setup(struct hda_codec * codec)8071 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8072 {
8073 struct ca0132_spec *spec = codec->spec;
8074
8075 mutex_lock(&spec->chipio_mutex);
8076
8077 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8078 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8079
8080 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8081
8082 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8083 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8084
8085 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8086 chipio_set_stream_channels(codec, 0x18, 6);
8087 chipio_set_stream_control(codec, 0x18, 1);
8088
8089 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8090
8091 mutex_unlock(&spec->chipio_mutex);
8092 }
8093
ae7_post_dsp_pll_setup(struct hda_codec * codec)8094 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8095 {
8096 static const unsigned int addr[] = {
8097 0x41, 0x45, 0x40, 0x43, 0x51
8098 };
8099 static const unsigned int data[] = {
8100 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8101 };
8102 unsigned int i;
8103
8104 for (i = 0; i < ARRAY_SIZE(addr); i++)
8105 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8106 }
8107
ae7_post_dsp_asi_setup_ports(struct hda_codec * codec)8108 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8109 {
8110 struct ca0132_spec *spec = codec->spec;
8111 static const unsigned int target[] = {
8112 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8113 };
8114 static const unsigned int data[] = {
8115 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8116 };
8117 unsigned int i;
8118
8119 mutex_lock(&spec->chipio_mutex);
8120
8121 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8122
8123 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8124 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8125 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8126 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8127
8128 ae7_post_dsp_pll_setup(codec);
8129 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8130
8131 for (i = 0; i < ARRAY_SIZE(target); i++)
8132 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8133
8134 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8135 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8136 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8137
8138 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8139 chipio_set_stream_channels(codec, 0x21, 2);
8140 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8141
8142 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8143 /*
8144 * In the 8051's memory, this param is referred to as 'n2sid', which I
8145 * believe is 'node to streamID'. It seems to be a way to assign a
8146 * stream to a given HDA node.
8147 */
8148 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8149
8150 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8151
8152 /*
8153 * Now, at this point on Windows, an actual stream is setup and
8154 * seemingly sends data to the HDA node 0x09, which is the digital
8155 * audio input node. This is left out here, because obviously I don't
8156 * know what data is being sent. Interestingly, the AE-5 seems to go
8157 * through the motions of getting here and never actually takes this
8158 * step, but the AE-7 does.
8159 */
8160
8161 ca0113_mmio_gpio_set(codec, 0, 1);
8162 ca0113_mmio_gpio_set(codec, 1, 1);
8163
8164 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8165 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8166 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8167 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8168
8169 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8170 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8171
8172 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8173 chipio_set_stream_channels(codec, 0x18, 6);
8174
8175 /*
8176 * Runs again, this has been repeated a few times, but I'm just
8177 * following what the Windows driver does.
8178 */
8179 ae7_post_dsp_pll_setup(codec);
8180 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8181
8182 mutex_unlock(&spec->chipio_mutex);
8183 }
8184
8185 /*
8186 * The Windows driver has commands that seem to setup ASI, which I believe to
8187 * be some sort of audio serial interface. My current speculation is that it's
8188 * related to communicating with the new DAC.
8189 */
ae7_post_dsp_asi_setup(struct hda_codec * codec)8190 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8191 {
8192 chipio_8051_write_direct(codec, 0x93, 0x10);
8193
8194 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8195
8196 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8197 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8198
8199 chipio_set_control_param(codec, 3, 3);
8200 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8201
8202 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8203 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8204 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8205
8206 chipio_8051_write_exram(codec, 0xfa92, 0x22);
8207
8208 ae7_post_dsp_pll_setup(codec);
8209 ae7_post_dsp_asi_stream_setup(codec);
8210
8211 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8212
8213 ae7_post_dsp_asi_setup_ports(codec);
8214 }
8215
8216 /*
8217 * Setup default parameters for DSP
8218 */
ca0132_setup_defaults(struct hda_codec * codec)8219 static void ca0132_setup_defaults(struct hda_codec *codec)
8220 {
8221 struct ca0132_spec *spec = codec->spec;
8222 unsigned int tmp;
8223 int num_fx;
8224 int idx, i;
8225
8226 if (spec->dsp_state != DSP_DOWNLOADED)
8227 return;
8228
8229 /* out, in effects + voicefx */
8230 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8231 for (idx = 0; idx < num_fx; idx++) {
8232 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8233 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8234 ca0132_effects[idx].reqs[i],
8235 ca0132_effects[idx].def_vals[i]);
8236 }
8237 }
8238
8239 /*remove DSP headroom*/
8240 tmp = FLOAT_ZERO;
8241 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8242
8243 /*set speaker EQ bypass attenuation*/
8244 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8245
8246 /* set AMic1 and AMic2 as mono mic */
8247 tmp = FLOAT_ONE;
8248 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8249 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8250
8251 /* set AMic1 as CrystalVoice input */
8252 tmp = FLOAT_ONE;
8253 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8254
8255 /* set WUH source */
8256 tmp = FLOAT_TWO;
8257 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8258 }
8259
8260 /*
8261 * Setup default parameters for Recon3D/Recon3Di DSP.
8262 */
8263
r3d_setup_defaults(struct hda_codec * codec)8264 static void r3d_setup_defaults(struct hda_codec *codec)
8265 {
8266 struct ca0132_spec *spec = codec->spec;
8267 unsigned int tmp;
8268 int num_fx;
8269 int idx, i;
8270
8271 if (spec->dsp_state != DSP_DOWNLOADED)
8272 return;
8273
8274 ca0132_alt_init_analog_mics(codec);
8275 ca0132_alt_start_dsp_audio_streams(codec);
8276
8277 /*remove DSP headroom*/
8278 tmp = FLOAT_ZERO;
8279 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8280
8281 /* set WUH source */
8282 tmp = FLOAT_TWO;
8283 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8284 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8285
8286 /* Set speaker source? */
8287 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8288
8289 if (ca0132_quirk(spec) == QUIRK_R3DI)
8290 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8291
8292 /* Disable mute on Center/LFE. */
8293 if (ca0132_quirk(spec) == QUIRK_R3D) {
8294 ca0113_mmio_gpio_set(codec, 2, false);
8295 ca0113_mmio_gpio_set(codec, 4, true);
8296 }
8297
8298 /* Setup effect defaults */
8299 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8300 for (idx = 0; idx < num_fx; idx++) {
8301 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8302 dspio_set_uint_param(codec,
8303 ca0132_effects[idx].mid,
8304 ca0132_effects[idx].reqs[i],
8305 ca0132_effects[idx].def_vals[i]);
8306 }
8307 }
8308 }
8309
8310 /*
8311 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8312 * than the Chromebook setup.
8313 */
sbz_setup_defaults(struct hda_codec * codec)8314 static void sbz_setup_defaults(struct hda_codec *codec)
8315 {
8316 struct ca0132_spec *spec = codec->spec;
8317 unsigned int tmp;
8318 int num_fx;
8319 int idx, i;
8320
8321 if (spec->dsp_state != DSP_DOWNLOADED)
8322 return;
8323
8324 ca0132_alt_init_analog_mics(codec);
8325 ca0132_alt_start_dsp_audio_streams(codec);
8326 sbz_connect_streams(codec);
8327 sbz_chipio_startup_data(codec);
8328
8329 /*
8330 * Sets internal input loopback to off, used to have a switch to
8331 * enable input loopback, but turned out to be way too buggy.
8332 */
8333 tmp = FLOAT_ONE;
8334 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8335 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8336
8337 /*remove DSP headroom*/
8338 tmp = FLOAT_ZERO;
8339 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8340
8341 /* set WUH source */
8342 tmp = FLOAT_TWO;
8343 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8344 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8345
8346 /* Set speaker source? */
8347 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8348
8349 ca0132_alt_dsp_initial_mic_setup(codec);
8350
8351 /* out, in effects + voicefx */
8352 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8353 for (idx = 0; idx < num_fx; idx++) {
8354 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8355 dspio_set_uint_param(codec,
8356 ca0132_effects[idx].mid,
8357 ca0132_effects[idx].reqs[i],
8358 ca0132_effects[idx].def_vals[i]);
8359 }
8360 }
8361
8362 ca0132_alt_init_speaker_tuning(codec);
8363 }
8364
8365 /*
8366 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8367 */
ae5_setup_defaults(struct hda_codec * codec)8368 static void ae5_setup_defaults(struct hda_codec *codec)
8369 {
8370 struct ca0132_spec *spec = codec->spec;
8371 unsigned int tmp;
8372 int num_fx;
8373 int idx, i;
8374
8375 if (spec->dsp_state != DSP_DOWNLOADED)
8376 return;
8377
8378 ca0132_alt_init_analog_mics(codec);
8379 ca0132_alt_start_dsp_audio_streams(codec);
8380
8381 /* New, unknown SCP req's */
8382 tmp = FLOAT_ZERO;
8383 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8384 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8385 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8386 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8387
8388 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8389 ca0113_mmio_gpio_set(codec, 0, false);
8390 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8391
8392 /* Internal loopback off */
8393 tmp = FLOAT_ONE;
8394 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8395 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8396
8397 /*remove DSP headroom*/
8398 tmp = FLOAT_ZERO;
8399 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8400
8401 /* set WUH source */
8402 tmp = FLOAT_TWO;
8403 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8404 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8405
8406 /* Set speaker source? */
8407 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8408
8409 ca0132_alt_dsp_initial_mic_setup(codec);
8410 ae5_post_dsp_register_set(codec);
8411 ae5_post_dsp_param_setup(codec);
8412 ae5_post_dsp_pll_setup(codec);
8413 ae5_post_dsp_stream_setup(codec);
8414 ae5_post_dsp_startup_data(codec);
8415
8416 /* out, in effects + voicefx */
8417 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8418 for (idx = 0; idx < num_fx; idx++) {
8419 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8420 dspio_set_uint_param(codec,
8421 ca0132_effects[idx].mid,
8422 ca0132_effects[idx].reqs[i],
8423 ca0132_effects[idx].def_vals[i]);
8424 }
8425 }
8426
8427 ca0132_alt_init_speaker_tuning(codec);
8428 }
8429
8430 /*
8431 * Setup default parameters for the Sound Blaster AE-7 DSP.
8432 */
ae7_setup_defaults(struct hda_codec * codec)8433 static void ae7_setup_defaults(struct hda_codec *codec)
8434 {
8435 struct ca0132_spec *spec = codec->spec;
8436 unsigned int tmp;
8437 int num_fx;
8438 int idx, i;
8439
8440 if (spec->dsp_state != DSP_DOWNLOADED)
8441 return;
8442
8443 ca0132_alt_init_analog_mics(codec);
8444 ca0132_alt_start_dsp_audio_streams(codec);
8445 ae7_post_dsp_setup_ports(codec);
8446
8447 tmp = FLOAT_ZERO;
8448 dspio_set_uint_param(codec, 0x96,
8449 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8450 dspio_set_uint_param(codec, 0x96,
8451 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8452
8453 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8454
8455 /* New, unknown SCP req's */
8456 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8457 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8458
8459 ca0113_mmio_gpio_set(codec, 0, false);
8460
8461 /* Internal loopback off */
8462 tmp = FLOAT_ONE;
8463 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8464 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8465
8466 /*remove DSP headroom*/
8467 tmp = FLOAT_ZERO;
8468 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8469
8470 /* set WUH source */
8471 tmp = FLOAT_TWO;
8472 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8473 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8474
8475 /* Set speaker source? */
8476 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8477 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8478
8479 /*
8480 * This is the second time we've called this, but this is seemingly
8481 * what Windows does.
8482 */
8483 ca0132_alt_init_analog_mics(codec);
8484
8485 ae7_post_dsp_asi_setup(codec);
8486
8487 /*
8488 * Not sure why, but these are both set to 1. They're only set to 0
8489 * upon shutdown.
8490 */
8491 ca0113_mmio_gpio_set(codec, 0, true);
8492 ca0113_mmio_gpio_set(codec, 1, true);
8493
8494 /* Volume control related. */
8495 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8496 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8497 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8498
8499 /* out, in effects + voicefx */
8500 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8501 for (idx = 0; idx < num_fx; idx++) {
8502 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8503 dspio_set_uint_param(codec,
8504 ca0132_effects[idx].mid,
8505 ca0132_effects[idx].reqs[i],
8506 ca0132_effects[idx].def_vals[i]);
8507 }
8508 }
8509
8510 ca0132_alt_init_speaker_tuning(codec);
8511 }
8512
8513 /*
8514 * Initialization of flags in chip
8515 */
ca0132_init_flags(struct hda_codec * codec)8516 static void ca0132_init_flags(struct hda_codec *codec)
8517 {
8518 struct ca0132_spec *spec = codec->spec;
8519
8520 if (ca0132_use_alt_functions(spec)) {
8521 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8522 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8523 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8524 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8525 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8526 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8527 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8528 chipio_set_control_flag(codec,
8529 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8530 chipio_set_control_flag(codec,
8531 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8532 } else {
8533 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8534 chipio_set_control_flag(codec,
8535 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8536 chipio_set_control_flag(codec,
8537 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8538 chipio_set_control_flag(codec,
8539 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8540 chipio_set_control_flag(codec,
8541 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8542 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8543 }
8544 }
8545
8546 /*
8547 * Initialization of parameters in chip
8548 */
ca0132_init_params(struct hda_codec * codec)8549 static void ca0132_init_params(struct hda_codec *codec)
8550 {
8551 struct ca0132_spec *spec = codec->spec;
8552
8553 if (ca0132_use_alt_functions(spec)) {
8554 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8555 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8556 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8557 chipio_set_control_param(codec, 0, 0);
8558 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8559 }
8560
8561 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8562 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8563 }
8564
ca0132_set_dsp_msr(struct hda_codec * codec,bool is96k)8565 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8566 {
8567 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8568 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8569 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8570 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8571 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8572 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8573
8574 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8575 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8576 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8577 }
8578
ca0132_download_dsp_images(struct hda_codec * codec)8579 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8580 {
8581 bool dsp_loaded = false;
8582 struct ca0132_spec *spec = codec->spec;
8583 const struct dsp_image_seg *dsp_os_image;
8584 const struct firmware *fw_entry = NULL;
8585 /*
8586 * Alternate firmwares for different variants. The Recon3Di apparently
8587 * can use the default firmware, but I'll leave the option in case
8588 * it needs it again.
8589 */
8590 switch (ca0132_quirk(spec)) {
8591 case QUIRK_SBZ:
8592 case QUIRK_R3D:
8593 case QUIRK_AE5:
8594 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8595 codec->card->dev) != 0)
8596 codec_dbg(codec, "Desktop firmware not found.");
8597 else
8598 codec_dbg(codec, "Desktop firmware selected.");
8599 break;
8600 case QUIRK_R3DI:
8601 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
8602 codec->card->dev) != 0)
8603 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8604 else
8605 codec_dbg(codec, "Recon3Di firmware selected.");
8606 break;
8607 default:
8608 break;
8609 }
8610 /*
8611 * Use default ctefx.bin if no alt firmware is detected, or if none
8612 * exists for your particular codec.
8613 */
8614 if (!fw_entry) {
8615 codec_dbg(codec, "Default firmware selected.");
8616 if (request_firmware(&fw_entry, EFX_FILE,
8617 codec->card->dev) != 0)
8618 return false;
8619 }
8620
8621 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8622 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8623 codec_err(codec, "ca0132 DSP load image failed\n");
8624 goto exit_download;
8625 }
8626
8627 dsp_loaded = dspload_wait_loaded(codec);
8628
8629 exit_download:
8630 release_firmware(fw_entry);
8631
8632 return dsp_loaded;
8633 }
8634
ca0132_download_dsp(struct hda_codec * codec)8635 static void ca0132_download_dsp(struct hda_codec *codec)
8636 {
8637 struct ca0132_spec *spec = codec->spec;
8638
8639 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8640 return; /* NOP */
8641 #endif
8642
8643 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8644 return; /* don't retry failures */
8645
8646 chipio_enable_clocks(codec);
8647 if (spec->dsp_state != DSP_DOWNLOADED) {
8648 spec->dsp_state = DSP_DOWNLOADING;
8649
8650 if (!ca0132_download_dsp_images(codec))
8651 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8652 else
8653 spec->dsp_state = DSP_DOWNLOADED;
8654 }
8655
8656 /* For codecs using alt functions, this is already done earlier */
8657 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8658 ca0132_set_dsp_msr(codec, true);
8659 }
8660
ca0132_process_dsp_response(struct hda_codec * codec,struct hda_jack_callback * callback)8661 static void ca0132_process_dsp_response(struct hda_codec *codec,
8662 struct hda_jack_callback *callback)
8663 {
8664 struct ca0132_spec *spec = codec->spec;
8665
8666 codec_dbg(codec, "ca0132_process_dsp_response\n");
8667 snd_hda_power_up_pm(codec);
8668 if (spec->wait_scp) {
8669 if (dspio_get_response_data(codec) >= 0)
8670 spec->wait_scp = 0;
8671 }
8672
8673 dspio_clear_response_queue(codec);
8674 snd_hda_power_down_pm(codec);
8675 }
8676
hp_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8677 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8678 {
8679 struct ca0132_spec *spec = codec->spec;
8680 struct hda_jack_tbl *tbl;
8681
8682 /* Delay enabling the HP amp, to let the mic-detection
8683 * state machine run.
8684 */
8685 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8686 if (tbl)
8687 tbl->block_report = 1;
8688 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8689 }
8690
amic_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8691 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8692 {
8693 struct ca0132_spec *spec = codec->spec;
8694
8695 if (ca0132_use_alt_functions(spec))
8696 ca0132_alt_select_in(codec);
8697 else
8698 ca0132_select_mic(codec);
8699 }
8700
ca0132_setup_unsol(struct hda_codec * codec)8701 static void ca0132_setup_unsol(struct hda_codec *codec)
8702 {
8703 struct ca0132_spec *spec = codec->spec;
8704 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8705 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8706 amic_callback);
8707 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8708 ca0132_process_dsp_response);
8709 /* Front headphone jack detection */
8710 if (ca0132_use_alt_functions(spec))
8711 snd_hda_jack_detect_enable_callback(codec,
8712 spec->unsol_tag_front_hp, hp_callback);
8713 }
8714
8715 /*
8716 * Verbs tables.
8717 */
8718
8719 /* Sends before DSP download. */
8720 static const struct hda_verb ca0132_base_init_verbs[] = {
8721 /*enable ct extension*/
8722 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8723 {}
8724 };
8725
8726 /* Send at exit. */
8727 static const struct hda_verb ca0132_base_exit_verbs[] = {
8728 /*set afg to D3*/
8729 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8730 /*disable ct extension*/
8731 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8732 {}
8733 };
8734
8735 /* Other verbs tables. Sends after DSP download. */
8736
8737 static const struct hda_verb ca0132_init_verbs0[] = {
8738 /* chip init verbs */
8739 {0x15, 0x70D, 0xF0},
8740 {0x15, 0x70E, 0xFE},
8741 {0x15, 0x707, 0x75},
8742 {0x15, 0x707, 0xD3},
8743 {0x15, 0x707, 0x09},
8744 {0x15, 0x707, 0x53},
8745 {0x15, 0x707, 0xD4},
8746 {0x15, 0x707, 0xEF},
8747 {0x15, 0x707, 0x75},
8748 {0x15, 0x707, 0xD3},
8749 {0x15, 0x707, 0x09},
8750 {0x15, 0x707, 0x02},
8751 {0x15, 0x707, 0x37},
8752 {0x15, 0x707, 0x78},
8753 {0x15, 0x53C, 0xCE},
8754 {0x15, 0x575, 0xC9},
8755 {0x15, 0x53D, 0xCE},
8756 {0x15, 0x5B7, 0xC9},
8757 {0x15, 0x70D, 0xE8},
8758 {0x15, 0x70E, 0xFE},
8759 {0x15, 0x707, 0x02},
8760 {0x15, 0x707, 0x68},
8761 {0x15, 0x707, 0x62},
8762 {0x15, 0x53A, 0xCE},
8763 {0x15, 0x546, 0xC9},
8764 {0x15, 0x53B, 0xCE},
8765 {0x15, 0x5E8, 0xC9},
8766 {}
8767 };
8768
8769 /* Extra init verbs for desktop cards. */
8770 static const struct hda_verb ca0132_init_verbs1[] = {
8771 {0x15, 0x70D, 0x20},
8772 {0x15, 0x70E, 0x19},
8773 {0x15, 0x707, 0x00},
8774 {0x15, 0x539, 0xCE},
8775 {0x15, 0x546, 0xC9},
8776 {0x15, 0x70D, 0xB7},
8777 {0x15, 0x70E, 0x09},
8778 {0x15, 0x707, 0x10},
8779 {0x15, 0x70D, 0xAF},
8780 {0x15, 0x70E, 0x09},
8781 {0x15, 0x707, 0x01},
8782 {0x15, 0x707, 0x05},
8783 {0x15, 0x70D, 0x73},
8784 {0x15, 0x70E, 0x09},
8785 {0x15, 0x707, 0x14},
8786 {0x15, 0x6FF, 0xC4},
8787 {}
8788 };
8789
ca0132_init_chip(struct hda_codec * codec)8790 static void ca0132_init_chip(struct hda_codec *codec)
8791 {
8792 struct ca0132_spec *spec = codec->spec;
8793 int num_fx;
8794 int i;
8795 unsigned int on;
8796
8797 mutex_init(&spec->chipio_mutex);
8798
8799 /*
8800 * The Windows driver always does this upon startup, which seems to
8801 * clear out any previous configuration. This should help issues where
8802 * a boot into Windows prior to a boot into Linux breaks things. Also,
8803 * Windows always sends the reset twice.
8804 */
8805 if (ca0132_use_alt_functions(spec)) {
8806 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8807 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8808
8809 snd_hda_codec_write(codec, codec->core.afg, 0,
8810 AC_VERB_SET_CODEC_RESET, 0);
8811 snd_hda_codec_write(codec, codec->core.afg, 0,
8812 AC_VERB_SET_CODEC_RESET, 0);
8813 }
8814
8815 spec->cur_out_type = SPEAKER_OUT;
8816 if (!ca0132_use_alt_functions(spec))
8817 spec->cur_mic_type = DIGITAL_MIC;
8818 else
8819 spec->cur_mic_type = REAR_MIC;
8820
8821 spec->cur_mic_boost = 0;
8822
8823 for (i = 0; i < VNODES_COUNT; i++) {
8824 spec->vnode_lvol[i] = 0x5a;
8825 spec->vnode_rvol[i] = 0x5a;
8826 spec->vnode_lswitch[i] = 0;
8827 spec->vnode_rswitch[i] = 0;
8828 }
8829
8830 /*
8831 * Default states for effects are in ca0132_effects[].
8832 */
8833 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8834 for (i = 0; i < num_fx; i++) {
8835 on = (unsigned int)ca0132_effects[i].reqs[0];
8836 spec->effects_switch[i] = on ? 1 : 0;
8837 }
8838 /*
8839 * Sets defaults for the effect slider controls, only for alternative
8840 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8841 */
8842 if (ca0132_use_alt_controls(spec)) {
8843 /* Set speakers to default to full range. */
8844 spec->speaker_range_val[0] = 1;
8845 spec->speaker_range_val[1] = 1;
8846
8847 spec->xbass_xover_freq = 8;
8848 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8849 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8850
8851 spec->bass_redirect_xover_freq = 8;
8852 }
8853
8854 spec->voicefx_val = 0;
8855 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8856 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8857
8858 /*
8859 * The ZxR doesn't have a front panel header, and it's line-in is on
8860 * the daughter board. So, there is no input enum control, and we need
8861 * to make sure that spec->in_enum_val is set properly.
8862 */
8863 if (ca0132_quirk(spec) == QUIRK_ZXR)
8864 spec->in_enum_val = REAR_MIC;
8865
8866 #ifdef ENABLE_TUNING_CONTROLS
8867 ca0132_init_tuning_defaults(codec);
8868 #endif
8869 }
8870
8871 /*
8872 * Recon3Di exit specific commands.
8873 */
8874 /* prevents popping noise on shutdown */
r3di_gpio_shutdown(struct hda_codec * codec)8875 static void r3di_gpio_shutdown(struct hda_codec *codec)
8876 {
8877 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8878 }
8879
8880 /*
8881 * Sound Blaster Z exit specific commands.
8882 */
sbz_region2_exit(struct hda_codec * codec)8883 static void sbz_region2_exit(struct hda_codec *codec)
8884 {
8885 struct ca0132_spec *spec = codec->spec;
8886 unsigned int i;
8887
8888 for (i = 0; i < 4; i++)
8889 writeb(0x0, spec->mem_base + 0x100);
8890 for (i = 0; i < 8; i++)
8891 writeb(0xb3, spec->mem_base + 0x304);
8892
8893 ca0113_mmio_gpio_set(codec, 0, false);
8894 ca0113_mmio_gpio_set(codec, 1, false);
8895 ca0113_mmio_gpio_set(codec, 4, true);
8896 ca0113_mmio_gpio_set(codec, 5, false);
8897 ca0113_mmio_gpio_set(codec, 7, false);
8898 }
8899
sbz_set_pin_ctl_default(struct hda_codec * codec)8900 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8901 {
8902 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8903 unsigned int i;
8904
8905 snd_hda_codec_write(codec, 0x11, 0,
8906 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8907
8908 for (i = 0; i < ARRAY_SIZE(pins); i++)
8909 snd_hda_codec_write(codec, pins[i], 0,
8910 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8911 }
8912
ca0132_clear_unsolicited(struct hda_codec * codec)8913 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8914 {
8915 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8916 unsigned int i;
8917
8918 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8919 snd_hda_codec_write(codec, pins[i], 0,
8920 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8921 }
8922 }
8923
8924 /* On shutdown, sends commands in sets of three */
sbz_gpio_shutdown_commands(struct hda_codec * codec,int dir,int mask,int data)8925 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8926 int mask, int data)
8927 {
8928 if (dir >= 0)
8929 snd_hda_codec_write(codec, 0x01, 0,
8930 AC_VERB_SET_GPIO_DIRECTION, dir);
8931 if (mask >= 0)
8932 snd_hda_codec_write(codec, 0x01, 0,
8933 AC_VERB_SET_GPIO_MASK, mask);
8934
8935 if (data >= 0)
8936 snd_hda_codec_write(codec, 0x01, 0,
8937 AC_VERB_SET_GPIO_DATA, data);
8938 }
8939
zxr_dbpro_power_state_shutdown(struct hda_codec * codec)8940 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8941 {
8942 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8943 unsigned int i;
8944
8945 for (i = 0; i < ARRAY_SIZE(pins); i++)
8946 snd_hda_codec_write(codec, pins[i], 0,
8947 AC_VERB_SET_POWER_STATE, 0x03);
8948 }
8949
sbz_exit_chip(struct hda_codec * codec)8950 static void sbz_exit_chip(struct hda_codec *codec)
8951 {
8952 chipio_set_stream_control(codec, 0x03, 0);
8953 chipio_set_stream_control(codec, 0x04, 0);
8954
8955 /* Mess with GPIO */
8956 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8957 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8958 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8959
8960 chipio_set_stream_control(codec, 0x14, 0);
8961 chipio_set_stream_control(codec, 0x0C, 0);
8962
8963 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8964 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8965
8966 chipio_write(codec, 0x18a020, 0x00000083);
8967
8968 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8969 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8970 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8971
8972 chipio_set_stream_control(codec, 0x0C, 0);
8973
8974 chipio_set_control_param(codec, 0x0D, 0x24);
8975
8976 ca0132_clear_unsolicited(codec);
8977 sbz_set_pin_ctl_default(codec);
8978
8979 snd_hda_codec_write(codec, 0x0B, 0,
8980 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8981
8982 sbz_region2_exit(codec);
8983 }
8984
r3d_exit_chip(struct hda_codec * codec)8985 static void r3d_exit_chip(struct hda_codec *codec)
8986 {
8987 ca0132_clear_unsolicited(codec);
8988 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8989 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8990 }
8991
ae5_exit_chip(struct hda_codec * codec)8992 static void ae5_exit_chip(struct hda_codec *codec)
8993 {
8994 chipio_set_stream_control(codec, 0x03, 0);
8995 chipio_set_stream_control(codec, 0x04, 0);
8996
8997 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8998 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8999 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9000 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9001 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9002 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
9003 ca0113_mmio_gpio_set(codec, 0, false);
9004 ca0113_mmio_gpio_set(codec, 1, false);
9005
9006 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9007 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9008
9009 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9010
9011 chipio_set_stream_control(codec, 0x18, 0);
9012 chipio_set_stream_control(codec, 0x0c, 0);
9013
9014 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
9015 }
9016
ae7_exit_chip(struct hda_codec * codec)9017 static void ae7_exit_chip(struct hda_codec *codec)
9018 {
9019 chipio_set_stream_control(codec, 0x18, 0);
9020 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
9021 chipio_set_stream_channels(codec, 0x21, 0);
9022 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
9023 chipio_set_control_param(codec, 0x20, 0x01);
9024
9025 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9026
9027 chipio_set_stream_control(codec, 0x18, 0);
9028 chipio_set_stream_control(codec, 0x0c, 0);
9029
9030 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9031 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
9032 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9033 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9034 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
9035 ca0113_mmio_gpio_set(codec, 0, false);
9036 ca0113_mmio_gpio_set(codec, 1, false);
9037 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9038
9039 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9040 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9041 }
9042
zxr_exit_chip(struct hda_codec * codec)9043 static void zxr_exit_chip(struct hda_codec *codec)
9044 {
9045 chipio_set_stream_control(codec, 0x03, 0);
9046 chipio_set_stream_control(codec, 0x04, 0);
9047 chipio_set_stream_control(codec, 0x14, 0);
9048 chipio_set_stream_control(codec, 0x0C, 0);
9049
9050 chipio_set_conn_rate(codec, 0x41, SR_192_000);
9051 chipio_set_conn_rate(codec, 0x91, SR_192_000);
9052
9053 chipio_write(codec, 0x18a020, 0x00000083);
9054
9055 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9056 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9057
9058 ca0132_clear_unsolicited(codec);
9059 sbz_set_pin_ctl_default(codec);
9060 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
9061
9062 ca0113_mmio_gpio_set(codec, 5, false);
9063 ca0113_mmio_gpio_set(codec, 2, false);
9064 ca0113_mmio_gpio_set(codec, 3, false);
9065 ca0113_mmio_gpio_set(codec, 0, false);
9066 ca0113_mmio_gpio_set(codec, 4, true);
9067 ca0113_mmio_gpio_set(codec, 0, true);
9068 ca0113_mmio_gpio_set(codec, 5, true);
9069 ca0113_mmio_gpio_set(codec, 2, false);
9070 ca0113_mmio_gpio_set(codec, 3, false);
9071 }
9072
ca0132_exit_chip(struct hda_codec * codec)9073 static void ca0132_exit_chip(struct hda_codec *codec)
9074 {
9075 /* put any chip cleanup stuffs here. */
9076
9077 if (dspload_is_loaded(codec))
9078 dsp_reset(codec);
9079 }
9080
9081 /*
9082 * This fixes a problem that was hard to reproduce. Very rarely, I would
9083 * boot up, and there would be no sound, but the DSP indicated it had loaded
9084 * properly. I did a few memory dumps to see if anything was different, and
9085 * there were a few areas of memory uninitialized with a1a2a3a4. This function
9086 * checks if those areas are uninitialized, and if they are, it'll attempt to
9087 * reload the card 3 times. Usually it fixes by the second.
9088 */
sbz_dsp_startup_check(struct hda_codec * codec)9089 static void sbz_dsp_startup_check(struct hda_codec *codec)
9090 {
9091 struct ca0132_spec *spec = codec->spec;
9092 unsigned int dsp_data_check[4];
9093 unsigned int cur_address = 0x390;
9094 unsigned int i;
9095 unsigned int failure = 0;
9096 unsigned int reload = 3;
9097
9098 if (spec->startup_check_entered)
9099 return;
9100
9101 spec->startup_check_entered = true;
9102
9103 for (i = 0; i < 4; i++) {
9104 chipio_read(codec, cur_address, &dsp_data_check[i]);
9105 cur_address += 0x4;
9106 }
9107 for (i = 0; i < 4; i++) {
9108 if (dsp_data_check[i] == 0xa1a2a3a4)
9109 failure = 1;
9110 }
9111
9112 codec_dbg(codec, "Startup Check: %d ", failure);
9113 if (failure)
9114 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9115 /*
9116 * While the failure condition is true, and we haven't reached our
9117 * three reload limit, continue trying to reload the driver and
9118 * fix the issue.
9119 */
9120 while (failure && (reload != 0)) {
9121 codec_info(codec, "Reloading... Tries left: %d", reload);
9122 sbz_exit_chip(codec);
9123 spec->dsp_state = DSP_DOWNLOAD_INIT;
9124 snd_hda_codec_init(codec);
9125 failure = 0;
9126 for (i = 0; i < 4; i++) {
9127 chipio_read(codec, cur_address, &dsp_data_check[i]);
9128 cur_address += 0x4;
9129 }
9130 for (i = 0; i < 4; i++) {
9131 if (dsp_data_check[i] == 0xa1a2a3a4)
9132 failure = 1;
9133 }
9134 reload--;
9135 }
9136
9137 if (!failure && reload < 3)
9138 codec_info(codec, "DSP fixed.");
9139
9140 if (!failure)
9141 return;
9142
9143 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9144 }
9145
9146 /*
9147 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9148 * extra precision for decibel values. If you had the dB value in floating point
9149 * you would take the value after the decimal point, multiply by 64, and divide
9150 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
9151 * implement fixed point or floating point dB volumes. For now, I'll set them
9152 * to 0 just incase a value has lingered from a boot into Windows.
9153 */
ca0132_alt_vol_setup(struct hda_codec * codec)9154 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9155 {
9156 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9157 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9158 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9159 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9160 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9161 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9162 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9163 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9164 }
9165
9166 /*
9167 * Extra commands that don't really fit anywhere else.
9168 */
sbz_pre_dsp_setup(struct hda_codec * codec)9169 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9170 {
9171 struct ca0132_spec *spec = codec->spec;
9172
9173 writel(0x00820680, spec->mem_base + 0x01C);
9174 writel(0x00820680, spec->mem_base + 0x01C);
9175
9176 chipio_write(codec, 0x18b0a4, 0x000000c2);
9177
9178 snd_hda_codec_write(codec, 0x11, 0,
9179 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9180 }
9181
r3d_pre_dsp_setup(struct hda_codec * codec)9182 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9183 {
9184 chipio_write(codec, 0x18b0a4, 0x000000c2);
9185
9186 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9187
9188 snd_hda_codec_write(codec, 0x11, 0,
9189 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9190 }
9191
r3di_pre_dsp_setup(struct hda_codec * codec)9192 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9193 {
9194 chipio_write(codec, 0x18b0a4, 0x000000c2);
9195
9196 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9197 chipio_8051_write_exram(codec, 0x1920, 0x00);
9198 chipio_8051_write_exram(codec, 0x1921, 0x40);
9199
9200 snd_hda_codec_write(codec, 0x11, 0,
9201 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9202 }
9203
9204 /*
9205 * The ZxR seems to use alternative DAC's for the surround channels, which
9206 * require PLL PMU setup for the clock rate, I'm guessing. Without setting
9207 * this up, we get no audio out of the surround jacks.
9208 */
zxr_pre_dsp_setup(struct hda_codec * codec)9209 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9210 {
9211 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9212 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9213 unsigned int i;
9214
9215 chipio_write(codec, 0x189000, 0x0001f100);
9216 msleep(50);
9217 chipio_write(codec, 0x18900c, 0x0001f100);
9218 msleep(50);
9219
9220 /*
9221 * This writes a RET instruction at the entry point of the function at
9222 * 0xfa92 in exram. This function seems to have something to do with
9223 * ASI. Might be some way to prevent the card from reconfiguring the
9224 * ASI stuff itself.
9225 */
9226 chipio_8051_write_exram(codec, 0xfa92, 0x22);
9227
9228 chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9229
9230 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9231 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9232
9233 chipio_write(codec, 0x18902c, 0x00000000);
9234 msleep(50);
9235 chipio_write(codec, 0x18902c, 0x00000003);
9236 msleep(50);
9237
9238 for (i = 0; i < ARRAY_SIZE(addr); i++)
9239 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9240 }
9241
9242 /*
9243 * These are sent before the DSP is downloaded. Not sure
9244 * what they do, or if they're necessary. Could possibly
9245 * be removed. Figure they're better to leave in.
9246 */
9247 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9248 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9249 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9250 };
9251
9252 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9253 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9254 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9255 0x000000c1, 0x00000080
9256 };
9257
9258 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9259 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9260 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9261 0x000000c1, 0x00000080
9262 };
9263
9264 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9265 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9266 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9267 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9268 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9269 };
9270
9271 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9272 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9273 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9274 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9275 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9276 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9277 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9278 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9279 0x00000080, 0x00880680
9280 };
9281
ca0132_mmio_init_sbz(struct hda_codec * codec)9282 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9283 {
9284 struct ca0132_spec *spec = codec->spec;
9285 unsigned int tmp[2], i, count, cur_addr;
9286 const unsigned int *addr, *data;
9287
9288 addr = ca0113_mmio_init_address_sbz;
9289 for (i = 0; i < 3; i++)
9290 writel(0x00000000, spec->mem_base + addr[i]);
9291
9292 cur_addr = i;
9293 switch (ca0132_quirk(spec)) {
9294 case QUIRK_ZXR:
9295 tmp[0] = 0x00880480;
9296 tmp[1] = 0x00000080;
9297 break;
9298 case QUIRK_SBZ:
9299 tmp[0] = 0x00820680;
9300 tmp[1] = 0x00000083;
9301 break;
9302 case QUIRK_R3D:
9303 tmp[0] = 0x00880680;
9304 tmp[1] = 0x00000083;
9305 break;
9306 default:
9307 tmp[0] = 0x00000000;
9308 tmp[1] = 0x00000000;
9309 break;
9310 }
9311
9312 for (i = 0; i < 2; i++)
9313 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9314
9315 cur_addr += i;
9316
9317 switch (ca0132_quirk(spec)) {
9318 case QUIRK_ZXR:
9319 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9320 data = ca0113_mmio_init_data_zxr;
9321 break;
9322 default:
9323 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9324 data = ca0113_mmio_init_data_sbz;
9325 break;
9326 }
9327
9328 for (i = 0; i < count; i++)
9329 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9330 }
9331
ca0132_mmio_init_ae5(struct hda_codec * codec)9332 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9333 {
9334 struct ca0132_spec *spec = codec->spec;
9335 const unsigned int *addr, *data;
9336 unsigned int i, count;
9337
9338 addr = ca0113_mmio_init_address_ae5;
9339 data = ca0113_mmio_init_data_ae5;
9340 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9341
9342 if (ca0132_quirk(spec) == QUIRK_AE7) {
9343 writel(0x00000680, spec->mem_base + 0x1c);
9344 writel(0x00880680, spec->mem_base + 0x1c);
9345 }
9346
9347 for (i = 0; i < count; i++) {
9348 /*
9349 * AE-7 shares all writes with the AE-5, except that it writes
9350 * a different value to 0x20c.
9351 */
9352 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9353 writel(0x00800001, spec->mem_base + addr[i]);
9354 continue;
9355 }
9356
9357 writel(data[i], spec->mem_base + addr[i]);
9358 }
9359
9360 if (ca0132_quirk(spec) == QUIRK_AE5)
9361 writel(0x00880680, spec->mem_base + 0x1c);
9362 }
9363
ca0132_mmio_init(struct hda_codec * codec)9364 static void ca0132_mmio_init(struct hda_codec *codec)
9365 {
9366 struct ca0132_spec *spec = codec->spec;
9367
9368 switch (ca0132_quirk(spec)) {
9369 case QUIRK_R3D:
9370 case QUIRK_SBZ:
9371 case QUIRK_ZXR:
9372 ca0132_mmio_init_sbz(codec);
9373 break;
9374 case QUIRK_AE5:
9375 ca0132_mmio_init_ae5(codec);
9376 break;
9377 default:
9378 break;
9379 }
9380 }
9381
9382 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9383 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9384 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9385 };
9386
9387 static const unsigned char ca0132_ae5_register_set_data[] = {
9388 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9389 0x01, 0x6b, 0x57
9390 };
9391
9392 /*
9393 * This function writes to some SFR's, does some region2 writes, and then
9394 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9395 * what it does.
9396 */
ae5_register_set(struct hda_codec * codec)9397 static void ae5_register_set(struct hda_codec *codec)
9398 {
9399 struct ca0132_spec *spec = codec->spec;
9400 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9401 const unsigned int *addr = ca0132_ae5_register_set_addresses;
9402 const unsigned char *data = ca0132_ae5_register_set_data;
9403 unsigned int i, cur_addr;
9404 unsigned char tmp[3];
9405
9406 if (ca0132_quirk(spec) == QUIRK_AE7)
9407 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9408
9409 chipio_8051_write_direct(codec, 0x93, 0x10);
9410 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9411
9412 if (ca0132_quirk(spec) == QUIRK_AE7) {
9413 tmp[0] = 0x03;
9414 tmp[1] = 0x03;
9415 tmp[2] = 0x07;
9416 } else {
9417 tmp[0] = 0x0f;
9418 tmp[1] = 0x0f;
9419 tmp[2] = 0x0f;
9420 }
9421
9422 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9423 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9424
9425 /*
9426 * First writes are in single bytes, final are in 4 bytes. So, we use
9427 * writeb, then writel.
9428 */
9429 for (i = 0; cur_addr < 12; i++, cur_addr++)
9430 writeb(data[i], spec->mem_base + addr[cur_addr]);
9431
9432 for (; cur_addr < count; i++, cur_addr++)
9433 writel(data[i], spec->mem_base + addr[cur_addr]);
9434
9435 writel(0x00800001, spec->mem_base + 0x20c);
9436
9437 if (ca0132_quirk(spec) == QUIRK_AE7) {
9438 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9439 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9440 } else {
9441 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9442 }
9443
9444 chipio_8051_write_direct(codec, 0x90, 0x00);
9445 chipio_8051_write_direct(codec, 0x90, 0x10);
9446
9447 if (ca0132_quirk(spec) == QUIRK_AE5)
9448 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9449 }
9450
9451 /*
9452 * Extra init functions for alternative ca0132 codecs. Done
9453 * here so they don't clutter up the main ca0132_init function
9454 * anymore than they have to.
9455 */
ca0132_alt_init(struct hda_codec * codec)9456 static void ca0132_alt_init(struct hda_codec *codec)
9457 {
9458 struct ca0132_spec *spec = codec->spec;
9459
9460 ca0132_alt_vol_setup(codec);
9461
9462 switch (ca0132_quirk(spec)) {
9463 case QUIRK_SBZ:
9464 codec_dbg(codec, "SBZ alt_init");
9465 ca0132_gpio_init(codec);
9466 sbz_pre_dsp_setup(codec);
9467 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9468 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9469 break;
9470 case QUIRK_R3DI:
9471 codec_dbg(codec, "R3DI alt_init");
9472 ca0132_gpio_init(codec);
9473 ca0132_gpio_setup(codec);
9474 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9475 r3di_pre_dsp_setup(codec);
9476 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9477 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9478 break;
9479 case QUIRK_R3D:
9480 r3d_pre_dsp_setup(codec);
9481 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9482 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9483 break;
9484 case QUIRK_AE5:
9485 ca0132_gpio_init(codec);
9486 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9487 chipio_write(codec, 0x18b030, 0x00000020);
9488 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9489 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9490 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9491 break;
9492 case QUIRK_AE7:
9493 ca0132_gpio_init(codec);
9494 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9495 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9496 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9497 chipio_write(codec, 0x18b008, 0x000000f8);
9498 chipio_write(codec, 0x18b008, 0x000000f0);
9499 chipio_write(codec, 0x18b030, 0x00000020);
9500 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9501 break;
9502 case QUIRK_ZXR:
9503 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9504 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9505 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9506 zxr_pre_dsp_setup(codec);
9507 break;
9508 default:
9509 break;
9510 }
9511 }
9512
ca0132_init(struct hda_codec * codec)9513 static int ca0132_init(struct hda_codec *codec)
9514 {
9515 struct ca0132_spec *spec = codec->spec;
9516 struct auto_pin_cfg *cfg = &spec->autocfg;
9517 int i;
9518 bool dsp_loaded;
9519
9520 /*
9521 * If the DSP is already downloaded, and init has been entered again,
9522 * there's only two reasons for it. One, the codec has awaken from a
9523 * suspended state, and in that case dspload_is_loaded will return
9524 * false, and the init will be ran again. The other reason it gets
9525 * re entered is on startup for some reason it triggers a suspend and
9526 * resume state. In this case, it will check if the DSP is downloaded,
9527 * and not run the init function again. For codecs using alt_functions,
9528 * it will check if the DSP is loaded properly.
9529 */
9530 if (spec->dsp_state == DSP_DOWNLOADED) {
9531 dsp_loaded = dspload_is_loaded(codec);
9532 if (!dsp_loaded) {
9533 spec->dsp_reload = true;
9534 spec->dsp_state = DSP_DOWNLOAD_INIT;
9535 } else {
9536 if (ca0132_quirk(spec) == QUIRK_SBZ)
9537 sbz_dsp_startup_check(codec);
9538 return 0;
9539 }
9540 }
9541
9542 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9543 spec->dsp_state = DSP_DOWNLOAD_INIT;
9544 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9545
9546 if (ca0132_use_pci_mmio(spec))
9547 ca0132_mmio_init(codec);
9548
9549 snd_hda_power_up_pm(codec);
9550
9551 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9552 ae5_register_set(codec);
9553
9554 ca0132_init_params(codec);
9555 ca0132_init_flags(codec);
9556
9557 snd_hda_sequence_write(codec, spec->base_init_verbs);
9558
9559 if (ca0132_use_alt_functions(spec))
9560 ca0132_alt_init(codec);
9561
9562 ca0132_download_dsp(codec);
9563
9564 ca0132_refresh_widget_caps(codec);
9565
9566 switch (ca0132_quirk(spec)) {
9567 case QUIRK_R3DI:
9568 case QUIRK_R3D:
9569 r3d_setup_defaults(codec);
9570 break;
9571 case QUIRK_SBZ:
9572 case QUIRK_ZXR:
9573 sbz_setup_defaults(codec);
9574 break;
9575 case QUIRK_AE5:
9576 ae5_setup_defaults(codec);
9577 break;
9578 case QUIRK_AE7:
9579 ae7_setup_defaults(codec);
9580 break;
9581 default:
9582 ca0132_setup_defaults(codec);
9583 ca0132_init_analog_mic2(codec);
9584 ca0132_init_dmic(codec);
9585 break;
9586 }
9587
9588 for (i = 0; i < spec->num_outputs; i++)
9589 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9590
9591 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9592
9593 for (i = 0; i < spec->num_inputs; i++)
9594 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9595
9596 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9597
9598 if (!ca0132_use_alt_functions(spec)) {
9599 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9601 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9602 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9603 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9604 }
9605
9606 if (ca0132_quirk(spec) == QUIRK_SBZ)
9607 ca0132_gpio_setup(codec);
9608
9609 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9610 if (ca0132_use_alt_functions(spec)) {
9611 ca0132_alt_select_out(codec);
9612 ca0132_alt_select_in(codec);
9613 } else {
9614 ca0132_select_out(codec);
9615 ca0132_select_mic(codec);
9616 }
9617
9618 snd_hda_jack_report_sync(codec);
9619
9620 /*
9621 * Re set the PlayEnhancement switch on a resume event, because the
9622 * controls will not be reloaded.
9623 */
9624 if (spec->dsp_reload) {
9625 spec->dsp_reload = false;
9626 ca0132_pe_switch_set(codec);
9627 }
9628
9629 snd_hda_power_down_pm(codec);
9630
9631 return 0;
9632 }
9633
dbpro_init(struct hda_codec * codec)9634 static int dbpro_init(struct hda_codec *codec)
9635 {
9636 struct ca0132_spec *spec = codec->spec;
9637 struct auto_pin_cfg *cfg = &spec->autocfg;
9638 unsigned int i;
9639
9640 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9641 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9642
9643 for (i = 0; i < spec->num_inputs; i++)
9644 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9645
9646 return 0;
9647 }
9648
ca0132_free(struct hda_codec * codec)9649 static void ca0132_free(struct hda_codec *codec)
9650 {
9651 struct ca0132_spec *spec = codec->spec;
9652
9653 cancel_delayed_work_sync(&spec->unsol_hp_work);
9654 snd_hda_power_up(codec);
9655 switch (ca0132_quirk(spec)) {
9656 case QUIRK_SBZ:
9657 sbz_exit_chip(codec);
9658 break;
9659 case QUIRK_ZXR:
9660 zxr_exit_chip(codec);
9661 break;
9662 case QUIRK_R3D:
9663 r3d_exit_chip(codec);
9664 break;
9665 case QUIRK_AE5:
9666 ae5_exit_chip(codec);
9667 break;
9668 case QUIRK_AE7:
9669 ae7_exit_chip(codec);
9670 break;
9671 case QUIRK_R3DI:
9672 r3di_gpio_shutdown(codec);
9673 break;
9674 default:
9675 break;
9676 }
9677
9678 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9679 ca0132_exit_chip(codec);
9680
9681 snd_hda_power_down(codec);
9682 #ifdef CONFIG_PCI
9683 if (spec->mem_base)
9684 pci_iounmap(codec->bus->pci, spec->mem_base);
9685 #endif
9686 kfree(spec->spec_init_verbs);
9687 kfree(codec->spec);
9688 }
9689
dbpro_free(struct hda_codec * codec)9690 static void dbpro_free(struct hda_codec *codec)
9691 {
9692 struct ca0132_spec *spec = codec->spec;
9693
9694 zxr_dbpro_power_state_shutdown(codec);
9695
9696 kfree(spec->spec_init_verbs);
9697 kfree(codec->spec);
9698 }
9699
ca0132_config(struct hda_codec * codec)9700 static void ca0132_config(struct hda_codec *codec)
9701 {
9702 struct ca0132_spec *spec = codec->spec;
9703
9704 spec->dacs[0] = 0x2;
9705 spec->dacs[1] = 0x3;
9706 spec->dacs[2] = 0x4;
9707
9708 spec->multiout.dac_nids = spec->dacs;
9709 spec->multiout.num_dacs = 3;
9710
9711 if (!ca0132_use_alt_functions(spec))
9712 spec->multiout.max_channels = 2;
9713 else
9714 spec->multiout.max_channels = 6;
9715
9716 switch (ca0132_quirk(spec)) {
9717 case QUIRK_ALIENWARE:
9718 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9719 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9720 break;
9721 case QUIRK_SBZ:
9722 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9723 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9724 break;
9725 case QUIRK_ZXR:
9726 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9727 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9728 break;
9729 case QUIRK_R3D:
9730 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9731 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9732 break;
9733 case QUIRK_R3DI:
9734 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9735 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9736 break;
9737 case QUIRK_AE5:
9738 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9739 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9740 break;
9741 case QUIRK_AE7:
9742 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9743 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9744 break;
9745 default:
9746 break;
9747 }
9748
9749 switch (ca0132_quirk(spec)) {
9750 case QUIRK_ALIENWARE:
9751 spec->num_outputs = 2;
9752 spec->out_pins[0] = 0x0b; /* speaker out */
9753 spec->out_pins[1] = 0x0f;
9754 spec->shared_out_nid = 0x2;
9755 spec->unsol_tag_hp = 0x0f;
9756
9757 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9758 spec->adcs[1] = 0x8; /* analog mic2 */
9759 spec->adcs[2] = 0xa; /* what u hear */
9760
9761 spec->num_inputs = 3;
9762 spec->input_pins[0] = 0x12;
9763 spec->input_pins[1] = 0x11;
9764 spec->input_pins[2] = 0x13;
9765 spec->shared_mic_nid = 0x7;
9766 spec->unsol_tag_amic1 = 0x11;
9767 break;
9768 case QUIRK_SBZ:
9769 case QUIRK_R3D:
9770 spec->num_outputs = 2;
9771 spec->out_pins[0] = 0x0B; /* Line out */
9772 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9773 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9774 spec->out_pins[3] = 0x11; /* Rear surround */
9775 spec->shared_out_nid = 0x2;
9776 spec->unsol_tag_hp = spec->out_pins[1];
9777 spec->unsol_tag_front_hp = spec->out_pins[2];
9778
9779 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9780 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9781 spec->adcs[2] = 0xa; /* what u hear */
9782
9783 spec->num_inputs = 2;
9784 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9785 spec->input_pins[1] = 0x13; /* What U Hear */
9786 spec->shared_mic_nid = 0x7;
9787 spec->unsol_tag_amic1 = spec->input_pins[0];
9788
9789 /* SPDIF I/O */
9790 spec->dig_out = 0x05;
9791 spec->multiout.dig_out_nid = spec->dig_out;
9792 spec->dig_in = 0x09;
9793 break;
9794 case QUIRK_ZXR:
9795 spec->num_outputs = 2;
9796 spec->out_pins[0] = 0x0B; /* Line out */
9797 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9798 spec->out_pins[2] = 0x10; /* Center/LFE */
9799 spec->out_pins[3] = 0x11; /* Rear surround */
9800 spec->shared_out_nid = 0x2;
9801 spec->unsol_tag_hp = spec->out_pins[1];
9802 spec->unsol_tag_front_hp = spec->out_pins[2];
9803
9804 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9805 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9806 spec->adcs[2] = 0xa; /* what u hear */
9807
9808 spec->num_inputs = 2;
9809 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9810 spec->input_pins[1] = 0x13; /* What U Hear */
9811 spec->shared_mic_nid = 0x7;
9812 spec->unsol_tag_amic1 = spec->input_pins[0];
9813 break;
9814 case QUIRK_ZXR_DBPRO:
9815 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9816
9817 spec->num_inputs = 1;
9818 spec->input_pins[0] = 0x11; /* RCA Line-in */
9819
9820 spec->dig_out = 0x05;
9821 spec->multiout.dig_out_nid = spec->dig_out;
9822
9823 spec->dig_in = 0x09;
9824 break;
9825 case QUIRK_AE5:
9826 case QUIRK_AE7:
9827 spec->num_outputs = 2;
9828 spec->out_pins[0] = 0x0B; /* Line out */
9829 spec->out_pins[1] = 0x11; /* Rear headphone out */
9830 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9831 spec->out_pins[3] = 0x0F; /* Rear surround */
9832 spec->shared_out_nid = 0x2;
9833 spec->unsol_tag_hp = spec->out_pins[1];
9834 spec->unsol_tag_front_hp = spec->out_pins[2];
9835
9836 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9837 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9838 spec->adcs[2] = 0xa; /* what u hear */
9839
9840 spec->num_inputs = 2;
9841 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9842 spec->input_pins[1] = 0x13; /* What U Hear */
9843 spec->shared_mic_nid = 0x7;
9844 spec->unsol_tag_amic1 = spec->input_pins[0];
9845
9846 /* SPDIF I/O */
9847 spec->dig_out = 0x05;
9848 spec->multiout.dig_out_nid = spec->dig_out;
9849 break;
9850 case QUIRK_R3DI:
9851 spec->num_outputs = 2;
9852 spec->out_pins[0] = 0x0B; /* Line out */
9853 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9854 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9855 spec->out_pins[3] = 0x11; /* Rear surround */
9856 spec->shared_out_nid = 0x2;
9857 spec->unsol_tag_hp = spec->out_pins[1];
9858 spec->unsol_tag_front_hp = spec->out_pins[2];
9859
9860 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9861 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9862 spec->adcs[2] = 0x0a; /* what u hear */
9863
9864 spec->num_inputs = 2;
9865 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9866 spec->input_pins[1] = 0x13; /* What U Hear */
9867 spec->shared_mic_nid = 0x7;
9868 spec->unsol_tag_amic1 = spec->input_pins[0];
9869
9870 /* SPDIF I/O */
9871 spec->dig_out = 0x05;
9872 spec->multiout.dig_out_nid = spec->dig_out;
9873 break;
9874 default:
9875 spec->num_outputs = 2;
9876 spec->out_pins[0] = 0x0b; /* speaker out */
9877 spec->out_pins[1] = 0x10; /* headphone out */
9878 spec->shared_out_nid = 0x2;
9879 spec->unsol_tag_hp = spec->out_pins[1];
9880
9881 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9882 spec->adcs[1] = 0x8; /* analog mic2 */
9883 spec->adcs[2] = 0xa; /* what u hear */
9884
9885 spec->num_inputs = 3;
9886 spec->input_pins[0] = 0x12;
9887 spec->input_pins[1] = 0x11;
9888 spec->input_pins[2] = 0x13;
9889 spec->shared_mic_nid = 0x7;
9890 spec->unsol_tag_amic1 = spec->input_pins[0];
9891
9892 /* SPDIF I/O */
9893 spec->dig_out = 0x05;
9894 spec->multiout.dig_out_nid = spec->dig_out;
9895 spec->dig_in = 0x09;
9896 break;
9897 }
9898 }
9899
ca0132_prepare_verbs(struct hda_codec * codec)9900 static int ca0132_prepare_verbs(struct hda_codec *codec)
9901 {
9902 /* Verbs + terminator (an empty element) */
9903 #define NUM_SPEC_VERBS 2
9904 struct ca0132_spec *spec = codec->spec;
9905
9906 spec->chip_init_verbs = ca0132_init_verbs0;
9907 /*
9908 * Since desktop cards use pci_mmio, this can be used to determine
9909 * whether or not to use these verbs instead of a separate bool.
9910 */
9911 if (ca0132_use_pci_mmio(spec))
9912 spec->desktop_init_verbs = ca0132_init_verbs1;
9913 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9914 sizeof(struct hda_verb),
9915 GFP_KERNEL);
9916 if (!spec->spec_init_verbs)
9917 return -ENOMEM;
9918
9919 /* config EAPD */
9920 spec->spec_init_verbs[0].nid = 0x0b;
9921 spec->spec_init_verbs[0].param = 0x78D;
9922 spec->spec_init_verbs[0].verb = 0x00;
9923
9924 /* Previously commented configuration */
9925 /*
9926 spec->spec_init_verbs[2].nid = 0x0b;
9927 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9928 spec->spec_init_verbs[2].verb = 0x02;
9929
9930 spec->spec_init_verbs[3].nid = 0x10;
9931 spec->spec_init_verbs[3].param = 0x78D;
9932 spec->spec_init_verbs[3].verb = 0x02;
9933
9934 spec->spec_init_verbs[4].nid = 0x10;
9935 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9936 spec->spec_init_verbs[4].verb = 0x02;
9937 */
9938
9939 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9940 return 0;
9941 }
9942
9943 /*
9944 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9945 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9946 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9947 * daughter boards ID.
9948 */
sbz_detect_quirk(struct hda_codec * codec)9949 static void sbz_detect_quirk(struct hda_codec *codec)
9950 {
9951 switch (codec->core.subsystem_id) {
9952 case 0x11020033:
9953 codec->fixup_id = QUIRK_ZXR;
9954 break;
9955 case 0x1102003f:
9956 codec->fixup_id = QUIRK_ZXR_DBPRO;
9957 break;
9958 default:
9959 codec->fixup_id = QUIRK_SBZ;
9960 break;
9961 }
9962 }
9963
ca0132_codec_remove(struct hda_codec * codec)9964 static void ca0132_codec_remove(struct hda_codec *codec)
9965 {
9966 struct ca0132_spec *spec = codec->spec;
9967
9968 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
9969 return dbpro_free(codec);
9970 else
9971 return ca0132_free(codec);
9972 }
9973
ca0132_codec_probe(struct hda_codec * codec,const struct hda_device_id * id)9974 static int ca0132_codec_probe(struct hda_codec *codec,
9975 const struct hda_device_id *id)
9976 {
9977 struct ca0132_spec *spec;
9978 int err;
9979
9980 codec_dbg(codec, "%s\n", __func__);
9981
9982 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9983 if (!spec)
9984 return -ENOMEM;
9985 codec->spec = spec;
9986 spec->codec = codec;
9987
9988 /* Detect codec quirk */
9989 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL);
9990 if (ca0132_quirk(spec) == QUIRK_SBZ)
9991 sbz_detect_quirk(codec);
9992
9993 codec->pcm_format_first = 1;
9994 codec->no_sticky_stream = 1;
9995
9996
9997 spec->dsp_state = DSP_DOWNLOAD_INIT;
9998 spec->num_mixers = 1;
9999
10000 /* Set which mixers each quirk uses. */
10001 switch (ca0132_quirk(spec)) {
10002 case QUIRK_SBZ:
10003 spec->mixers[0] = desktop_mixer;
10004 snd_hda_codec_set_name(codec, "Sound Blaster Z");
10005 break;
10006 case QUIRK_ZXR:
10007 spec->mixers[0] = desktop_mixer;
10008 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
10009 break;
10010 case QUIRK_ZXR_DBPRO:
10011 break;
10012 case QUIRK_R3D:
10013 spec->mixers[0] = desktop_mixer;
10014 snd_hda_codec_set_name(codec, "Recon3D");
10015 break;
10016 case QUIRK_R3DI:
10017 spec->mixers[0] = r3di_mixer;
10018 snd_hda_codec_set_name(codec, "Recon3Di");
10019 break;
10020 case QUIRK_AE5:
10021 spec->mixers[0] = desktop_mixer;
10022 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
10023 break;
10024 case QUIRK_AE7:
10025 spec->mixers[0] = desktop_mixer;
10026 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
10027 break;
10028 default:
10029 spec->mixers[0] = ca0132_mixer;
10030 break;
10031 }
10032
10033 /* Setup whether or not to use alt functions/controls/pci_mmio */
10034 switch (ca0132_quirk(spec)) {
10035 case QUIRK_SBZ:
10036 case QUIRK_R3D:
10037 case QUIRK_AE5:
10038 case QUIRK_AE7:
10039 case QUIRK_ZXR:
10040 spec->use_alt_controls = true;
10041 spec->use_alt_functions = true;
10042 spec->use_pci_mmio = true;
10043 break;
10044 case QUIRK_R3DI:
10045 spec->use_alt_controls = true;
10046 spec->use_alt_functions = true;
10047 spec->use_pci_mmio = false;
10048 break;
10049 default:
10050 spec->use_alt_controls = false;
10051 spec->use_alt_functions = false;
10052 spec->use_pci_mmio = false;
10053 break;
10054 }
10055
10056 #ifdef CONFIG_PCI
10057 if (spec->use_pci_mmio) {
10058 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
10059 if (spec->mem_base == NULL) {
10060 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
10061 codec->fixup_id = QUIRK_NONE;
10062 }
10063 }
10064 #endif
10065
10066 spec->base_init_verbs = ca0132_base_init_verbs;
10067 spec->base_exit_verbs = ca0132_base_exit_verbs;
10068
10069 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
10070
10071 ca0132_init_chip(codec);
10072
10073 ca0132_config(codec);
10074
10075 err = ca0132_prepare_verbs(codec);
10076 if (err < 0)
10077 goto error;
10078
10079 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10080 if (err < 0)
10081 goto error;
10082
10083 ca0132_setup_unsol(codec);
10084
10085 return 0;
10086
10087 error:
10088 ca0132_codec_remove(codec);
10089 return err;
10090 }
10091
ca0132_codec_build_controls(struct hda_codec * codec)10092 static int ca0132_codec_build_controls(struct hda_codec *codec)
10093 {
10094 struct ca0132_spec *spec = codec->spec;
10095
10096 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10097 return dbpro_build_controls(codec);
10098 else
10099 return ca0132_build_controls(codec);
10100 }
10101
ca0132_codec_build_pcms(struct hda_codec * codec)10102 static int ca0132_codec_build_pcms(struct hda_codec *codec)
10103 {
10104 struct ca0132_spec *spec = codec->spec;
10105
10106 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10107 return dbpro_build_pcms(codec);
10108 else
10109 return ca0132_build_pcms(codec);
10110 }
10111
ca0132_codec_init(struct hda_codec * codec)10112 static int ca0132_codec_init(struct hda_codec *codec)
10113 {
10114 struct ca0132_spec *spec = codec->spec;
10115
10116 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10117 return dbpro_init(codec);
10118 else
10119 return ca0132_init(codec);
10120 }
10121
ca0132_codec_suspend(struct hda_codec * codec)10122 static int ca0132_codec_suspend(struct hda_codec *codec)
10123 {
10124 struct ca0132_spec *spec = codec->spec;
10125
10126 cancel_delayed_work_sync(&spec->unsol_hp_work);
10127 return 0;
10128 }
10129
10130 static const struct hda_codec_ops ca0132_codec_ops = {
10131 .probe = ca0132_codec_probe,
10132 .remove = ca0132_codec_remove,
10133 .build_controls = ca0132_codec_build_controls,
10134 .build_pcms = ca0132_codec_build_pcms,
10135 .init = ca0132_codec_init,
10136 .unsol_event = snd_hda_jack_unsol_event,
10137 .suspend = ca0132_codec_suspend,
10138 };
10139
10140 /*
10141 * driver entries
10142 */
10143 static const struct hda_device_id snd_hda_id_ca0132[] = {
10144 HDA_CODEC_ID(0x11020011, "CA0132"),
10145 {} /* terminator */
10146 };
10147 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
10148
10149 MODULE_LICENSE("GPL");
10150 MODULE_DESCRIPTION("Creative Sound Core3D codec");
10151
10152 static struct hda_codec_driver ca0132_driver = {
10153 .id = snd_hda_id_ca0132,
10154 .ops = &ca0132_codec_ops,
10155 };
10156
10157 module_hda_codec_driver(ca0132_driver);
10158