1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2019 NXP 3 4 #include <linux/bitrev.h> 5 #include <linux/clk.h> 6 #include <linux/firmware.h> 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of_platform.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 #include <linux/reset.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_iec958.h> 15 #include <sound/pcm_params.h> 16 17 #include "fsl_xcvr.h" 18 #include "fsl_utils.h" 19 #include "imx-pcm.h" 20 21 #define FSL_XCVR_CAPDS_SIZE 256 22 #define SPDIF_NUM_RATES 7 23 24 enum fsl_xcvr_pll_verison { 25 PLL_MX8MP, 26 PLL_MX95, 27 }; 28 29 struct fsl_xcvr_soc_data { 30 const char *fw_name; 31 bool spdif_only; 32 bool use_edma; 33 bool use_phy; 34 enum fsl_xcvr_pll_verison pll_ver; 35 }; 36 37 struct fsl_xcvr { 38 const struct fsl_xcvr_soc_data *soc_data; 39 struct platform_device *pdev; 40 struct regmap *regmap; 41 struct regmap *regmap_phy; 42 struct regmap *regmap_pll; 43 struct clk *ipg_clk; 44 struct clk *pll_ipg_clk; 45 struct clk *phy_clk; 46 struct clk *spba_clk; 47 struct clk *pll8k_clk; 48 struct clk *pll11k_clk; 49 struct reset_control *reset; 50 u8 streams; 51 u32 mode; 52 u32 arc_mode; 53 void __iomem *ram_addr; 54 struct snd_dmaengine_dai_dma_data dma_prms_rx; 55 struct snd_dmaengine_dai_dma_data dma_prms_tx; 56 struct snd_aes_iec958 rx_iec958; 57 struct snd_aes_iec958 tx_iec958; 58 u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; 59 struct work_struct work_rst; 60 spinlock_t lock; /* Protect hw_reset and trigger */ 61 struct snd_pcm_hw_constraint_list spdif_constr_rates; 62 u32 spdif_constr_rates_list[SPDIF_NUM_RATES]; 63 }; 64 65 static const char * const inc_mode[] = { 66 "On enabled and bitcount increment", "On enabled" 67 }; 68 69 static SOC_ENUM_SINGLE_DECL(transmit_tstmp_enum, 70 FSL_XCVR_TX_DPTH_CNTR_CTRL, 71 FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode); 72 static SOC_ENUM_SINGLE_DECL(receive_tstmp_enum, 73 FSL_XCVR_RX_DPTH_CNTR_CTRL, 74 FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC_SHIFT, inc_mode); 75 76 static const struct snd_kcontrol_new fsl_xcvr_timestamp_ctrls[] = { 77 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Control Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL, 78 FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0, 79 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 80 FSL_ASOC_ENUM_EXT("Transmit Timestamp Increment", transmit_tstmp_enum, 81 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 82 FSL_ASOC_SINGLE_EXT("Transmit Timestamp Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL, 83 FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0, 84 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 85 FSL_ASOC_SINGLE_EXT("Transmit Bit Counter Reset Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL, 86 FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0, 87 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 88 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Timestamp Counter", FSL_XCVR_TX_DPTH_TSCR, 89 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 90 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Counter", FSL_XCVR_TX_DPTH_BCR, 91 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 92 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Bit Count Timestamp", FSL_XCVR_TX_DPTH_BCTR, 93 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 94 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Transmit Latched Timestamp Counter", FSL_XCVR_TX_DPTH_BCRR, 95 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 96 FSL_ASOC_SINGLE_EXT("Receive Timestamp Control Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL, 97 FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN_SHIFT, 1, 0, 98 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 99 FSL_ASOC_ENUM_EXT("Receive Timestamp Increment", receive_tstmp_enum, 100 fsl_asoc_get_enum_double, fsl_asoc_put_enum_double), 101 FSL_ASOC_SINGLE_EXT("Receive Timestamp Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL, 102 FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC_SHIFT, 1, 0, 103 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 104 FSL_ASOC_SINGLE_EXT("Receive Bit Counter Reset Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL, 105 FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC_SHIFT, 1, 0, 106 fsl_asoc_get_volsw, fsl_asoc_put_volsw), 107 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Timestamp Counter", FSL_XCVR_RX_DPTH_TSCR, 108 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 109 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Counter", FSL_XCVR_RX_DPTH_BCR, 110 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 111 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Bit Count Timestamp", FSL_XCVR_RX_DPTH_BCTR, 112 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 113 FSL_ASOC_SINGLE_XR_SX_EXT_RO("Receive Latched Timestamp Counter", FSL_XCVR_RX_DPTH_BCRR, 114 1, 32, 0, 0xffffffff, 0, fsl_asoc_get_xr_sx), 115 }; 116 117 static const struct fsl_xcvr_pll_conf { 118 u8 mfi; /* min=0x18, max=0x38 */ 119 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ 120 u32 mfd; /* unsigned int */ 121 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */ 122 } fsl_xcvr_pll_cfg[] = { 123 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */ 124 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */ 125 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */ 126 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */ 127 }; 128 129 /* 130 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio 131 * stream. Todo: to check how this case can be considered below 132 */ 133 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; 134 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = { 135 .count = ARRAY_SIZE(fsl_xcvr_earc_channels), 136 .list = fsl_xcvr_earc_channels, 137 }; 138 139 static const u32 fsl_xcvr_earc_rates[] = { 140 32000, 44100, 48000, 64000, 88200, 96000, 141 128000, 176400, 192000, 256000, 352800, 384000, 142 512000, 705600, 768000, 1024000, 1411200, 1536000, 143 }; 144 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = { 145 .count = ARRAY_SIZE(fsl_xcvr_earc_rates), 146 .list = fsl_xcvr_earc_rates, 147 }; 148 149 static const u32 fsl_xcvr_spdif_channels[] = { 2, }; 150 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = { 151 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels), 152 .list = fsl_xcvr_spdif_channels, 153 }; 154 155 static const u32 fsl_xcvr_spdif_rates[] = { 156 32000, 44100, 48000, 88200, 96000, 176400, 192000, 157 }; 158 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = { 159 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates), 160 .list = fsl_xcvr_spdif_rates, 161 }; 162 163 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol, 164 struct snd_ctl_elem_value *ucontrol) 165 { 166 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 167 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 168 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 169 unsigned int *item = ucontrol->value.enumerated.item; 170 int val = snd_soc_enum_item_to_val(e, item[0]); 171 int ret; 172 173 if (val < 0 || val > 1) 174 return -EINVAL; 175 176 ret = (xcvr->arc_mode != val); 177 178 xcvr->arc_mode = val; 179 180 return ret; 181 } 182 183 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol, 184 struct snd_ctl_elem_value *ucontrol) 185 { 186 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 187 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 188 189 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; 190 191 return 0; 192 } 193 194 static const u32 fsl_xcvr_phy_arc_cfg[] = { 195 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN, 196 }; 197 198 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", }; 199 static const struct soc_enum fsl_xcvr_arc_mode_enum = 200 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode); 201 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl = 202 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum, 203 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put); 204 205 /* Capabilities data structure, bytes */ 206 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol, 207 struct snd_ctl_elem_info *uinfo) 208 { 209 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 210 uinfo->count = FSL_XCVR_CAPDS_SIZE; 211 212 return 0; 213 } 214 215 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol, 216 struct snd_ctl_elem_value *ucontrol) 217 { 218 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 219 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 220 221 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); 222 223 return 0; 224 } 225 226 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol, 227 struct snd_ctl_elem_value *ucontrol) 228 { 229 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 230 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 231 232 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); 233 234 return 0; 235 } 236 237 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = { 238 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 239 .name = "Capabilities Data Structure", 240 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 241 .info = fsl_xcvr_type_capds_bytes_info, 242 .get = fsl_xcvr_capds_get, 243 .put = fsl_xcvr_capds_put, 244 }; 245 246 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name, 247 bool active) 248 { 249 struct snd_soc_card *card = dai->component->card; 250 struct snd_kcontrol *kctl; 251 bool enabled; 252 253 lockdep_assert_held(&card->snd_card->controls_rwsem); 254 255 kctl = snd_soc_card_get_kcontrol(card, name); 256 if (kctl == NULL) 257 return -ENOENT; 258 259 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); 260 if (active == enabled) 261 return 0; /* nothing to do */ 262 263 if (active) 264 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 265 else 266 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; 267 268 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); 269 270 return 1; 271 } 272 273 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol, 274 struct snd_ctl_elem_value *ucontrol) 275 { 276 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 277 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 278 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 279 unsigned int *item = ucontrol->value.enumerated.item; 280 int val = snd_soc_enum_item_to_val(e, item[0]); 281 struct snd_soc_card *card = dai->component->card; 282 struct snd_soc_pcm_runtime *rtd; 283 int ret; 284 285 if (val < FSL_XCVR_MODE_SPDIF || val > FSL_XCVR_MODE_EARC) 286 return -EINVAL; 287 288 ret = (xcvr->mode != val); 289 290 xcvr->mode = val; 291 292 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 293 (xcvr->mode == FSL_XCVR_MODE_ARC)); 294 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 295 (xcvr->mode == FSL_XCVR_MODE_EARC)); 296 /* Allow playback for SPDIF only */ 297 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 298 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = 299 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); 300 return ret; 301 } 302 303 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol, 304 struct snd_ctl_elem_value *ucontrol) 305 { 306 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 307 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 308 309 ucontrol->value.enumerated.item[0] = xcvr->mode; 310 311 return 0; 312 } 313 314 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", }; 315 static const struct soc_enum fsl_xcvr_mode_enum = 316 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode); 317 static struct snd_kcontrol_new fsl_xcvr_mode_kctl = 318 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum, 319 fsl_xcvr_mode_get, fsl_xcvr_mode_put); 320 321 /** phy: true => phy, false => pll */ 322 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) 323 { 324 struct device *dev = &xcvr->pdev->dev; 325 u32 val, idx, tidx; 326 int ret; 327 328 idx = BIT(phy ? 26 : 24); 329 tidx = BIT(phy ? 27 : 25); 330 331 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 332 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); 333 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); 334 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 335 336 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 337 (val & idx) == ((val & tidx) >> 1), 338 10, 10000); 339 if (ret) 340 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n", 341 phy ? "PHY" : "PLL", reg, data); 342 return ret; 343 } 344 345 static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy) 346 { 347 struct device *dev = &xcvr->pdev->dev; 348 u32 val, idx, tidx; 349 int ret; 350 351 idx = BIT(phy ? 26 : 24); 352 tidx = BIT(phy ? 27 : 25); 353 354 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 355 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 356 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 357 358 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 359 (val & idx) == ((val & tidx) >> 1), 360 10, 10000); 361 if (ret) 362 dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n", 363 phy ? "PHY" : "PLL", reg); 364 365 regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data); 366 367 return ret; 368 } 369 370 static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val) 371 { 372 struct fsl_xcvr *xcvr = context; 373 374 return fsl_xcvr_ai_read(xcvr, reg, val, 1); 375 } 376 377 static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val) 378 { 379 struct fsl_xcvr *xcvr = context; 380 381 return fsl_xcvr_ai_write(xcvr, reg, val, 1); 382 } 383 384 static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val) 385 { 386 struct fsl_xcvr *xcvr = context; 387 388 return fsl_xcvr_ai_read(xcvr, reg, val, 0); 389 } 390 391 static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val) 392 { 393 struct fsl_xcvr *xcvr = context; 394 395 return fsl_xcvr_ai_write(xcvr, reg, val, 0); 396 } 397 398 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) 399 { 400 struct device *dev = &xcvr->pdev->dev; 401 u32 i, div = 0, log2, val; 402 int ret; 403 404 if (!xcvr->soc_data->use_phy) 405 return 0; 406 407 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) { 408 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) { 409 div = fsl_xcvr_pll_cfg[i].fout / freq; 410 break; 411 } 412 } 413 414 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg)) 415 return -EINVAL; 416 417 log2 = ilog2(div); 418 419 /* Release AI interface from reset */ 420 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 421 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 422 if (ret < 0) { 423 dev_err(dev, "Error while setting IER0: %d\n", ret); 424 return ret; 425 } 426 427 switch (xcvr->soc_data->pll_ver) { 428 case PLL_MX8MP: 429 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ 430 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP, 431 FSL_XCVR_PLL_BANDGAP_EN_VBG); 432 433 /* PLL: CTRL0: DIV_INTEGER */ 434 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi); 435 /* PLL: NUMERATOR: MFN */ 436 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn); 437 /* PLL: DENOMINATOR: MFD */ 438 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd); 439 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ 440 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 441 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP); 442 udelay(25); 443 /* PLL: CTRL0: Clear Hold Ring Off */ 444 regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 445 FSL_XCVR_PLL_CTRL0_HROFF); 446 udelay(100); 447 if (tx) { /* TX is enabled for SPDIF only */ 448 /* PLL: POSTDIV: PDIV0 */ 449 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 450 FSL_XCVR_PLL_PDIVx(log2, 0)); 451 /* PLL: CTRL_SET: CLKMUX0_EN */ 452 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 453 FSL_XCVR_PLL_CTRL0_CM0_EN); 454 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ 455 /* PLL: POSTDIV: PDIV1 */ 456 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 457 FSL_XCVR_PLL_PDIVx(log2, 1)); 458 /* PLL: CTRL_SET: CLKMUX1_EN */ 459 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 460 FSL_XCVR_PLL_CTRL0_CM1_EN); 461 } else { /* SPDIF / ARC RX */ 462 /* PLL: POSTDIV: PDIV2 */ 463 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 464 FSL_XCVR_PLL_PDIVx(log2, 2)); 465 /* PLL: CTRL_SET: CLKMUX2_EN */ 466 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 467 FSL_XCVR_PLL_CTRL0_CM2_EN); 468 } 469 break; 470 case PLL_MX95: 471 val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div; 472 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val); 473 val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT; 474 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val); 475 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR, 476 fsl_xcvr_pll_cfg[i].mfd); 477 val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN; 478 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val); 479 break; 480 default: 481 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); 482 return -EINVAL; 483 } 484 485 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 486 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 487 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 488 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 489 FSL_XCVR_PHY_CTRL_PHY_EN); 490 /* PHY: CTRL2_SET: EARC_TX_MODE */ 491 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 492 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 493 } else if (!tx) { /* SPDIF / ARC RX mode */ 494 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 495 /* PHY: CTRL_SET: SPDIF_EN */ 496 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 497 FSL_XCVR_PHY_CTRL_SPDIF_EN); 498 else /* PHY: CTRL_SET: ARC RX setup */ 499 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 500 FSL_XCVR_PHY_CTRL_PHY_EN | 501 FSL_XCVR_PHY_CTRL_RX_CM_EN | 502 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]); 503 } 504 505 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", 506 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi, 507 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2); 508 return 0; 509 } 510 511 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) 512 { 513 struct device *dev = &xcvr->pdev->dev; 514 int ret; 515 516 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; 517 clk_disable_unprepare(xcvr->phy_clk); 518 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk, 519 xcvr->pll8k_clk, xcvr->pll11k_clk, freq); 520 ret = clk_set_rate(xcvr->phy_clk, freq); 521 if (ret < 0) { 522 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret); 523 return ret; 524 } 525 ret = clk_prepare_enable(xcvr->phy_clk); 526 if (ret) { 527 dev_err(dev, "failed to start PHY clock: %d\n", ret); 528 return ret; 529 } 530 531 if (!xcvr->soc_data->use_phy) 532 return 0; 533 /* Release AI interface from reset */ 534 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 535 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 536 if (ret < 0) { 537 dev_err(dev, "Error while setting IER0: %d\n", ret); 538 return ret; 539 } 540 541 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 542 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 543 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 544 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 545 FSL_XCVR_PHY_CTRL_PHY_EN); 546 /* PHY: CTRL2_SET: EARC_TX_MODE */ 547 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 548 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 549 } else { /* SPDIF mode */ 550 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ 551 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 552 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | 553 FSL_XCVR_PHY_CTRL_SPDIF_EN); 554 } 555 556 dev_dbg(dev, "PLL Fexp: %u\n", freq); 557 558 return 0; 559 } 560 561 #define FSL_XCVR_SPDIF_RX_FREQ 175000000 562 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, 563 struct snd_soc_dai *dai) 564 { 565 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 566 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 567 u32 m_ctl = 0, v_ctl = 0; 568 u32 r = substream->runtime->rate, ch = substream->runtime->channels; 569 u32 fout = 32 * r * ch * 10; 570 int ret = 0; 571 572 switch (xcvr->mode) { 573 case FSL_XCVR_MODE_SPDIF: 574 if (xcvr->soc_data->spdif_only && tx) { 575 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 576 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, 577 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); 578 if (ret < 0) { 579 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); 580 return ret; 581 } 582 } 583 fallthrough; 584 case FSL_XCVR_MODE_ARC: 585 if (tx) { 586 ret = fsl_xcvr_en_aud_pll(xcvr, fout); 587 if (ret < 0) { 588 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", 589 fout, ret); 590 return ret; 591 } 592 593 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 594 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); 595 if (ret < 0) { 596 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); 597 return ret; 598 } 599 600 /** 601 * set SPDIF MODE - this flag is used to gate 602 * SPDIF output, useless for SPDIF RX 603 */ 604 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 605 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 606 } else { 607 /** 608 * Clear RX FIFO, flip RX FIFO bits, 609 * disable eARC related HW mode detects 610 */ 611 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 612 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 613 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | 614 FSL_XCVR_RX_DPTH_CTRL_COMP | 615 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 616 if (ret < 0) { 617 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 618 return ret; 619 } 620 621 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); 622 if (ret < 0) { 623 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", 624 FSL_XCVR_SPDIF_RX_FREQ, ret); 625 return ret; 626 } 627 } 628 break; 629 case FSL_XCVR_MODE_EARC: 630 if (!tx) { 631 /** Clear RX FIFO, flip RX FIFO bits */ 632 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 633 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 634 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); 635 if (ret < 0) { 636 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 637 return ret; 638 } 639 640 /** Enable eARC related HW mode detects */ 641 ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 642 FSL_XCVR_RX_DPTH_CTRL_COMP | 643 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 644 if (ret < 0) { 645 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); 646 return ret; 647 } 648 } 649 650 /* clear CMDC RESET */ 651 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 652 /* set TX_RX_MODE */ 653 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE; 654 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0); 655 break; 656 } 657 658 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); 659 if (ret < 0) { 660 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); 661 return ret; 662 } 663 664 return 0; 665 } 666 667 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream, 668 const struct snd_pcm_hw_constraint_list *channels, 669 const struct snd_pcm_hw_constraint_list *rates) 670 { 671 struct snd_pcm_runtime *rt = substream->runtime; 672 int ret; 673 674 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 675 channels); 676 if (ret < 0) 677 return ret; 678 679 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE, 680 rates); 681 if (ret < 0) 682 return ret; 683 684 return 0; 685 } 686 687 static int fsl_xcvr_startup(struct snd_pcm_substream *substream, 688 struct snd_soc_dai *dai) 689 { 690 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 691 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 692 int ret = 0; 693 694 if (xcvr->streams & BIT(substream->stream)) { 695 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); 696 return -EBUSY; 697 } 698 699 /* 700 * EDMA controller needs period size to be a multiple of 701 * tx/rx maxburst 702 */ 703 if (xcvr->soc_data->use_edma) 704 snd_pcm_hw_constraint_step(substream->runtime, 0, 705 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 706 tx ? xcvr->dma_prms_tx.maxburst : 707 xcvr->dma_prms_rx.maxburst); 708 709 switch (xcvr->mode) { 710 case FSL_XCVR_MODE_SPDIF: 711 case FSL_XCVR_MODE_ARC: 712 if (xcvr->soc_data->spdif_only && tx) 713 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 714 &xcvr->spdif_constr_rates); 715 else 716 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 717 &fsl_xcvr_spdif_rates_constr); 718 break; 719 case FSL_XCVR_MODE_EARC: 720 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr, 721 &fsl_xcvr_earc_rates_constr); 722 break; 723 } 724 if (ret < 0) 725 return ret; 726 727 xcvr->streams |= BIT(substream->stream); 728 729 if (!xcvr->soc_data->spdif_only) { 730 struct snd_soc_card *card = dai->component->card; 731 732 /* Disable XCVR controls if there is stream started */ 733 down_read(&card->snd_card->controls_rwsem); 734 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false); 735 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false); 736 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false); 737 up_read(&card->snd_card->controls_rwsem); 738 } 739 740 return 0; 741 } 742 743 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream, 744 struct snd_soc_dai *dai) 745 { 746 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 747 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 748 u32 mask = 0, val = 0; 749 int ret; 750 751 xcvr->streams &= ~BIT(substream->stream); 752 753 /* Enable XCVR controls if there is no stream started */ 754 if (!xcvr->streams) { 755 if (!xcvr->soc_data->spdif_only) { 756 struct snd_soc_card *card = dai->component->card; 757 758 down_read(&card->snd_card->controls_rwsem); 759 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true); 760 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 761 (xcvr->mode == FSL_XCVR_MODE_ARC)); 762 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 763 (xcvr->mode == FSL_XCVR_MODE_EARC)); 764 up_read(&card->snd_card->controls_rwsem); 765 } 766 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 767 FSL_XCVR_IRQ_EARC_ALL, 0); 768 if (ret < 0) { 769 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); 770 return; 771 } 772 773 /* clear SPDIF MODE */ 774 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 775 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 776 } 777 778 if (xcvr->mode == FSL_XCVR_MODE_EARC) { 779 /* set CMDC RESET */ 780 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 781 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 782 } 783 784 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 785 if (ret < 0) { 786 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); 787 return; 788 } 789 } 790 791 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, 792 struct snd_soc_dai *dai) 793 { 794 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 795 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 796 unsigned long lock_flags; 797 int ret = 0; 798 799 spin_lock_irqsave(&xcvr->lock, lock_flags); 800 801 switch (cmd) { 802 case SNDRV_PCM_TRIGGER_START: 803 case SNDRV_PCM_TRIGGER_RESUME: 804 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 805 /* set DPATH RESET */ 806 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 807 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 808 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx)); 809 if (ret < 0) { 810 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret); 811 goto release_lock; 812 } 813 814 if (tx) { 815 switch (xcvr->mode) { 816 case FSL_XCVR_MODE_EARC: 817 /* set isr_cmdc_tx_en, w1c */ 818 ret = regmap_write(xcvr->regmap, 819 FSL_XCVR_ISR_SET, 820 FSL_XCVR_ISR_CMDC_TX_EN); 821 if (ret < 0) { 822 dev_err(dai->dev, "err updating isr %d\n", ret); 823 goto release_lock; 824 } 825 fallthrough; 826 case FSL_XCVR_MODE_SPDIF: 827 ret = regmap_set_bits(xcvr->regmap, 828 FSL_XCVR_TX_DPTH_CTRL, 829 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 830 if (ret < 0) { 831 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); 832 goto release_lock; 833 } 834 break; 835 } 836 } 837 838 /* enable DMA RD/WR */ 839 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 840 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0); 841 if (ret < 0) { 842 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); 843 goto release_lock; 844 } 845 846 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 847 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL); 848 if (ret < 0) { 849 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); 850 goto release_lock; 851 } 852 853 /* clear DPATH RESET */ 854 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 855 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 856 0); 857 if (ret < 0) { 858 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); 859 goto release_lock; 860 } 861 862 break; 863 case SNDRV_PCM_TRIGGER_STOP: 864 case SNDRV_PCM_TRIGGER_SUSPEND: 865 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 866 /* disable DMA RD/WR */ 867 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 868 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 869 FSL_XCVR_EXT_CTRL_DMA_DIS(tx)); 870 if (ret < 0) { 871 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); 872 goto release_lock; 873 } 874 875 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 876 FSL_XCVR_IRQ_EARC_ALL, 0); 877 if (ret < 0) { 878 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret); 879 goto release_lock; 880 } 881 882 if (tx) { 883 switch (xcvr->mode) { 884 case FSL_XCVR_MODE_SPDIF: 885 ret = regmap_clear_bits(xcvr->regmap, 886 FSL_XCVR_TX_DPTH_CTRL, 887 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 888 if (ret < 0) { 889 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); 890 goto release_lock; 891 } 892 if (xcvr->soc_data->spdif_only) 893 break; 894 else 895 fallthrough; 896 case FSL_XCVR_MODE_EARC: 897 /* clear ISR_CMDC_TX_EN, W1C */ 898 ret = regmap_write(xcvr->regmap, 899 FSL_XCVR_ISR_CLR, 900 FSL_XCVR_ISR_CMDC_TX_EN); 901 if (ret < 0) { 902 dev_err(dai->dev, 903 "Err updating ISR %d\n", ret); 904 goto release_lock; 905 } 906 break; 907 } 908 } 909 break; 910 default: 911 ret = -EINVAL; 912 break; 913 } 914 915 release_lock: 916 spin_unlock_irqrestore(&xcvr->lock, lock_flags); 917 return ret; 918 } 919 920 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) 921 { 922 struct device *dev = &xcvr->pdev->dev; 923 const struct firmware *fw; 924 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET; 925 u32 mask, val; 926 927 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); 928 if (ret) { 929 dev_err(dev, "failed to request firmware.\n"); 930 return ret; 931 } 932 933 rem = fw->size; 934 935 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */ 936 if (rem > 16384) { 937 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem); 938 release_firmware(fw); 939 return -ENOMEM; 940 } 941 942 for (page = 0; page < 10; page++) { 943 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 944 FSL_XCVR_EXT_CTRL_PAGE_MASK, 945 FSL_XCVR_EXT_CTRL_PAGE(page)); 946 if (ret < 0) { 947 dev_err(dev, "FW: failed to set page %d, err=%d\n", 948 page, ret); 949 goto err_firmware; 950 } 951 952 off = page * size; 953 out = min(rem, size); 954 /* IPG clock is assumed to be running, otherwise it will hang */ 955 if (out > 0) { 956 /* write firmware into code memory */ 957 memcpy_toio(xcvr->ram_addr, fw->data + off, out); 958 rem -= out; 959 if (rem == 0) { 960 /* last part of firmware written */ 961 /* clean remaining part of code memory page */ 962 memset_io(xcvr->ram_addr + out, 0, size - out); 963 } 964 } else { 965 /* clean current page, including data memory */ 966 memset_io(xcvr->ram_addr, 0, size); 967 } 968 } 969 970 err_firmware: 971 release_firmware(fw); 972 if (ret < 0) 973 return ret; 974 975 /* configure watermarks */ 976 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK; 977 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX); 978 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX); 979 /* disable DMA RD/WR */ 980 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 981 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 982 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 983 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK; 984 val |= FSL_XCVR_EXT_CTRL_PAGE(8); 985 986 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 987 if (ret < 0) { 988 dev_err(dev, "Failed to set watermarks: %d\n", ret); 989 return ret; 990 } 991 992 /* Store Capabilities Data Structure into Data RAM */ 993 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, 994 FSL_XCVR_CAPDS_SIZE); 995 return 0; 996 } 997 998 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol, 999 struct snd_ctl_elem_info *uinfo) 1000 { 1001 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1002 uinfo->count = 1; 1003 1004 return 0; 1005 } 1006 1007 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol, 1008 struct snd_ctl_elem_info *uinfo) 1009 { 1010 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1011 uinfo->count = sizeof_field(struct snd_aes_iec958, status); 1012 1013 return 0; 1014 } 1015 1016 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol, 1017 struct snd_ctl_elem_value *ucontrol) 1018 { 1019 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1020 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1021 1022 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); 1023 1024 return 0; 1025 } 1026 1027 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol, 1028 struct snd_ctl_elem_value *ucontrol) 1029 { 1030 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1031 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1032 1033 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); 1034 1035 return 0; 1036 } 1037 1038 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol, 1039 struct snd_ctl_elem_value *ucontrol) 1040 { 1041 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1042 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1043 1044 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); 1045 1046 return 0; 1047 } 1048 1049 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = { 1050 /* Channel status controller */ 1051 { 1052 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1053 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1054 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1055 .info = fsl_xcvr_type_iec958_info, 1056 .get = fsl_xcvr_rx_cs_get, 1057 }, 1058 /* Capture channel status, bytes */ 1059 { 1060 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1061 .name = "Capture Channel Status", 1062 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1063 .info = fsl_xcvr_type_iec958_bytes_info, 1064 .get = fsl_xcvr_rx_cs_get, 1065 }, 1066 }; 1067 1068 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = { 1069 /* Channel status controller */ 1070 { 1071 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1072 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1073 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1074 .info = fsl_xcvr_type_iec958_info, 1075 .get = fsl_xcvr_tx_cs_get, 1076 .put = fsl_xcvr_tx_cs_put, 1077 }, 1078 /* Playback channel status, bytes */ 1079 { 1080 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1081 .name = "Playback Channel Status", 1082 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1083 .info = fsl_xcvr_type_iec958_bytes_info, 1084 .get = fsl_xcvr_tx_cs_get, 1085 .put = fsl_xcvr_tx_cs_put, 1086 }, 1087 }; 1088 1089 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai) 1090 { 1091 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1092 1093 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); 1094 1095 if (xcvr->soc_data->spdif_only) 1096 xcvr->mode = FSL_XCVR_MODE_SPDIF; 1097 else { 1098 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1); 1099 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1); 1100 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1); 1101 } 1102 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls, 1103 ARRAY_SIZE(fsl_xcvr_tx_ctls)); 1104 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls, 1105 ARRAY_SIZE(fsl_xcvr_rx_ctls)); 1106 return 0; 1107 } 1108 1109 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = { 1110 .probe = fsl_xcvr_dai_probe, 1111 .prepare = fsl_xcvr_prepare, 1112 .startup = fsl_xcvr_startup, 1113 .shutdown = fsl_xcvr_shutdown, 1114 .trigger = fsl_xcvr_trigger, 1115 }; 1116 1117 static struct snd_soc_dai_driver fsl_xcvr_dai = { 1118 .ops = &fsl_xcvr_dai_ops, 1119 .playback = { 1120 .stream_name = "CPU-Playback", 1121 .channels_min = 1, 1122 .channels_max = 32, 1123 .rate_min = 32000, 1124 .rate_max = 1536000, 1125 .rates = SNDRV_PCM_RATE_KNOT, 1126 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1127 }, 1128 .capture = { 1129 .stream_name = "CPU-Capture", 1130 .channels_min = 1, 1131 .channels_max = 32, 1132 .rate_min = 32000, 1133 .rate_max = 1536000, 1134 .rates = SNDRV_PCM_RATE_KNOT, 1135 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1136 }, 1137 }; 1138 1139 static int fsl_xcvr_component_probe(struct snd_soc_component *component) 1140 { 1141 struct fsl_xcvr *xcvr = snd_soc_component_get_drvdata(component); 1142 1143 snd_soc_component_init_regmap(component, xcvr->regmap); 1144 1145 return 0; 1146 } 1147 1148 static const struct snd_soc_component_driver fsl_xcvr_comp = { 1149 .name = "fsl-xcvr-dai", 1150 .probe = fsl_xcvr_component_probe, 1151 .controls = fsl_xcvr_timestamp_ctrls, 1152 .num_controls = ARRAY_SIZE(fsl_xcvr_timestamp_ctrls), 1153 .legacy_dai_naming = 1, 1154 }; 1155 1156 static const struct reg_default fsl_xcvr_reg_defaults[] = { 1157 { FSL_XCVR_VERSION, 0x00000000 }, 1158 { FSL_XCVR_EXT_CTRL, 0xF8204040 }, 1159 { FSL_XCVR_EXT_STATUS, 0x00000000 }, 1160 { FSL_XCVR_EXT_IER0, 0x00000000 }, 1161 { FSL_XCVR_EXT_IER1, 0x00000000 }, 1162 { FSL_XCVR_EXT_ISR, 0x00000000 }, 1163 { FSL_XCVR_EXT_ISR_SET, 0x00000000 }, 1164 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 }, 1165 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 }, 1166 { FSL_XCVR_IER, 0x00000000 }, 1167 { FSL_XCVR_ISR, 0x00000000 }, 1168 { FSL_XCVR_ISR_SET, 0x00000000 }, 1169 { FSL_XCVR_ISR_CLR, 0x00000000 }, 1170 { FSL_XCVR_ISR_TOG, 0x00000000 }, 1171 { FSL_XCVR_CLK_CTRL, 0x0000018F }, 1172 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 }, 1173 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 }, 1174 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 }, 1175 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 }, 1176 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 }, 1177 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1178 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1179 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1180 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 }, 1181 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 }, 1182 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 }, 1183 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 }, 1184 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 }, 1185 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 }, 1186 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 }, 1187 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 }, 1188 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 }, 1189 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 }, 1190 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 }, 1191 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 }, 1192 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 }, 1193 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 }, 1194 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 }, 1195 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1196 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1197 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1198 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 }, 1199 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 }, 1200 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 }, 1201 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 }, 1202 { FSL_XCVR_DEBUG_REG_0, 0x00000000 }, 1203 { FSL_XCVR_DEBUG_REG_1, 0x00000000 }, 1204 }; 1205 1206 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) 1207 { 1208 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1209 1210 if (!xcvr->soc_data->use_phy) 1211 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) || 1212 reg > FSL_XCVR_TX_DPTH_BCRR) 1213 return false; 1214 switch (reg) { 1215 case FSL_XCVR_VERSION: 1216 case FSL_XCVR_EXT_CTRL: 1217 case FSL_XCVR_EXT_STATUS: 1218 case FSL_XCVR_EXT_IER0: 1219 case FSL_XCVR_EXT_IER1: 1220 case FSL_XCVR_EXT_ISR: 1221 case FSL_XCVR_EXT_ISR_SET: 1222 case FSL_XCVR_EXT_ISR_CLR: 1223 case FSL_XCVR_EXT_ISR_TOG: 1224 case FSL_XCVR_IER: 1225 case FSL_XCVR_ISR: 1226 case FSL_XCVR_ISR_SET: 1227 case FSL_XCVR_ISR_CLR: 1228 case FSL_XCVR_ISR_TOG: 1229 case FSL_XCVR_PHY_AI_CTRL: 1230 case FSL_XCVR_PHY_AI_CTRL_SET: 1231 case FSL_XCVR_PHY_AI_CTRL_CLR: 1232 case FSL_XCVR_PHY_AI_CTRL_TOG: 1233 case FSL_XCVR_PHY_AI_RDATA: 1234 case FSL_XCVR_CLK_CTRL: 1235 case FSL_XCVR_RX_DPTH_CTRL: 1236 case FSL_XCVR_RX_DPTH_CTRL_SET: 1237 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1238 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1239 case FSL_XCVR_RX_CS_DATA_0: 1240 case FSL_XCVR_RX_CS_DATA_1: 1241 case FSL_XCVR_RX_CS_DATA_2: 1242 case FSL_XCVR_RX_CS_DATA_3: 1243 case FSL_XCVR_RX_CS_DATA_4: 1244 case FSL_XCVR_RX_CS_DATA_5: 1245 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1246 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1247 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1248 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1249 case FSL_XCVR_RX_DPTH_TSCR: 1250 case FSL_XCVR_RX_DPTH_BCR: 1251 case FSL_XCVR_RX_DPTH_BCTR: 1252 case FSL_XCVR_RX_DPTH_BCRR: 1253 case FSL_XCVR_TX_DPTH_CTRL: 1254 case FSL_XCVR_TX_DPTH_CTRL_SET: 1255 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1256 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1257 case FSL_XCVR_TX_CS_DATA_0: 1258 case FSL_XCVR_TX_CS_DATA_1: 1259 case FSL_XCVR_TX_CS_DATA_2: 1260 case FSL_XCVR_TX_CS_DATA_3: 1261 case FSL_XCVR_TX_CS_DATA_4: 1262 case FSL_XCVR_TX_CS_DATA_5: 1263 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1264 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1265 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1266 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1267 case FSL_XCVR_TX_DPTH_TSCR: 1268 case FSL_XCVR_TX_DPTH_BCR: 1269 case FSL_XCVR_TX_DPTH_BCTR: 1270 case FSL_XCVR_TX_DPTH_BCRR: 1271 case FSL_XCVR_DEBUG_REG_0: 1272 case FSL_XCVR_DEBUG_REG_1: 1273 return true; 1274 default: 1275 return false; 1276 } 1277 } 1278 1279 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) 1280 { 1281 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1282 1283 if (!xcvr->soc_data->use_phy) 1284 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) 1285 return false; 1286 switch (reg) { 1287 case FSL_XCVR_EXT_CTRL: 1288 case FSL_XCVR_EXT_IER0: 1289 case FSL_XCVR_EXT_IER1: 1290 case FSL_XCVR_EXT_ISR: 1291 case FSL_XCVR_EXT_ISR_SET: 1292 case FSL_XCVR_EXT_ISR_CLR: 1293 case FSL_XCVR_EXT_ISR_TOG: 1294 case FSL_XCVR_IER: 1295 case FSL_XCVR_ISR_SET: 1296 case FSL_XCVR_ISR_CLR: 1297 case FSL_XCVR_ISR_TOG: 1298 case FSL_XCVR_PHY_AI_CTRL: 1299 case FSL_XCVR_PHY_AI_CTRL_SET: 1300 case FSL_XCVR_PHY_AI_CTRL_CLR: 1301 case FSL_XCVR_PHY_AI_CTRL_TOG: 1302 case FSL_XCVR_PHY_AI_WDATA: 1303 case FSL_XCVR_CLK_CTRL: 1304 case FSL_XCVR_RX_DPTH_CTRL: 1305 case FSL_XCVR_RX_DPTH_CTRL_SET: 1306 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1307 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1308 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1309 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1310 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1311 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1312 case FSL_XCVR_TX_DPTH_CTRL: 1313 case FSL_XCVR_TX_DPTH_CTRL_SET: 1314 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1315 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1316 case FSL_XCVR_TX_CS_DATA_0: 1317 case FSL_XCVR_TX_CS_DATA_1: 1318 case FSL_XCVR_TX_CS_DATA_2: 1319 case FSL_XCVR_TX_CS_DATA_3: 1320 case FSL_XCVR_TX_CS_DATA_4: 1321 case FSL_XCVR_TX_CS_DATA_5: 1322 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1323 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1324 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1325 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1326 return true; 1327 default: 1328 return false; 1329 } 1330 } 1331 1332 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) 1333 { 1334 switch (reg) { 1335 case FSL_XCVR_EXT_STATUS: 1336 case FSL_XCVR_EXT_ISR: 1337 case FSL_XCVR_EXT_ISR_SET: 1338 case FSL_XCVR_EXT_ISR_CLR: 1339 case FSL_XCVR_EXT_ISR_TOG: 1340 case FSL_XCVR_ISR: 1341 case FSL_XCVR_ISR_SET: 1342 case FSL_XCVR_ISR_CLR: 1343 case FSL_XCVR_ISR_TOG: 1344 case FSL_XCVR_PHY_AI_CTRL: 1345 case FSL_XCVR_PHY_AI_CTRL_SET: 1346 case FSL_XCVR_PHY_AI_CTRL_CLR: 1347 case FSL_XCVR_PHY_AI_CTRL_TOG: 1348 case FSL_XCVR_PHY_AI_RDATA: 1349 case FSL_XCVR_RX_CS_DATA_0: 1350 case FSL_XCVR_RX_CS_DATA_1: 1351 case FSL_XCVR_RX_CS_DATA_2: 1352 case FSL_XCVR_RX_CS_DATA_3: 1353 case FSL_XCVR_RX_CS_DATA_4: 1354 case FSL_XCVR_RX_CS_DATA_5: 1355 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1356 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1357 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1358 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1359 case FSL_XCVR_RX_DPTH_TSCR: 1360 case FSL_XCVR_RX_DPTH_BCR: 1361 case FSL_XCVR_RX_DPTH_BCTR: 1362 case FSL_XCVR_RX_DPTH_BCRR: 1363 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1364 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1365 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1366 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1367 case FSL_XCVR_TX_DPTH_TSCR: 1368 case FSL_XCVR_TX_DPTH_BCR: 1369 case FSL_XCVR_TX_DPTH_BCTR: 1370 case FSL_XCVR_TX_DPTH_BCRR: 1371 case FSL_XCVR_DEBUG_REG_0: 1372 case FSL_XCVR_DEBUG_REG_1: 1373 return true; 1374 default: 1375 return false; 1376 } 1377 } 1378 1379 static const struct regmap_config fsl_xcvr_regmap_cfg = { 1380 .reg_bits = 32, 1381 .reg_stride = 4, 1382 .val_bits = 32, 1383 .max_register = FSL_XCVR_MAX_REG, 1384 .reg_defaults = fsl_xcvr_reg_defaults, 1385 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults), 1386 .readable_reg = fsl_xcvr_readable_reg, 1387 .volatile_reg = fsl_xcvr_volatile_reg, 1388 .writeable_reg = fsl_xcvr_writeable_reg, 1389 .cache_type = REGCACHE_FLAT, 1390 }; 1391 1392 static const struct reg_default fsl_xcvr_phy_reg_defaults[] = { 1393 { FSL_XCVR_PHY_CTRL, 0x58200804 }, 1394 { FSL_XCVR_PHY_STATUS, 0x00000000 }, 1395 { FSL_XCVR_PHY_ANALOG_TRIM, 0x00260F13 }, 1396 { FSL_XCVR_PHY_SLEW_RATE_TRIM, 0x00000411 }, 1397 { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 }, 1398 { FSL_XCVR_PHY_TEST_CTRL, 0x00000000 }, 1399 { FSL_XCVR_PHY_DIFF_CDR_CTRL, 0x016D0009 }, 1400 { FSL_XCVR_PHY_CTRL2, 0x80000000 }, 1401 }; 1402 1403 static const struct regmap_config fsl_xcvr_regmap_phy_cfg = { 1404 .name = "phy", 1405 .reg_bits = 8, 1406 .reg_stride = 4, 1407 .val_bits = 32, 1408 .max_register = FSL_XCVR_PHY_CTRL2_TOG, 1409 .reg_defaults = fsl_xcvr_phy_reg_defaults, 1410 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults), 1411 .cache_type = REGCACHE_FLAT, 1412 .reg_read = fsl_xcvr_phy_reg_read, 1413 .reg_write = fsl_xcvr_phy_reg_write, 1414 }; 1415 1416 static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = { 1417 .name = "pllv0", 1418 .reg_bits = 8, 1419 .reg_stride = 4, 1420 .val_bits = 32, 1421 .max_register = FSL_XCVR_PLL_STAT0_TOG, 1422 .cache_type = REGCACHE_FLAT, 1423 .reg_read = fsl_xcvr_pll_reg_read, 1424 .reg_write = fsl_xcvr_pll_reg_write, 1425 }; 1426 1427 static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = { 1428 .name = "pllv1", 1429 .reg_bits = 8, 1430 .reg_stride = 4, 1431 .val_bits = 32, 1432 .max_register = FSL_XCVR_GP_PLL_STATUS_TOG, 1433 .cache_type = REGCACHE_FLAT, 1434 .reg_read = fsl_xcvr_pll_reg_read, 1435 .reg_write = fsl_xcvr_pll_reg_write, 1436 }; 1437 1438 static void reset_rx_work(struct work_struct *work) 1439 { 1440 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst); 1441 struct device *dev = &xcvr->pdev->dev; 1442 unsigned long lock_flags; 1443 u32 ext_ctrl; 1444 1445 dev_dbg(dev, "reset rx path\n"); 1446 spin_lock_irqsave(&xcvr->lock, lock_flags); 1447 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl); 1448 1449 if (!(ext_ctrl & FSL_XCVR_EXT_CTRL_DMA_RD_DIS)) { 1450 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1451 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1452 FSL_XCVR_EXT_CTRL_DMA_RD_DIS); 1453 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1454 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1455 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET); 1456 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1457 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1458 0); 1459 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1460 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1461 0); 1462 } 1463 spin_unlock_irqrestore(&xcvr->lock, lock_flags); 1464 } 1465 1466 static irqreturn_t irq0_isr(int irq, void *devid) 1467 { 1468 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; 1469 struct device *dev = &xcvr->pdev->dev; 1470 struct regmap *regmap = xcvr->regmap; 1471 void __iomem *reg_ctrl, *reg_buff; 1472 u32 isr, isr_clr = 0, val, i; 1473 1474 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr); 1475 1476 if (isr & FSL_XCVR_IRQ_NEW_CS) { 1477 dev_dbg(dev, "Received new CS block\n"); 1478 isr_clr |= FSL_XCVR_IRQ_NEW_CS; 1479 if (xcvr->soc_data->fw_name) { 1480 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 1481 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1482 FSL_XCVR_EXT_CTRL_PAGE_MASK, 1483 FSL_XCVR_EXT_CTRL_PAGE(8)); 1484 1485 /* Find updated CS buffer */ 1486 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; 1487 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; 1488 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1489 if (!val) { 1490 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; 1491 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; 1492 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1493 } 1494 1495 if (val) { 1496 /* copy CS buffer */ 1497 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, 1498 sizeof(xcvr->rx_iec958.status)); 1499 for (i = 0; i < 6; i++) { 1500 val = *(u32 *)(xcvr->rx_iec958.status + i*4); 1501 *(u32 *)(xcvr->rx_iec958.status + i*4) = 1502 bitrev32(val); 1503 } 1504 /* clear CS control register */ 1505 writel_relaxed(0, reg_ctrl); 1506 } 1507 } else { 1508 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0, 1509 (u32 *)&xcvr->rx_iec958.status[0]); 1510 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1, 1511 (u32 *)&xcvr->rx_iec958.status[4]); 1512 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2, 1513 (u32 *)&xcvr->rx_iec958.status[8]); 1514 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3, 1515 (u32 *)&xcvr->rx_iec958.status[12]); 1516 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4, 1517 (u32 *)&xcvr->rx_iec958.status[16]); 1518 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5, 1519 (u32 *)&xcvr->rx_iec958.status[20]); 1520 for (i = 0; i < 6; i++) { 1521 val = *(u32 *)(xcvr->rx_iec958.status + i * 4); 1522 *(u32 *)(xcvr->rx_iec958.status + i * 4) = 1523 bitrev32(val); 1524 } 1525 regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 1526 FSL_XCVR_RX_DPTH_CTRL_CSA); 1527 } 1528 } 1529 if (isr & FSL_XCVR_IRQ_NEW_UD) { 1530 dev_dbg(dev, "Received new UD block\n"); 1531 isr_clr |= FSL_XCVR_IRQ_NEW_UD; 1532 } 1533 if (isr & FSL_XCVR_IRQ_MUTE) { 1534 dev_dbg(dev, "HW mute bit detected\n"); 1535 isr_clr |= FSL_XCVR_IRQ_MUTE; 1536 } 1537 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) { 1538 dev_dbg(dev, "RX/TX FIFO full/empty\n"); 1539 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR; 1540 } 1541 if (isr & FSL_XCVR_IRQ_ARC_MODE) { 1542 dev_dbg(dev, "CMDC SM falls out of eARC mode\n"); 1543 isr_clr |= FSL_XCVR_IRQ_ARC_MODE; 1544 } 1545 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) { 1546 dev_dbg(dev, "DMA read request\n"); 1547 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ; 1548 } 1549 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) { 1550 dev_dbg(dev, "DMA write request\n"); 1551 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ; 1552 } 1553 if (isr & FSL_XCVR_IRQ_CMDC_STATUS_UPD) { 1554 dev_dbg(dev, "CMDC status update\n"); 1555 isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD; 1556 } 1557 if (isr & FSL_XCVR_IRQ_PREAMBLE_MISMATCH) { 1558 dev_dbg(dev, "Preamble mismatch\n"); 1559 isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH; 1560 } 1561 if (isr & FSL_XCVR_IRQ_UNEXP_PRE_REC) { 1562 dev_dbg(dev, "Unexpected preamble received\n"); 1563 isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC; 1564 } 1565 if (isr & FSL_XCVR_IRQ_M_W_PRE_MISMATCH) { 1566 dev_dbg(dev, "M/W preamble mismatch\n"); 1567 isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH; 1568 } 1569 if (isr & FSL_XCVR_IRQ_B_PRE_MISMATCH) { 1570 dev_dbg(dev, "B preamble mismatch\n"); 1571 isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH; 1572 } 1573 1574 if (isr & (FSL_XCVR_IRQ_PREAMBLE_MISMATCH | 1575 FSL_XCVR_IRQ_UNEXP_PRE_REC | 1576 FSL_XCVR_IRQ_M_W_PRE_MISMATCH | 1577 FSL_XCVR_IRQ_B_PRE_MISMATCH)) { 1578 schedule_work(&xcvr->work_rst); 1579 } 1580 1581 if (isr_clr) { 1582 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr); 1583 return IRQ_HANDLED; 1584 } 1585 1586 return IRQ_NONE; 1587 } 1588 1589 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = { 1590 .fw_name = "imx/xcvr/xcvr-imx8mp.bin", 1591 .use_phy = true, 1592 .pll_ver = PLL_MX8MP, 1593 }; 1594 1595 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = { 1596 .spdif_only = true, 1597 .use_edma = true, 1598 }; 1599 1600 static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = { 1601 .fw_name = "imx/xcvr/xcvr-imx95.bin", 1602 .spdif_only = true, 1603 .use_phy = true, 1604 .use_edma = true, 1605 .pll_ver = PLL_MX95, 1606 }; 1607 1608 static const struct of_device_id fsl_xcvr_dt_ids[] = { 1609 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data }, 1610 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data}, 1611 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data}, 1612 { /* sentinel */ } 1613 }; 1614 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids); 1615 1616 static int fsl_xcvr_probe(struct platform_device *pdev) 1617 { 1618 struct device *dev = &pdev->dev; 1619 struct fsl_xcvr *xcvr; 1620 struct resource *rx_res, *tx_res; 1621 void __iomem *regs; 1622 int ret, irq; 1623 1624 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); 1625 if (!xcvr) 1626 return -ENOMEM; 1627 1628 xcvr->pdev = pdev; 1629 xcvr->soc_data = of_device_get_match_data(&pdev->dev); 1630 1631 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); 1632 if (IS_ERR(xcvr->ipg_clk)) 1633 return dev_err_probe(dev, PTR_ERR(xcvr->ipg_clk), 1634 "failed to get ipg clock\n"); 1635 1636 xcvr->phy_clk = devm_clk_get(dev, "phy"); 1637 if (IS_ERR(xcvr->phy_clk)) 1638 return dev_err_probe(dev, PTR_ERR(xcvr->phy_clk), 1639 "failed to get phy clock\n"); 1640 1641 xcvr->spba_clk = devm_clk_get(dev, "spba"); 1642 if (IS_ERR(xcvr->spba_clk)) 1643 return dev_err_probe(dev, PTR_ERR(xcvr->spba_clk), 1644 "failed to get spba clock\n"); 1645 1646 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); 1647 if (IS_ERR(xcvr->pll_ipg_clk)) 1648 return dev_err_probe(dev, PTR_ERR(xcvr->pll_ipg_clk), 1649 "failed to get pll_ipg clock\n"); 1650 1651 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, 1652 &xcvr->pll11k_clk); 1653 1654 if (xcvr->soc_data->spdif_only) { 1655 if (!(xcvr->pll8k_clk || xcvr->pll11k_clk)) 1656 xcvr->pll8k_clk = xcvr->phy_clk; 1657 fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates, 1658 &fsl_xcvr_spdif_rates_constr, 1659 xcvr->pll8k_clk, xcvr->pll11k_clk, NULL, 1660 xcvr->spdif_constr_rates_list); 1661 } 1662 1663 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); 1664 if (IS_ERR(xcvr->ram_addr)) 1665 return PTR_ERR(xcvr->ram_addr); 1666 1667 regs = devm_platform_ioremap_resource_byname(pdev, "regs"); 1668 if (IS_ERR(regs)) 1669 return PTR_ERR(regs); 1670 1671 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, 1672 &fsl_xcvr_regmap_cfg); 1673 if (IS_ERR(xcvr->regmap)) 1674 return dev_err_probe(dev, PTR_ERR(xcvr->regmap), "failed to init XCVR regmap\n"); 1675 1676 if (xcvr->soc_data->use_phy) { 1677 xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr, 1678 &fsl_xcvr_regmap_phy_cfg); 1679 if (IS_ERR(xcvr->regmap_phy)) 1680 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_phy), 1681 "failed to init XCVR PHY regmap\n"); 1682 1683 switch (xcvr->soc_data->pll_ver) { 1684 case PLL_MX8MP: 1685 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1686 &fsl_xcvr_regmap_pllv0_cfg); 1687 if (IS_ERR(xcvr->regmap_pll)) 1688 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1689 "failed to init XCVR PLL regmap\n"); 1690 break; 1691 case PLL_MX95: 1692 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1693 &fsl_xcvr_regmap_pllv1_cfg); 1694 if (IS_ERR(xcvr->regmap_pll)) 1695 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1696 "failed to init XCVR PLL regmap\n"); 1697 break; 1698 default: 1699 return dev_err_probe(dev, -EINVAL, 1700 "Error for PLL version %d\n", 1701 xcvr->soc_data->pll_ver); 1702 } 1703 } 1704 1705 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 1706 if (IS_ERR(xcvr->reset)) 1707 return dev_err_probe(dev, PTR_ERR(xcvr->reset), 1708 "failed to get XCVR reset control\n"); 1709 1710 /* get IRQs */ 1711 irq = platform_get_irq(pdev, 0); 1712 if (irq < 0) 1713 return irq; 1714 1715 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); 1716 if (ret) 1717 return dev_err_probe(dev, ret, "failed to claim IRQ0\n"); 1718 1719 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo"); 1720 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo"); 1721 if (!rx_res || !tx_res) 1722 return dev_err_probe(dev, -EINVAL, "could not find rxfifo or txfifo resource\n"); 1723 xcvr->dma_prms_rx.chan_name = "rx"; 1724 xcvr->dma_prms_tx.chan_name = "tx"; 1725 xcvr->dma_prms_rx.addr = rx_res->start; 1726 xcvr->dma_prms_tx.addr = tx_res->start; 1727 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; 1728 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; 1729 1730 platform_set_drvdata(pdev, xcvr); 1731 pm_runtime_enable(dev); 1732 regcache_cache_only(xcvr->regmap, true); 1733 if (xcvr->soc_data->use_phy) { 1734 regcache_cache_only(xcvr->regmap_phy, true); 1735 regcache_cache_only(xcvr->regmap_pll, true); 1736 } 1737 1738 /* 1739 * Register platform component before registering cpu dai for there 1740 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1741 */ 1742 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1743 if (ret) { 1744 pm_runtime_disable(dev); 1745 return dev_err_probe(dev, ret, "failed to pcm register\n"); 1746 } 1747 1748 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp, 1749 &fsl_xcvr_dai, 1); 1750 if (ret) { 1751 pm_runtime_disable(dev); 1752 dev_err(dev, "failed to register component %s\n", 1753 fsl_xcvr_comp.name); 1754 } 1755 1756 INIT_WORK(&xcvr->work_rst, reset_rx_work); 1757 spin_lock_init(&xcvr->lock); 1758 return ret; 1759 } 1760 1761 static void fsl_xcvr_remove(struct platform_device *pdev) 1762 { 1763 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev); 1764 1765 cancel_work_sync(&xcvr->work_rst); 1766 pm_runtime_disable(&pdev->dev); 1767 } 1768 1769 static int fsl_xcvr_runtime_suspend(struct device *dev) 1770 { 1771 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1772 int ret; 1773 1774 if (!xcvr->soc_data->spdif_only && 1775 xcvr->mode == FSL_XCVR_MODE_EARC) { 1776 /* Assert M0+ reset */ 1777 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1778 FSL_XCVR_EXT_CTRL_CORE_RESET, 1779 FSL_XCVR_EXT_CTRL_CORE_RESET); 1780 if (ret < 0) 1781 dev_err(dev, "Failed to assert M0+ core: %d\n", ret); 1782 } 1783 1784 regcache_cache_only(xcvr->regmap, true); 1785 if (xcvr->soc_data->use_phy) { 1786 regcache_cache_only(xcvr->regmap_phy, true); 1787 regcache_cache_only(xcvr->regmap_pll, true); 1788 } 1789 1790 clk_disable_unprepare(xcvr->spba_clk); 1791 clk_disable_unprepare(xcvr->phy_clk); 1792 clk_disable_unprepare(xcvr->pll_ipg_clk); 1793 clk_disable_unprepare(xcvr->ipg_clk); 1794 1795 return 0; 1796 } 1797 1798 static int fsl_xcvr_runtime_resume(struct device *dev) 1799 { 1800 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1801 int ret; 1802 1803 ret = reset_control_assert(xcvr->reset); 1804 if (ret < 0) { 1805 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); 1806 return ret; 1807 } 1808 1809 ret = clk_prepare_enable(xcvr->ipg_clk); 1810 if (ret) { 1811 dev_err(dev, "failed to start IPG clock.\n"); 1812 return ret; 1813 } 1814 1815 ret = clk_prepare_enable(xcvr->pll_ipg_clk); 1816 if (ret) { 1817 dev_err(dev, "failed to start PLL IPG clock.\n"); 1818 goto stop_ipg_clk; 1819 } 1820 1821 ret = clk_prepare_enable(xcvr->phy_clk); 1822 if (ret) { 1823 dev_err(dev, "failed to start PHY clock: %d\n", ret); 1824 goto stop_pll_ipg_clk; 1825 } 1826 1827 ret = clk_prepare_enable(xcvr->spba_clk); 1828 if (ret) { 1829 dev_err(dev, "failed to start SPBA clock.\n"); 1830 goto stop_phy_clk; 1831 } 1832 1833 ret = reset_control_deassert(xcvr->reset); 1834 if (ret) { 1835 dev_err(dev, "failed to deassert M0+ reset.\n"); 1836 goto stop_spba_clk; 1837 } 1838 1839 regcache_cache_only(xcvr->regmap, false); 1840 regcache_mark_dirty(xcvr->regmap); 1841 ret = regcache_sync(xcvr->regmap); 1842 1843 if (ret) { 1844 dev_err(dev, "failed to sync regcache.\n"); 1845 goto stop_spba_clk; 1846 } 1847 1848 if (xcvr->soc_data->use_phy) { 1849 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 1850 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 1851 if (ret < 0) { 1852 dev_err(dev, "Error while release PHY reset: %d\n", ret); 1853 goto stop_spba_clk; 1854 } 1855 1856 regcache_cache_only(xcvr->regmap_phy, false); 1857 regcache_mark_dirty(xcvr->regmap_phy); 1858 ret = regcache_sync(xcvr->regmap_phy); 1859 if (ret) { 1860 dev_err(dev, "failed to sync phy regcache.\n"); 1861 goto stop_spba_clk; 1862 } 1863 1864 regcache_cache_only(xcvr->regmap_pll, false); 1865 regcache_mark_dirty(xcvr->regmap_pll); 1866 ret = regcache_sync(xcvr->regmap_pll); 1867 if (ret) { 1868 dev_err(dev, "failed to sync pll regcache.\n"); 1869 goto stop_spba_clk; 1870 } 1871 } 1872 1873 if (xcvr->soc_data->fw_name) { 1874 ret = fsl_xcvr_load_firmware(xcvr); 1875 if (ret) { 1876 dev_err(dev, "failed to load firmware.\n"); 1877 goto stop_spba_clk; 1878 } 1879 1880 /* Release M0+ reset */ 1881 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1882 FSL_XCVR_EXT_CTRL_CORE_RESET, 0); 1883 if (ret < 0) { 1884 dev_err(dev, "M0+ core release failed: %d\n", ret); 1885 goto stop_spba_clk; 1886 } 1887 1888 /* Let M0+ core complete firmware initialization */ 1889 msleep(50); 1890 } 1891 1892 return 0; 1893 1894 stop_spba_clk: 1895 clk_disable_unprepare(xcvr->spba_clk); 1896 stop_phy_clk: 1897 clk_disable_unprepare(xcvr->phy_clk); 1898 stop_pll_ipg_clk: 1899 clk_disable_unprepare(xcvr->pll_ipg_clk); 1900 stop_ipg_clk: 1901 clk_disable_unprepare(xcvr->ipg_clk); 1902 1903 return ret; 1904 } 1905 1906 static const struct dev_pm_ops fsl_xcvr_pm_ops = { 1907 RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, fsl_xcvr_runtime_resume, NULL) 1908 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1909 }; 1910 1911 static struct platform_driver fsl_xcvr_driver = { 1912 .probe = fsl_xcvr_probe, 1913 .driver = { 1914 .name = "fsl-xcvr", 1915 .pm = pm_ptr(&fsl_xcvr_pm_ops), 1916 .of_match_table = fsl_xcvr_dt_ids, 1917 }, 1918 .remove = fsl_xcvr_remove, 1919 }; 1920 module_platform_driver(fsl_xcvr_driver); 1921 1922 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>"); 1923 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver"); 1924 MODULE_LICENSE("GPL v2"); 1925