1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v12_0_ppsmc.h"
29 #include "smu12_driver_if.h"
30 #include "smu_v12_0.h"
31 #include "renoir_ppt.h"
32 #include "smu_cmn.h"
33
34 /*
35 * DO NOT use these for err/warn/info/debug messages.
36 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
37 * They are more MGPU friendly.
38 */
39 #undef pr_err
40 #undef pr_warn
41 #undef pr_info
42 #undef pr_debug
43
44 #define mmMP1_SMN_C2PMSG_66 0x0282
45 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
46
47 #define mmMP1_SMN_C2PMSG_82 0x0292
48 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
49
50 #define mmMP1_SMN_C2PMSG_90 0x029a
51 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
52
53 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
54 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
55 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
56 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
57 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1),
58 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
59 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
60 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
61 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
62 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
63 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
64 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1),
65 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1),
66 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1),
67 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
68 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
69 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
70 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
71 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
72 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
73 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
74 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1),
75 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
76 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
77 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
78 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
79 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
80 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1),
81 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1),
82 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
83 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1),
84 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
85 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1),
86 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1),
87 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1),
88 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1),
89 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
90 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
91 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
92 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
93 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1),
94 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1),
95 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1),
96 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1),
97 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
98 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
99 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
100 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
101 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
102 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1),
103 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1),
104 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
105 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
106 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1),
107 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
110 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1),
111 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1),
112 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
113 };
114
115 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
116 CLK_MAP(GFXCLK, CLOCK_GFXCLK),
117 CLK_MAP(SCLK, CLOCK_GFXCLK),
118 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
119 CLK_MAP(UCLK, CLOCK_FCLK),
120 CLK_MAP(MCLK, CLOCK_FCLK),
121 CLK_MAP(VCLK, CLOCK_VCLK),
122 CLK_MAP(DCLK, CLOCK_DCLK),
123 };
124
125 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
126 TAB_MAP_VALID(WATERMARKS),
127 TAB_MAP_INVALID(CUSTOM_DPM),
128 TAB_MAP_VALID(DPMCLOCKS),
129 TAB_MAP_VALID(SMU_METRICS),
130 };
131
132 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
133 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
134 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
135 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
136 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
137 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
138 };
139
140 static const uint8_t renoir_throttler_map[] = {
141 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
142 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
143 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
144 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
145 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
146 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
147 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
148 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
149 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
150 [THROTTLER_STATUS_BIT_PROCHOT_CPU] = (SMU_THROTTLER_PROCHOT_CPU_BIT),
151 [THROTTLER_STATUS_BIT_PROCHOT_GFX] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
152 [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT),
153 [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT),
154 };
155
renoir_init_smc_tables(struct smu_context * smu)156 static int renoir_init_smc_tables(struct smu_context *smu)
157 {
158 struct smu_table_context *smu_table = &smu->smu_table;
159 struct smu_table *tables = smu_table->tables;
160
161 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
162 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
163 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
164 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
165 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
166 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
167
168 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
169 if (!smu_table->clocks_table)
170 goto err0_out;
171
172 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
173 if (!smu_table->metrics_table)
174 goto err1_out;
175 smu_table->metrics_time = 0;
176
177 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
178 if (!smu_table->watermarks_table)
179 goto err2_out;
180
181 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
182 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
183 if (!smu_table->gpu_metrics_table)
184 goto err3_out;
185
186 return 0;
187
188 err3_out:
189 kfree(smu_table->watermarks_table);
190 err2_out:
191 kfree(smu_table->metrics_table);
192 err1_out:
193 kfree(smu_table->clocks_table);
194 err0_out:
195 return -ENOMEM;
196 }
197
198 /*
199 * This interface just for getting uclk ultimate freq and should't introduce
200 * other likewise function result in overmuch callback.
201 */
renoir_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)202 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
203 uint32_t dpm_level, uint32_t *freq)
204 {
205 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
206
207 if (!clk_table || clk_type >= SMU_CLK_COUNT)
208 return -EINVAL;
209
210 switch (clk_type) {
211 case SMU_SOCCLK:
212 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
213 return -EINVAL;
214 *freq = clk_table->SocClocks[dpm_level].Freq;
215 break;
216 case SMU_UCLK:
217 case SMU_MCLK:
218 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
219 return -EINVAL;
220 *freq = clk_table->FClocks[dpm_level].Freq;
221 break;
222 case SMU_DCEFCLK:
223 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
224 return -EINVAL;
225 *freq = clk_table->DcfClocks[dpm_level].Freq;
226 break;
227 case SMU_FCLK:
228 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
229 return -EINVAL;
230 *freq = clk_table->FClocks[dpm_level].Freq;
231 break;
232 case SMU_VCLK:
233 if (dpm_level >= NUM_VCN_DPM_LEVELS)
234 return -EINVAL;
235 *freq = clk_table->VClocks[dpm_level].Freq;
236 break;
237 case SMU_DCLK:
238 if (dpm_level >= NUM_VCN_DPM_LEVELS)
239 return -EINVAL;
240 *freq = clk_table->DClocks[dpm_level].Freq;
241 break;
242
243 default:
244 return -EINVAL;
245 }
246
247 return 0;
248 }
249
renoir_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)250 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
251 enum amd_dpm_forced_level level,
252 uint32_t *sclk_mask,
253 uint32_t *mclk_mask,
254 uint32_t *soc_mask)
255 {
256
257 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
258 if (sclk_mask)
259 *sclk_mask = 0;
260 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
261 if (mclk_mask)
262 /* mclk levels are in reverse order */
263 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
264 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
265 if (sclk_mask)
266 /* The sclk as gfxclk and has three level about max/min/current */
267 *sclk_mask = 3 - 1;
268
269 if (mclk_mask)
270 /* mclk levels are in reverse order */
271 *mclk_mask = 0;
272
273 if (soc_mask)
274 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
275 }
276
277 return 0;
278 }
279
renoir_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)280 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
281 enum smu_clk_type clk_type,
282 uint32_t *min,
283 uint32_t *max)
284 {
285 int ret = 0;
286 uint32_t mclk_mask, soc_mask;
287 uint32_t clock_limit;
288
289 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
290 switch (clk_type) {
291 case SMU_MCLK:
292 case SMU_UCLK:
293 clock_limit = smu->smu_table.boot_values.uclk;
294 break;
295 case SMU_GFXCLK:
296 case SMU_SCLK:
297 clock_limit = smu->smu_table.boot_values.gfxclk;
298 break;
299 case SMU_SOCCLK:
300 clock_limit = smu->smu_table.boot_values.socclk;
301 break;
302 default:
303 clock_limit = 0;
304 break;
305 }
306
307 /* clock in Mhz unit */
308 if (min)
309 *min = clock_limit / 100;
310 if (max)
311 *max = clock_limit / 100;
312
313 return 0;
314 }
315
316 if (max) {
317 ret = renoir_get_profiling_clk_mask(smu,
318 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
319 NULL,
320 &mclk_mask,
321 &soc_mask);
322 if (ret)
323 goto failed;
324
325 switch (clk_type) {
326 case SMU_GFXCLK:
327 case SMU_SCLK:
328 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
329 if (ret) {
330 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
331 goto failed;
332 }
333 break;
334 case SMU_UCLK:
335 case SMU_FCLK:
336 case SMU_MCLK:
337 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
338 if (ret)
339 goto failed;
340 break;
341 case SMU_SOCCLK:
342 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
343 if (ret)
344 goto failed;
345 break;
346 default:
347 ret = -EINVAL;
348 goto failed;
349 }
350 }
351
352 if (min) {
353 switch (clk_type) {
354 case SMU_GFXCLK:
355 case SMU_SCLK:
356 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
357 if (ret) {
358 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
359 goto failed;
360 }
361 break;
362 case SMU_UCLK:
363 case SMU_FCLK:
364 case SMU_MCLK:
365 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
366 if (ret)
367 goto failed;
368 break;
369 case SMU_SOCCLK:
370 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
371 if (ret)
372 goto failed;
373 break;
374 default:
375 ret = -EINVAL;
376 goto failed;
377 }
378 }
379 failed:
380 return ret;
381 }
382
renoir_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)383 static int renoir_od_edit_dpm_table(struct smu_context *smu,
384 enum PP_OD_DPM_TABLE_COMMAND type,
385 long input[], uint32_t size)
386 {
387 int ret = 0;
388 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
389
390 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
391 dev_warn(smu->adev->dev,
392 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
393 return -EINVAL;
394 }
395
396 switch (type) {
397 case PP_OD_EDIT_SCLK_VDDC_TABLE:
398 if (size != 2) {
399 dev_err(smu->adev->dev, "Input parameter number not correct\n");
400 return -EINVAL;
401 }
402
403 if (input[0] == 0) {
404 if (input[1] < smu->gfx_default_hard_min_freq) {
405 dev_warn(smu->adev->dev,
406 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
407 input[1], smu->gfx_default_hard_min_freq);
408 return -EINVAL;
409 }
410 smu->gfx_actual_hard_min_freq = input[1];
411 } else if (input[0] == 1) {
412 if (input[1] > smu->gfx_default_soft_max_freq) {
413 dev_warn(smu->adev->dev,
414 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
415 input[1], smu->gfx_default_soft_max_freq);
416 return -EINVAL;
417 }
418 smu->gfx_actual_soft_max_freq = input[1];
419 } else {
420 return -EINVAL;
421 }
422 break;
423 case PP_OD_RESTORE_DEFAULT_TABLE:
424 if (size != 0) {
425 dev_err(smu->adev->dev, "Input parameter number not correct\n");
426 return -EINVAL;
427 }
428 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
429 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
430 break;
431 case PP_OD_COMMIT_DPM_TABLE:
432 if (size != 0) {
433 dev_err(smu->adev->dev, "Input parameter number not correct\n");
434 return -EINVAL;
435 } else {
436 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
437 dev_err(smu->adev->dev,
438 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
439 smu->gfx_actual_hard_min_freq,
440 smu->gfx_actual_soft_max_freq);
441 return -EINVAL;
442 }
443
444 ret = smu_cmn_send_smc_msg_with_param(smu,
445 SMU_MSG_SetHardMinGfxClk,
446 smu->gfx_actual_hard_min_freq,
447 NULL);
448 if (ret) {
449 dev_err(smu->adev->dev, "Set hard min sclk failed!");
450 return ret;
451 }
452
453 ret = smu_cmn_send_smc_msg_with_param(smu,
454 SMU_MSG_SetSoftMaxGfxClk,
455 smu->gfx_actual_soft_max_freq,
456 NULL);
457 if (ret) {
458 dev_err(smu->adev->dev, "Set soft max sclk failed!");
459 return ret;
460 }
461 }
462 break;
463 default:
464 return -ENOSYS;
465 }
466
467 return ret;
468 }
469
renoir_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)470 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
471 {
472 uint32_t min = 0, max = 0;
473 uint32_t ret = 0;
474
475 ret = smu_cmn_send_smc_msg_with_param(smu,
476 SMU_MSG_GetMinGfxclkFrequency,
477 0, &min);
478 if (ret)
479 return ret;
480 ret = smu_cmn_send_smc_msg_with_param(smu,
481 SMU_MSG_GetMaxGfxclkFrequency,
482 0, &max);
483 if (ret)
484 return ret;
485
486 smu->gfx_default_hard_min_freq = min;
487 smu->gfx_default_soft_max_freq = max;
488 smu->gfx_actual_hard_min_freq = 0;
489 smu->gfx_actual_soft_max_freq = 0;
490
491 return 0;
492 }
493
renoir_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)494 static int renoir_print_clk_levels(struct smu_context *smu,
495 enum smu_clk_type clk_type, char *buf)
496 {
497 int i, idx, size = 0, ret = 0;
498 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
499 SmuMetrics_t metrics;
500 bool cur_value_match_level = false;
501
502 memset(&metrics, 0, sizeof(metrics));
503
504 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
505 if (ret)
506 return ret;
507
508 smu_cmn_get_sysfs_buf(&buf, &size);
509
510 switch (clk_type) {
511 case SMU_OD_RANGE:
512 ret = smu_cmn_send_smc_msg_with_param(smu,
513 SMU_MSG_GetMinGfxclkFrequency,
514 0, &min);
515 if (ret)
516 return ret;
517 ret = smu_cmn_send_smc_msg_with_param(smu,
518 SMU_MSG_GetMaxGfxclkFrequency,
519 0, &max);
520 if (ret)
521 return ret;
522 size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max);
523 break;
524 case SMU_OD_SCLK:
525 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
526 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
527 size += sysfs_emit_at(buf, size, "OD_SCLK\n");
528 size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min);
529 size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max);
530 break;
531 case SMU_GFXCLK:
532 case SMU_SCLK:
533 /* retirve table returned paramters unit is MHz */
534 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
535 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
536 if (!ret) {
537 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
538 if (cur_value == max)
539 i = 2;
540 else if (cur_value == min)
541 i = 0;
542 else
543 i = 1;
544
545 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
546 i == 0 ? "*" : "");
547 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
548 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
549 i == 1 ? "*" : "");
550 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
551 i == 2 ? "*" : "");
552 }
553 return size;
554 case SMU_SOCCLK:
555 count = NUM_SOCCLK_DPM_LEVELS;
556 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
557 break;
558 case SMU_MCLK:
559 count = NUM_MEMCLK_DPM_LEVELS;
560 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
561 break;
562 case SMU_DCEFCLK:
563 count = NUM_DCFCLK_DPM_LEVELS;
564 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
565 break;
566 case SMU_FCLK:
567 count = NUM_FCLK_DPM_LEVELS;
568 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
569 break;
570 case SMU_VCLK:
571 count = NUM_VCN_DPM_LEVELS;
572 cur_value = metrics.ClockFrequency[CLOCK_VCLK];
573 break;
574 case SMU_DCLK:
575 count = NUM_VCN_DPM_LEVELS;
576 cur_value = metrics.ClockFrequency[CLOCK_DCLK];
577 break;
578 default:
579 break;
580 }
581
582 switch (clk_type) {
583 case SMU_SOCCLK:
584 case SMU_MCLK:
585 case SMU_DCEFCLK:
586 case SMU_FCLK:
587 case SMU_VCLK:
588 case SMU_DCLK:
589 for (i = 0; i < count; i++) {
590 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
591 ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value);
592 if (ret)
593 return ret;
594 if (!value)
595 continue;
596 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
597 cur_value == value ? "*" : "");
598 if (cur_value == value)
599 cur_value_match_level = true;
600 }
601
602 if (!cur_value_match_level)
603 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
604
605 break;
606 default:
607 break;
608 }
609
610 return size;
611 }
612
renoir_get_current_power_state(struct smu_context * smu)613 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
614 {
615 enum amd_pm_state_type pm_type;
616 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
617
618 if (!smu_dpm_ctx->dpm_context ||
619 !smu_dpm_ctx->dpm_current_power_state)
620 return -EINVAL;
621
622 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
623 case SMU_STATE_UI_LABEL_BATTERY:
624 pm_type = POWER_STATE_TYPE_BATTERY;
625 break;
626 case SMU_STATE_UI_LABEL_BALLANCED:
627 pm_type = POWER_STATE_TYPE_BALANCED;
628 break;
629 case SMU_STATE_UI_LABEL_PERFORMANCE:
630 pm_type = POWER_STATE_TYPE_PERFORMANCE;
631 break;
632 default:
633 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
634 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
635 else
636 pm_type = POWER_STATE_TYPE_DEFAULT;
637 break;
638 }
639
640 return pm_type;
641 }
642
renoir_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)643 static int renoir_dpm_set_vcn_enable(struct smu_context *smu,
644 bool enable,
645 int inst)
646 {
647 int ret = 0;
648
649 if (enable) {
650 /* vcn dpm on is a prerequisite for vcn power gate messages */
651 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
652 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
653 if (ret)
654 return ret;
655 }
656 } else {
657 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
658 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
659 if (ret)
660 return ret;
661 }
662 }
663
664 return ret;
665 }
666
renoir_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)667 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
668 {
669 int ret = 0;
670
671 if (enable) {
672 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
673 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
674 if (ret)
675 return ret;
676 }
677 } else {
678 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
679 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
680 if (ret)
681 return ret;
682 }
683 }
684
685 return ret;
686 }
687
renoir_force_dpm_limit_value(struct smu_context * smu,bool highest)688 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
689 {
690 int ret = 0, i = 0;
691 uint32_t min_freq, max_freq, force_freq;
692 enum smu_clk_type clk_type;
693
694 enum smu_clk_type clks[] = {
695 SMU_GFXCLK,
696 SMU_MCLK,
697 SMU_SOCCLK,
698 };
699
700 for (i = 0; i < ARRAY_SIZE(clks); i++) {
701 clk_type = clks[i];
702 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
703 if (ret)
704 return ret;
705
706 force_freq = highest ? max_freq : min_freq;
707 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);
708 if (ret)
709 return ret;
710 }
711
712 return ret;
713 }
714
renoir_unforce_dpm_levels(struct smu_context * smu)715 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
716
717 int ret = 0, i = 0;
718 uint32_t min_freq, max_freq;
719 enum smu_clk_type clk_type;
720
721 struct clk_feature_map {
722 enum smu_clk_type clk_type;
723 uint32_t feature;
724 } clk_feature_map[] = {
725 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
726 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
727 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
728 };
729
730 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
731 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
732 continue;
733
734 clk_type = clk_feature_map[i].clk_type;
735
736 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
737 if (ret)
738 return ret;
739
740 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
741 if (ret)
742 return ret;
743 }
744
745 return ret;
746 }
747
748 /*
749 * This interface get dpm clock table for dc
750 */
renoir_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)751 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
752 {
753 DpmClocks_t *table = smu->smu_table.clocks_table;
754 int i;
755
756 if (!clock_table || !table)
757 return -EINVAL;
758
759 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
760 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
761 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
762 }
763
764 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
765 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
766 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
767 }
768
769 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
770 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
771 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
772 }
773
774 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
775 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
776 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
777 }
778
779 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
780 clock_table->VClocks[i].Freq = table->VClocks[i].Freq;
781 clock_table->VClocks[i].Vol = table->VClocks[i].Vol;
782 }
783
784 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
785 clock_table->DClocks[i].Freq = table->DClocks[i].Freq;
786 clock_table->DClocks[i].Vol = table->DClocks[i].Vol;
787 }
788
789 return 0;
790 }
791
renoir_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)792 static int renoir_force_clk_levels(struct smu_context *smu,
793 enum smu_clk_type clk_type, uint32_t mask)
794 {
795
796 int ret = 0 ;
797 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
798
799 soft_min_level = mask ? (ffs(mask) - 1) : 0;
800 soft_max_level = mask ? (fls(mask) - 1) : 0;
801
802 switch (clk_type) {
803 case SMU_GFXCLK:
804 case SMU_SCLK:
805 if (soft_min_level > 2 || soft_max_level > 2) {
806 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
807 return -EINVAL;
808 }
809
810 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
811 if (ret)
812 return ret;
813 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
814 soft_max_level == 0 ? min_freq :
815 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
816 NULL);
817 if (ret)
818 return ret;
819 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
820 soft_min_level == 2 ? max_freq :
821 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
822 NULL);
823 if (ret)
824 return ret;
825 break;
826 case SMU_SOCCLK:
827 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
828 if (ret)
829 return ret;
830 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
831 if (ret)
832 return ret;
833 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
834 if (ret)
835 return ret;
836 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
837 if (ret)
838 return ret;
839 break;
840 case SMU_MCLK:
841 case SMU_FCLK:
842 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
843 if (ret)
844 return ret;
845 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
846 if (ret)
847 return ret;
848 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
849 if (ret)
850 return ret;
851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
852 if (ret)
853 return ret;
854 break;
855 default:
856 break;
857 }
858
859 return ret;
860 }
861
renoir_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)862 static int renoir_set_power_profile_mode(struct smu_context *smu,
863 u32 workload_mask,
864 long *custom_params,
865 u32 custom_params_max_idx)
866 {
867 int ret;
868 u32 backend_workload_mask = 0;
869
870 smu_cmn_get_backend_workload_mask(smu, workload_mask,
871 &backend_workload_mask);
872
873 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
874 backend_workload_mask,
875 NULL);
876 if (ret) {
877 dev_err_once(smu->adev->dev, "Failed to set workload mask 0x08%x\n",
878 workload_mask);
879 return ret;
880 }
881
882 return ret;
883 }
884
renoir_set_peak_clock_by_device(struct smu_context * smu)885 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
886 {
887 int ret = 0;
888 uint32_t sclk_freq = 0, uclk_freq = 0;
889
890 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
891 if (ret)
892 return ret;
893
894 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
895 if (ret)
896 return ret;
897
898 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
899 if (ret)
900 return ret;
901
902 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
903 if (ret)
904 return ret;
905
906 return ret;
907 }
908
renior_set_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type)909 static int renior_set_dpm_profile_freq(struct smu_context *smu,
910 enum amd_dpm_forced_level level,
911 enum smu_clk_type clk_type)
912 {
913 int ret = 0;
914 uint32_t sclk = 0, socclk = 0, fclk = 0;
915
916 switch (clk_type) {
917 case SMU_GFXCLK:
918 case SMU_SCLK:
919 sclk = RENOIR_UMD_PSTATE_GFXCLK;
920 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
921 renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk);
922 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
923 renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk, NULL);
924 break;
925 case SMU_SOCCLK:
926 socclk = RENOIR_UMD_PSTATE_SOCCLK;
927 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
928 renoir_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk);
929 break;
930 case SMU_FCLK:
931 case SMU_MCLK:
932 fclk = RENOIR_UMD_PSTATE_FCLK;
933 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
934 renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk);
935 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
936 renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk, NULL);
937 break;
938 default:
939 ret = -EINVAL;
940 break;
941 }
942
943 if (sclk)
944 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk, sclk, false);
945
946 if (socclk)
947 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk, socclk, false);
948
949 if (fclk)
950 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_FCLK, fclk, fclk, false);
951
952 return ret;
953 }
954
renoir_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)955 static int renoir_set_performance_level(struct smu_context *smu,
956 enum amd_dpm_forced_level level)
957 {
958 int ret = 0;
959
960 switch (level) {
961 case AMD_DPM_FORCED_LEVEL_HIGH:
962 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
963 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
964
965 ret = renoir_force_dpm_limit_value(smu, true);
966 break;
967 case AMD_DPM_FORCED_LEVEL_LOW:
968 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
969 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
970
971 ret = renoir_force_dpm_limit_value(smu, false);
972 break;
973 case AMD_DPM_FORCED_LEVEL_AUTO:
974 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
975 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
976
977 ret = renoir_unforce_dpm_levels(smu);
978 break;
979 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
980 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
981 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
982
983 ret = smu_cmn_send_smc_msg_with_param(smu,
984 SMU_MSG_SetHardMinGfxClk,
985 RENOIR_UMD_PSTATE_GFXCLK,
986 NULL);
987 if (ret)
988 return ret;
989 ret = smu_cmn_send_smc_msg_with_param(smu,
990 SMU_MSG_SetHardMinFclkByFreq,
991 RENOIR_UMD_PSTATE_FCLK,
992 NULL);
993 if (ret)
994 return ret;
995 ret = smu_cmn_send_smc_msg_with_param(smu,
996 SMU_MSG_SetHardMinSocclkByFreq,
997 RENOIR_UMD_PSTATE_SOCCLK,
998 NULL);
999 if (ret)
1000 return ret;
1001 ret = smu_cmn_send_smc_msg_with_param(smu,
1002 SMU_MSG_SetHardMinVcn,
1003 RENOIR_UMD_PSTATE_VCNCLK,
1004 NULL);
1005 if (ret)
1006 return ret;
1007
1008 ret = smu_cmn_send_smc_msg_with_param(smu,
1009 SMU_MSG_SetSoftMaxGfxClk,
1010 RENOIR_UMD_PSTATE_GFXCLK,
1011 NULL);
1012 if (ret)
1013 return ret;
1014 ret = smu_cmn_send_smc_msg_with_param(smu,
1015 SMU_MSG_SetSoftMaxFclkByFreq,
1016 RENOIR_UMD_PSTATE_FCLK,
1017 NULL);
1018 if (ret)
1019 return ret;
1020 ret = smu_cmn_send_smc_msg_with_param(smu,
1021 SMU_MSG_SetSoftMaxSocclkByFreq,
1022 RENOIR_UMD_PSTATE_SOCCLK,
1023 NULL);
1024 if (ret)
1025 return ret;
1026 ret = smu_cmn_send_smc_msg_with_param(smu,
1027 SMU_MSG_SetSoftMaxVcn,
1028 RENOIR_UMD_PSTATE_VCNCLK,
1029 NULL);
1030 if (ret)
1031 return ret;
1032 break;
1033 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1034 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1035 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1036 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1037
1038 renior_set_dpm_profile_freq(smu, level, SMU_SCLK);
1039 renior_set_dpm_profile_freq(smu, level, SMU_MCLK);
1040 renior_set_dpm_profile_freq(smu, level, SMU_SOCCLK);
1041 break;
1042 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1043 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1044 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1045
1046 ret = renoir_set_peak_clock_by_device(smu);
1047 break;
1048 case AMD_DPM_FORCED_LEVEL_MANUAL:
1049 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1050 default:
1051 break;
1052 }
1053 return ret;
1054 }
1055
1056 /* save watermark settings into pplib smu structure,
1057 * also pass data to smu controller
1058 */
renoir_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1059 static int renoir_set_watermarks_table(
1060 struct smu_context *smu,
1061 struct pp_smu_wm_range_sets *clock_ranges)
1062 {
1063 Watermarks_t *table = smu->smu_table.watermarks_table;
1064 int ret = 0;
1065 int i;
1066
1067 if (clock_ranges) {
1068 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1069 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1070 return -EINVAL;
1071
1072 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
1073 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1074 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1075 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1076 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1077 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1078 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1079 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1080 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1081 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1082
1083 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1084 clock_ranges->reader_wm_sets[i].wm_inst;
1085 table->WatermarkRow[WM_DCFCLK][i].WmType =
1086 clock_ranges->reader_wm_sets[i].wm_type;
1087 }
1088
1089 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1090 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1091 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1092 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1093 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1094 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1095 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1096 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1097 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1098
1099 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1100 clock_ranges->writer_wm_sets[i].wm_inst;
1101 table->WatermarkRow[WM_SOCCLK][i].WmType =
1102 clock_ranges->writer_wm_sets[i].wm_type;
1103 }
1104
1105 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1106 }
1107
1108 /* pass data to smu controller */
1109 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1110 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1111 ret = smu_cmn_write_watermarks_table(smu);
1112 if (ret) {
1113 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1114 return ret;
1115 }
1116 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1117 }
1118
1119 return 0;
1120 }
1121
renoir_get_power_profile_mode(struct smu_context * smu,char * buf)1122 static int renoir_get_power_profile_mode(struct smu_context *smu,
1123 char *buf)
1124 {
1125 uint32_t i, size = 0;
1126 int16_t workload_type = 0;
1127
1128 if (!buf)
1129 return -EINVAL;
1130
1131 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1132 /*
1133 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1134 * Not all profile modes are supported on arcturus.
1135 */
1136 workload_type = smu_cmn_to_asic_specific_index(smu,
1137 CMN2ASIC_MAPPING_WORKLOAD,
1138 i);
1139 if (workload_type < 0)
1140 continue;
1141
1142 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1143 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1144 }
1145
1146 return size;
1147 }
1148
renoir_get_ss_power_percent(SmuMetrics_t * metrics,uint32_t * apu_percent,uint32_t * dgpu_percent)1149 static void renoir_get_ss_power_percent(SmuMetrics_t *metrics,
1150 uint32_t *apu_percent, uint32_t *dgpu_percent)
1151 {
1152 uint32_t apu_boost = 0;
1153 uint32_t dgpu_boost = 0;
1154 uint16_t apu_limit = 0;
1155 uint16_t dgpu_limit = 0;
1156 uint16_t apu_power = 0;
1157 uint16_t dgpu_power = 0;
1158
1159 apu_power = metrics->ApuPower;
1160 apu_limit = metrics->StapmOriginalLimit;
1161 if (apu_power > apu_limit && apu_limit != 0)
1162 apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
1163 apu_boost = (apu_boost > 100) ? 100 : apu_boost;
1164
1165 dgpu_power = metrics->dGpuPower;
1166 if (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit)
1167 dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOriginalLimit;
1168 if (dgpu_power > dgpu_limit && dgpu_limit != 0)
1169 dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
1170 dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
1171
1172 if (dgpu_boost >= apu_boost)
1173 apu_boost = 0;
1174 else
1175 dgpu_boost = 0;
1176
1177 *apu_percent = apu_boost;
1178 *dgpu_percent = dgpu_boost;
1179 }
1180
1181
renoir_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1182 static int renoir_get_smu_metrics_data(struct smu_context *smu,
1183 MetricsMember_t member,
1184 uint32_t *value)
1185 {
1186 struct smu_table_context *smu_table = &smu->smu_table;
1187
1188 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
1189 int ret = 0;
1190 uint32_t apu_percent = 0;
1191 uint32_t dgpu_percent = 0;
1192 struct amdgpu_device *adev = smu->adev;
1193
1194
1195 ret = smu_cmn_get_metrics_table(smu,
1196 NULL,
1197 false);
1198 if (ret)
1199 return ret;
1200
1201 switch (member) {
1202 case METRICS_AVERAGE_GFXCLK:
1203 *value = metrics->ClockFrequency[CLOCK_GFXCLK];
1204 break;
1205 case METRICS_AVERAGE_SOCCLK:
1206 *value = metrics->ClockFrequency[CLOCK_SOCCLK];
1207 break;
1208 case METRICS_AVERAGE_UCLK:
1209 *value = metrics->ClockFrequency[CLOCK_FCLK];
1210 break;
1211 case METRICS_AVERAGE_GFXACTIVITY:
1212 *value = metrics->AverageGfxActivity / 100;
1213 break;
1214 case METRICS_AVERAGE_VCNACTIVITY:
1215 *value = metrics->AverageUvdActivity / 100;
1216 break;
1217 case METRICS_CURR_SOCKETPOWER:
1218 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1219 IP_VERSION(12, 0, 1)) &&
1220 (adev->pm.fw_version >= 0x40000f)) ||
1221 ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1222 IP_VERSION(12, 0, 0)) &&
1223 (adev->pm.fw_version >= 0x373200)))
1224 *value = metrics->CurrentSocketPower << 8;
1225 else
1226 *value = (metrics->CurrentSocketPower << 8) / 1000;
1227 break;
1228 case METRICS_TEMPERATURE_EDGE:
1229 *value = (metrics->GfxTemperature / 100) *
1230 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1231 break;
1232 case METRICS_TEMPERATURE_HOTSPOT:
1233 *value = (metrics->SocTemperature / 100) *
1234 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1235 break;
1236 case METRICS_THROTTLER_STATUS:
1237 *value = metrics->ThrottlerStatus;
1238 break;
1239 case METRICS_VOLTAGE_VDDGFX:
1240 *value = metrics->Voltage[0];
1241 break;
1242 case METRICS_VOLTAGE_VDDSOC:
1243 *value = metrics->Voltage[1];
1244 break;
1245 case METRICS_SS_APU_SHARE:
1246 /* return the percentage of APU power boost
1247 * with respect to APU's power limit.
1248 */
1249 renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1250 *value = apu_percent;
1251 break;
1252 case METRICS_SS_DGPU_SHARE:
1253 /* return the percentage of dGPU power boost
1254 * with respect to dGPU's power limit.
1255 */
1256 renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1257 *value = dgpu_percent;
1258 break;
1259 default:
1260 *value = UINT_MAX;
1261 break;
1262 }
1263
1264 return ret;
1265 }
1266
renoir_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1267 static int renoir_read_sensor(struct smu_context *smu,
1268 enum amd_pp_sensors sensor,
1269 void *data, uint32_t *size)
1270 {
1271 int ret = 0;
1272
1273 if (!data || !size)
1274 return -EINVAL;
1275
1276 switch (sensor) {
1277 case AMDGPU_PP_SENSOR_GPU_LOAD:
1278 ret = renoir_get_smu_metrics_data(smu,
1279 METRICS_AVERAGE_GFXACTIVITY,
1280 (uint32_t *)data);
1281 *size = 4;
1282 break;
1283 case AMDGPU_PP_SENSOR_VCN_LOAD:
1284 ret = renoir_get_smu_metrics_data(smu,
1285 METRICS_AVERAGE_VCNACTIVITY,
1286 (uint32_t *)data);
1287 *size = 4;
1288 break;
1289 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1290 ret = renoir_get_smu_metrics_data(smu,
1291 METRICS_TEMPERATURE_EDGE,
1292 (uint32_t *)data);
1293 *size = 4;
1294 break;
1295 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1296 ret = renoir_get_smu_metrics_data(smu,
1297 METRICS_TEMPERATURE_HOTSPOT,
1298 (uint32_t *)data);
1299 *size = 4;
1300 break;
1301 case AMDGPU_PP_SENSOR_GFX_MCLK:
1302 ret = renoir_get_smu_metrics_data(smu,
1303 METRICS_AVERAGE_UCLK,
1304 (uint32_t *)data);
1305 *(uint32_t *)data *= 100;
1306 *size = 4;
1307 break;
1308 case AMDGPU_PP_SENSOR_GFX_SCLK:
1309 ret = renoir_get_smu_metrics_data(smu,
1310 METRICS_AVERAGE_GFXCLK,
1311 (uint32_t *)data);
1312 *(uint32_t *)data *= 100;
1313 *size = 4;
1314 break;
1315 case AMDGPU_PP_SENSOR_VDDGFX:
1316 ret = renoir_get_smu_metrics_data(smu,
1317 METRICS_VOLTAGE_VDDGFX,
1318 (uint32_t *)data);
1319 *size = 4;
1320 break;
1321 case AMDGPU_PP_SENSOR_VDDNB:
1322 ret = renoir_get_smu_metrics_data(smu,
1323 METRICS_VOLTAGE_VDDSOC,
1324 (uint32_t *)data);
1325 *size = 4;
1326 break;
1327 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1328 ret = renoir_get_smu_metrics_data(smu,
1329 METRICS_CURR_SOCKETPOWER,
1330 (uint32_t *)data);
1331 *size = 4;
1332 break;
1333 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1334 ret = renoir_get_smu_metrics_data(smu,
1335 METRICS_SS_APU_SHARE,
1336 (uint32_t *)data);
1337 *size = 4;
1338 break;
1339 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1340 ret = renoir_get_smu_metrics_data(smu,
1341 METRICS_SS_DGPU_SHARE,
1342 (uint32_t *)data);
1343 *size = 4;
1344 break;
1345 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1346 default:
1347 ret = -EOPNOTSUPP;
1348 break;
1349 }
1350
1351 return ret;
1352 }
1353
renoir_is_dpm_running(struct smu_context * smu)1354 static bool renoir_is_dpm_running(struct smu_context *smu)
1355 {
1356 struct amdgpu_device *adev = smu->adev;
1357
1358 /*
1359 * Until now, the pmfw hasn't exported the interface of SMU
1360 * feature mask to APU SKU so just force on all the feature
1361 * at early initial stage.
1362 */
1363 if (adev->in_suspend)
1364 return false;
1365 else
1366 return true;
1367
1368 }
1369
renoir_get_gpu_metrics(struct smu_context * smu,void ** table)1370 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1371 void **table)
1372 {
1373 struct smu_table_context *smu_table = &smu->smu_table;
1374 struct gpu_metrics_v2_2 *gpu_metrics =
1375 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1376 SmuMetrics_t metrics;
1377 int ret = 0;
1378
1379 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1380 if (ret)
1381 return ret;
1382
1383 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1384
1385 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1386 gpu_metrics->temperature_soc = metrics.SocTemperature;
1387 memcpy(&gpu_metrics->temperature_core[0],
1388 &metrics.CoreTemperature[0],
1389 sizeof(uint16_t) * 8);
1390 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1391 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1392
1393 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1394 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1395
1396 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1397 gpu_metrics->average_cpu_power = metrics.Power[0];
1398 gpu_metrics->average_soc_power = metrics.Power[1];
1399 memcpy(&gpu_metrics->average_core_power[0],
1400 &metrics.CorePower[0],
1401 sizeof(uint16_t) * 8);
1402
1403 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1404 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1405 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1406 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1407
1408 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1409 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1410 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1411 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1412 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1413 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1414 memcpy(&gpu_metrics->current_coreclk[0],
1415 &metrics.CoreFrequency[0],
1416 sizeof(uint16_t) * 8);
1417 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1418 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1419
1420 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1421 gpu_metrics->indep_throttle_status =
1422 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1423 renoir_throttler_map);
1424
1425 gpu_metrics->fan_pwm = metrics.FanPwm;
1426
1427 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1428
1429 *table = (void *)gpu_metrics;
1430
1431 return sizeof(struct gpu_metrics_v2_2);
1432 }
1433
renoir_gfx_state_change_set(struct smu_context * smu,uint32_t state)1434 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
1435 {
1436
1437 return 0;
1438 }
1439
renoir_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)1440 static int renoir_get_enabled_mask(struct smu_context *smu,
1441 uint64_t *feature_mask)
1442 {
1443 if (!feature_mask)
1444 return -EINVAL;
1445 memset(feature_mask, 0xff, sizeof(*feature_mask));
1446
1447 return 0;
1448 }
1449
1450 static const struct pptable_funcs renoir_ppt_funcs = {
1451 .set_power_state = NULL,
1452 .print_clk_levels = renoir_print_clk_levels,
1453 .get_current_power_state = renoir_get_current_power_state,
1454 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1455 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1456 .force_clk_levels = renoir_force_clk_levels,
1457 .set_power_profile_mode = renoir_set_power_profile_mode,
1458 .set_performance_level = renoir_set_performance_level,
1459 .get_dpm_clock_table = renoir_get_dpm_clock_table,
1460 .set_watermarks_table = renoir_set_watermarks_table,
1461 .get_power_profile_mode = renoir_get_power_profile_mode,
1462 .read_sensor = renoir_read_sensor,
1463 .check_fw_status = smu_v12_0_check_fw_status,
1464 .check_fw_version = smu_v12_0_check_fw_version,
1465 .powergate_sdma = smu_v12_0_powergate_sdma,
1466 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1467 .send_smc_msg = smu_cmn_send_smc_msg,
1468 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1469 .gfx_off_control = smu_v12_0_gfx_off_control,
1470 .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1471 .init_smc_tables = renoir_init_smc_tables,
1472 .fini_smc_tables = smu_v12_0_fini_smc_tables,
1473 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1474 .get_enabled_mask = renoir_get_enabled_mask,
1475 .feature_is_enabled = smu_cmn_feature_is_enabled,
1476 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1477 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1478 .mode2_reset = smu_v12_0_mode2_reset,
1479 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1480 .set_driver_table_location = smu_v12_0_set_driver_table_location,
1481 .is_dpm_running = renoir_is_dpm_running,
1482 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1483 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1484 .get_gpu_metrics = renoir_get_gpu_metrics,
1485 .gfx_state_change_set = renoir_gfx_state_change_set,
1486 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters,
1487 .od_edit_dpm_table = renoir_od_edit_dpm_table,
1488 .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values,
1489 };
1490
renoir_set_ppt_funcs(struct smu_context * smu)1491 void renoir_set_ppt_funcs(struct smu_context *smu)
1492 {
1493 struct amdgpu_device *adev = smu->adev;
1494
1495 smu->ppt_funcs = &renoir_ppt_funcs;
1496 smu->message_map = renoir_message_map;
1497 smu->clock_map = renoir_clk_map;
1498 smu->table_map = renoir_table_map;
1499 smu->workload_map = renoir_workload_map;
1500 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1501 smu->is_apu = true;
1502 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1503 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1504 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1505 }
1506