1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v11_0.h"
29 #include "smu11_driver_if_vangogh.h"
30 #include "vangogh_ppt.h"
31 #include "smu_v11_5_ppsmc.h"
32 #include "smu_v11_5_pmfw.h"
33 #include "smu_cmn.h"
34 #include "soc15_common.h"
35 #include "asic_reg/gc/gc_10_3_0_offset.h"
36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37 #include <asm/processor.h>
38
39 /*
40 * DO NOT use these for err/warn/info/debug messages.
41 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42 * They are more MGPU friendly.
43 */
44 #undef pr_err
45 #undef pr_warn
46 #undef pr_info
47 #undef pr_debug
48
49 // Registers related to GFXOFF
50 // addressBlock: smuio_smuio_SmuSmuioDec
51 // base address: 0x5a000
52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5
53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
54
55 //SMUIO_GFX_MISC_CNTL
56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
60
61 #define FEATURE_MASK(feature) (1ULL << feature)
62 #define SMC_DPM_FEATURE ( \
63 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
64 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
65 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
66 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
67 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
68 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
69 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
70 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
71 FEATURE_MASK(FEATURE_GFX_DPM_BIT))
72
73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
77 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
80 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
81 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
82 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
83 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
84 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
85 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
86 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
87 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
88 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
89 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
94 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
95 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
96 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
97 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
98 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
99 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
100 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
101 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
102 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
103 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
104 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
105 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
106 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
107 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
110 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
111 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
112 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
113 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
114 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
115 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
116 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
117 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
118 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
119 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
120 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
121 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
122 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
123 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
124 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
125 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
126 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
127 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
128 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
129 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
130 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
131 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
132 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
133 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
134 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
135 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
136 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
137 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
138 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
139 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
140 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
141 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0),
142 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0),
143 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0),
144 };
145
146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
147 FEA_MAP(PPT),
148 FEA_MAP(TDC),
149 FEA_MAP(THERMAL),
150 FEA_MAP(DS_GFXCLK),
151 FEA_MAP(DS_SOCCLK),
152 FEA_MAP(DS_LCLK),
153 FEA_MAP(DS_FCLK),
154 FEA_MAP(DS_MP1CLK),
155 FEA_MAP(DS_MP0CLK),
156 FEA_MAP(ATHUB_PG),
157 FEA_MAP(CCLK_DPM),
158 FEA_MAP(FAN_CONTROLLER),
159 FEA_MAP(ULV),
160 FEA_MAP(VCN_DPM),
161 FEA_MAP(LCLK_DPM),
162 FEA_MAP(SHUBCLK_DPM),
163 FEA_MAP(DCFCLK_DPM),
164 FEA_MAP(DS_DCFCLK),
165 FEA_MAP(S0I2),
166 FEA_MAP(SMU_LOW_POWER),
167 FEA_MAP(GFX_DEM),
168 FEA_MAP(PSI),
169 FEA_MAP(PROCHOT),
170 FEA_MAP(CPUOFF),
171 FEA_MAP(STAPM),
172 FEA_MAP(S0I3),
173 FEA_MAP(DF_CSTATES),
174 FEA_MAP(PERF_LIMIT),
175 FEA_MAP(CORE_DLDO),
176 FEA_MAP(RSMU_LOW_POWER),
177 FEA_MAP(SMN_LOW_POWER),
178 FEA_MAP(THM_LOW_POWER),
179 FEA_MAP(SMUIO_LOW_POWER),
180 FEA_MAP(MP1_LOW_POWER),
181 FEA_MAP(DS_VCN),
182 FEA_MAP(CPPC),
183 FEA_MAP(OS_CSTATES),
184 FEA_MAP(ISP_DPM),
185 FEA_MAP(A55_DPM),
186 FEA_MAP(CVIP_DSP_DPM),
187 FEA_MAP(MSMU_LOW_POWER),
188 FEA_MAP_REVERSE(SOCCLK),
189 FEA_MAP_REVERSE(FCLK),
190 FEA_MAP_HALF_REVERSE(GFX),
191 };
192
193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
194 TAB_MAP_VALID(WATERMARKS),
195 TAB_MAP_VALID(SMU_METRICS),
196 TAB_MAP_VALID(CUSTOM_DPM),
197 TAB_MAP_VALID(DPMCLOCKS),
198 };
199
200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
201 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
202 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT),
208 };
209
210 static const uint8_t vangogh_throttler_map[] = {
211 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
212 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
213 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
214 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
215 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
216 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
217 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
218 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
219 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
220 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
221 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
222 };
223
vangogh_tables_init(struct smu_context * smu)224 static int vangogh_tables_init(struct smu_context *smu)
225 {
226 struct smu_table_context *smu_table = &smu->smu_table;
227 struct smu_table *tables = smu_table->tables;
228
229 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
230 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
231 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
235 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)),
238 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
239
240 smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL);
241 if (!smu_table->metrics_table)
242 goto err0_out;
243 smu_table->metrics_time = 0;
244
245 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
246 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_3));
247 smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_4));
248 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
249 if (!smu_table->gpu_metrics_table)
250 goto err1_out;
251
252 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
253 if (!smu_table->watermarks_table)
254 goto err2_out;
255
256 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
257 if (!smu_table->clocks_table)
258 goto err3_out;
259
260 return 0;
261
262 err3_out:
263 kfree(smu_table->watermarks_table);
264 err2_out:
265 kfree(smu_table->gpu_metrics_table);
266 err1_out:
267 kfree(smu_table->metrics_table);
268 err0_out:
269 return -ENOMEM;
270 }
271
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)272 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
273 MetricsMember_t member,
274 uint32_t *value)
275 {
276 struct smu_table_context *smu_table = &smu->smu_table;
277 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
278 int ret = 0;
279
280 ret = smu_cmn_get_metrics_table(smu,
281 NULL,
282 false);
283 if (ret)
284 return ret;
285
286 switch (member) {
287 case METRICS_CURR_GFXCLK:
288 *value = metrics->GfxclkFrequency;
289 break;
290 case METRICS_AVERAGE_SOCCLK:
291 *value = metrics->SocclkFrequency;
292 break;
293 case METRICS_AVERAGE_VCLK:
294 *value = metrics->VclkFrequency;
295 break;
296 case METRICS_AVERAGE_DCLK:
297 *value = metrics->DclkFrequency;
298 break;
299 case METRICS_CURR_UCLK:
300 *value = metrics->MemclkFrequency;
301 break;
302 case METRICS_AVERAGE_GFXACTIVITY:
303 *value = metrics->GfxActivity / 100;
304 break;
305 case METRICS_AVERAGE_VCNACTIVITY:
306 *value = metrics->UvdActivity / 100;
307 break;
308 case METRICS_AVERAGE_SOCKETPOWER:
309 *value = (metrics->CurrentSocketPower << 8) /
310 1000 ;
311 break;
312 case METRICS_TEMPERATURE_EDGE:
313 *value = metrics->GfxTemperature / 100 *
314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
315 break;
316 case METRICS_TEMPERATURE_HOTSPOT:
317 *value = metrics->SocTemperature / 100 *
318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
319 break;
320 case METRICS_THROTTLER_STATUS:
321 *value = metrics->ThrottlerStatus;
322 break;
323 case METRICS_VOLTAGE_VDDGFX:
324 *value = metrics->Voltage[2];
325 break;
326 case METRICS_VOLTAGE_VDDSOC:
327 *value = metrics->Voltage[1];
328 break;
329 case METRICS_AVERAGE_CPUCLK:
330 memcpy(value, &metrics->CoreFrequency[0],
331 smu->cpu_core_num * sizeof(uint16_t));
332 break;
333 default:
334 *value = UINT_MAX;
335 break;
336 }
337
338 return ret;
339 }
340
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)341 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
342 MetricsMember_t member,
343 uint32_t *value)
344 {
345 struct smu_table_context *smu_table = &smu->smu_table;
346 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
347 int ret = 0;
348
349 ret = smu_cmn_get_metrics_table(smu,
350 NULL,
351 false);
352 if (ret)
353 return ret;
354
355 switch (member) {
356 case METRICS_CURR_GFXCLK:
357 *value = metrics->Current.GfxclkFrequency;
358 break;
359 case METRICS_AVERAGE_SOCCLK:
360 *value = metrics->Current.SocclkFrequency;
361 break;
362 case METRICS_AVERAGE_VCLK:
363 *value = metrics->Current.VclkFrequency;
364 break;
365 case METRICS_AVERAGE_DCLK:
366 *value = metrics->Current.DclkFrequency;
367 break;
368 case METRICS_CURR_UCLK:
369 *value = metrics->Current.MemclkFrequency;
370 break;
371 case METRICS_AVERAGE_GFXACTIVITY:
372 *value = metrics->Current.GfxActivity;
373 break;
374 case METRICS_AVERAGE_VCNACTIVITY:
375 *value = metrics->Current.UvdActivity;
376 break;
377 case METRICS_AVERAGE_SOCKETPOWER:
378 *value = (metrics->Average.CurrentSocketPower << 8) /
379 1000;
380 break;
381 case METRICS_CURR_SOCKETPOWER:
382 *value = (metrics->Current.CurrentSocketPower << 8) /
383 1000;
384 break;
385 case METRICS_TEMPERATURE_EDGE:
386 *value = metrics->Current.GfxTemperature / 100 *
387 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
388 break;
389 case METRICS_TEMPERATURE_HOTSPOT:
390 *value = metrics->Current.SocTemperature / 100 *
391 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
392 break;
393 case METRICS_THROTTLER_STATUS:
394 *value = metrics->Current.ThrottlerStatus;
395 break;
396 case METRICS_VOLTAGE_VDDGFX:
397 *value = metrics->Current.Voltage[2];
398 break;
399 case METRICS_VOLTAGE_VDDSOC:
400 *value = metrics->Current.Voltage[1];
401 break;
402 case METRICS_AVERAGE_CPUCLK:
403 memcpy(value, &metrics->Current.CoreFrequency[0],
404 smu->cpu_core_num * sizeof(uint16_t));
405 break;
406 default:
407 *value = UINT_MAX;
408 break;
409 }
410
411 return ret;
412 }
413
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)414 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
415 MetricsMember_t member,
416 uint32_t *value)
417 {
418 int ret = 0;
419
420 if (smu->smc_fw_if_version < 0x3)
421 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
422 else
423 ret = vangogh_get_smu_metrics_data(smu, member, value);
424
425 return ret;
426 }
427
vangogh_allocate_dpm_context(struct smu_context * smu)428 static int vangogh_allocate_dpm_context(struct smu_context *smu)
429 {
430 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
431
432 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
433 GFP_KERNEL);
434 if (!smu_dpm->dpm_context)
435 return -ENOMEM;
436
437 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
438
439 return 0;
440 }
441
vangogh_init_smc_tables(struct smu_context * smu)442 static int vangogh_init_smc_tables(struct smu_context *smu)
443 {
444 int ret = 0;
445
446 ret = vangogh_tables_init(smu);
447 if (ret)
448 return ret;
449
450 ret = vangogh_allocate_dpm_context(smu);
451 if (ret)
452 return ret;
453
454 #ifdef CONFIG_X86
455 /* AMD x86 APU only */
456 smu->cpu_core_num = topology_num_cores_per_package();
457 #else
458 smu->cpu_core_num = 4;
459 #endif
460
461 return smu_v11_0_init_smc_tables(smu);
462 }
463
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)464 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu,
465 bool enable,
466 int inst)
467 {
468 int ret = 0;
469
470 if (enable) {
471 /* vcn dpm on is a prerequisite for vcn power gate messages */
472 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
473 if (ret)
474 return ret;
475 } else {
476 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
477 if (ret)
478 return ret;
479 }
480
481 return ret;
482 }
483
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)484 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
485 {
486 int ret = 0;
487
488 if (enable) {
489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
490 if (ret)
491 return ret;
492 } else {
493 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
494 if (ret)
495 return ret;
496 }
497
498 return ret;
499 }
500
vangogh_is_dpm_running(struct smu_context * smu)501 static bool vangogh_is_dpm_running(struct smu_context *smu)
502 {
503 struct amdgpu_device *adev = smu->adev;
504 int ret = 0;
505 uint64_t feature_enabled;
506
507 /* we need to re-init after suspend so return false */
508 if (adev->in_suspend)
509 return false;
510
511 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
512
513 if (ret)
514 return false;
515
516 return !!(feature_enabled & SMC_DPM_FEATURE);
517 }
518
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)519 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
520 uint32_t dpm_level, uint32_t *freq)
521 {
522 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
523
524 if (!clk_table || clk_type >= SMU_CLK_COUNT)
525 return -EINVAL;
526
527 switch (clk_type) {
528 case SMU_SOCCLK:
529 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
530 return -EINVAL;
531 *freq = clk_table->SocClocks[dpm_level];
532 break;
533 case SMU_VCLK:
534 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
535 return -EINVAL;
536 *freq = clk_table->VcnClocks[dpm_level].vclk;
537 break;
538 case SMU_DCLK:
539 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
540 return -EINVAL;
541 *freq = clk_table->VcnClocks[dpm_level].dclk;
542 break;
543 case SMU_UCLK:
544 case SMU_MCLK:
545 if (dpm_level >= clk_table->NumDfPstatesEnabled)
546 return -EINVAL;
547 *freq = clk_table->DfPstateTable[dpm_level].memclk;
548
549 break;
550 case SMU_FCLK:
551 if (dpm_level >= clk_table->NumDfPstatesEnabled)
552 return -EINVAL;
553 *freq = clk_table->DfPstateTable[dpm_level].fclk;
554 break;
555 default:
556 return -EINVAL;
557 }
558
559 return 0;
560 }
561
vangogh_print_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)562 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
563 enum smu_clk_type clk_type, char *buf)
564 {
565 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
566 SmuMetrics_legacy_t metrics;
567 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
568 int i, idx, size = 0, ret = 0;
569 uint32_t cur_value = 0, value = 0, count = 0;
570 bool cur_value_match_level = false;
571
572 memset(&metrics, 0, sizeof(metrics));
573
574 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
575 if (ret)
576 return ret;
577
578 smu_cmn_get_sysfs_buf(&buf, &size);
579
580 switch (clk_type) {
581 case SMU_OD_SCLK:
582 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
583 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
584 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
585 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
586 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
587 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
588 }
589 break;
590 case SMU_OD_CCLK:
591 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
592 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
593 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
594 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
595 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
596 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
597 }
598 break;
599 case SMU_OD_RANGE:
600 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
601 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
602 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
603 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
604 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
605 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
606 }
607 break;
608 case SMU_SOCCLK:
609 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
610 count = clk_table->NumSocClkLevelsEnabled;
611 cur_value = metrics.SocclkFrequency;
612 break;
613 case SMU_VCLK:
614 count = clk_table->VcnClkLevelsEnabled;
615 cur_value = metrics.VclkFrequency;
616 break;
617 case SMU_DCLK:
618 count = clk_table->VcnClkLevelsEnabled;
619 cur_value = metrics.DclkFrequency;
620 break;
621 case SMU_MCLK:
622 count = clk_table->NumDfPstatesEnabled;
623 cur_value = metrics.MemclkFrequency;
624 break;
625 case SMU_FCLK:
626 count = clk_table->NumDfPstatesEnabled;
627 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
628 if (ret)
629 return ret;
630 break;
631 default:
632 break;
633 }
634
635 switch (clk_type) {
636 case SMU_SOCCLK:
637 case SMU_VCLK:
638 case SMU_DCLK:
639 case SMU_MCLK:
640 case SMU_FCLK:
641 for (i = 0; i < count; i++) {
642 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
643 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
644 if (ret)
645 return ret;
646 if (!value)
647 continue;
648 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
649 cur_value == value ? "*" : "");
650 if (cur_value == value)
651 cur_value_match_level = true;
652 }
653
654 if (!cur_value_match_level)
655 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
656 break;
657 default:
658 break;
659 }
660
661 return size;
662 }
663
vangogh_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)664 static int vangogh_print_clk_levels(struct smu_context *smu,
665 enum smu_clk_type clk_type, char *buf)
666 {
667 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
668 SmuMetrics_t metrics;
669 int i, idx, size = 0, ret = 0;
670 uint32_t cur_value = 0, value = 0, count = 0;
671 bool cur_value_match_level = false;
672 uint32_t min, max;
673
674 memset(&metrics, 0, sizeof(metrics));
675
676 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
677 if (ret)
678 return ret;
679
680 smu_cmn_get_sysfs_buf(&buf, &size);
681
682 switch (clk_type) {
683 case SMU_OD_SCLK:
684 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
685 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
686 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
687 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
688 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
689 break;
690 case SMU_OD_CCLK:
691 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
692 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
693 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
694 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
695 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
696 break;
697 case SMU_OD_RANGE:
698 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
699 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
700 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
701 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
702 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
703 break;
704 case SMU_SOCCLK:
705 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
706 count = clk_table->NumSocClkLevelsEnabled;
707 cur_value = metrics.Current.SocclkFrequency;
708 break;
709 case SMU_VCLK:
710 count = clk_table->VcnClkLevelsEnabled;
711 cur_value = metrics.Current.VclkFrequency;
712 break;
713 case SMU_DCLK:
714 count = clk_table->VcnClkLevelsEnabled;
715 cur_value = metrics.Current.DclkFrequency;
716 break;
717 case SMU_MCLK:
718 count = clk_table->NumDfPstatesEnabled;
719 cur_value = metrics.Current.MemclkFrequency;
720 break;
721 case SMU_FCLK:
722 count = clk_table->NumDfPstatesEnabled;
723 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
724 if (ret)
725 return ret;
726 break;
727 case SMU_GFXCLK:
728 case SMU_SCLK:
729 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
730 if (ret) {
731 return ret;
732 }
733 break;
734 default:
735 break;
736 }
737
738 switch (clk_type) {
739 case SMU_SOCCLK:
740 case SMU_VCLK:
741 case SMU_DCLK:
742 case SMU_MCLK:
743 case SMU_FCLK:
744 for (i = 0; i < count; i++) {
745 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
746 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
747 if (ret)
748 return ret;
749 if (!value)
750 continue;
751 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
752 cur_value == value ? "*" : "");
753 if (cur_value == value)
754 cur_value_match_level = true;
755 }
756
757 if (!cur_value_match_level)
758 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
759 break;
760 case SMU_GFXCLK:
761 case SMU_SCLK:
762 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
763 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
764 if (cur_value == max)
765 i = 2;
766 else if (cur_value == min)
767 i = 0;
768 else
769 i = 1;
770 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
771 i == 0 ? "*" : "");
772 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
773 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
774 i == 1 ? "*" : "");
775 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
776 i == 2 ? "*" : "");
777 break;
778 default:
779 break;
780 }
781
782 return size;
783 }
784
vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)785 static int vangogh_common_print_clk_levels(struct smu_context *smu,
786 enum smu_clk_type clk_type, char *buf)
787 {
788 int ret = 0;
789
790 if (smu->smc_fw_if_version < 0x3)
791 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
792 else
793 ret = vangogh_print_clk_levels(smu, clk_type, buf);
794
795 return ret;
796 }
797
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)798 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
799 enum amd_dpm_forced_level level,
800 uint32_t *vclk_mask,
801 uint32_t *dclk_mask,
802 uint32_t *mclk_mask,
803 uint32_t *fclk_mask,
804 uint32_t *soc_mask)
805 {
806 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
807
808 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
809 if (mclk_mask)
810 *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
811
812 if (fclk_mask)
813 *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
814
815 if (soc_mask)
816 *soc_mask = 0;
817 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
818 if (mclk_mask)
819 *mclk_mask = 0;
820
821 if (fclk_mask)
822 *fclk_mask = 0;
823
824 if (soc_mask)
825 *soc_mask = 1;
826
827 if (vclk_mask)
828 *vclk_mask = 1;
829
830 if (dclk_mask)
831 *dclk_mask = 1;
832 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
833 if (mclk_mask)
834 *mclk_mask = 0;
835
836 if (fclk_mask)
837 *fclk_mask = 0;
838
839 if (soc_mask)
840 *soc_mask = 1;
841
842 if (vclk_mask)
843 *vclk_mask = 1;
844
845 if (dclk_mask)
846 *dclk_mask = 1;
847 }
848
849 return 0;
850 }
851
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)852 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
853 enum smu_clk_type clk_type)
854 {
855 enum smu_feature_mask feature_id = 0;
856
857 switch (clk_type) {
858 case SMU_MCLK:
859 case SMU_UCLK:
860 case SMU_FCLK:
861 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
862 break;
863 case SMU_GFXCLK:
864 case SMU_SCLK:
865 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
866 break;
867 case SMU_SOCCLK:
868 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
869 break;
870 case SMU_VCLK:
871 case SMU_DCLK:
872 feature_id = SMU_FEATURE_VCN_DPM_BIT;
873 break;
874 default:
875 return true;
876 }
877
878 if (!smu_cmn_feature_is_enabled(smu, feature_id))
879 return false;
880
881 return true;
882 }
883
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)884 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
885 enum smu_clk_type clk_type,
886 uint32_t *min,
887 uint32_t *max)
888 {
889 int ret = 0;
890 uint32_t soc_mask;
891 uint32_t vclk_mask;
892 uint32_t dclk_mask;
893 uint32_t mclk_mask;
894 uint32_t fclk_mask;
895 uint32_t clock_limit;
896
897 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
898 switch (clk_type) {
899 case SMU_MCLK:
900 case SMU_UCLK:
901 clock_limit = smu->smu_table.boot_values.uclk;
902 break;
903 case SMU_FCLK:
904 clock_limit = smu->smu_table.boot_values.fclk;
905 break;
906 case SMU_GFXCLK:
907 case SMU_SCLK:
908 clock_limit = smu->smu_table.boot_values.gfxclk;
909 break;
910 case SMU_SOCCLK:
911 clock_limit = smu->smu_table.boot_values.socclk;
912 break;
913 case SMU_VCLK:
914 clock_limit = smu->smu_table.boot_values.vclk;
915 break;
916 case SMU_DCLK:
917 clock_limit = smu->smu_table.boot_values.dclk;
918 break;
919 default:
920 clock_limit = 0;
921 break;
922 }
923
924 /* clock in Mhz unit */
925 if (min)
926 *min = clock_limit / 100;
927 if (max)
928 *max = clock_limit / 100;
929
930 return 0;
931 }
932 if (max) {
933 ret = vangogh_get_profiling_clk_mask(smu,
934 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
935 &vclk_mask,
936 &dclk_mask,
937 &mclk_mask,
938 &fclk_mask,
939 &soc_mask);
940 if (ret)
941 goto failed;
942
943 switch (clk_type) {
944 case SMU_UCLK:
945 case SMU_MCLK:
946 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
947 if (ret)
948 goto failed;
949 break;
950 case SMU_SOCCLK:
951 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
952 if (ret)
953 goto failed;
954 break;
955 case SMU_FCLK:
956 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
957 if (ret)
958 goto failed;
959 break;
960 case SMU_VCLK:
961 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
962 if (ret)
963 goto failed;
964 break;
965 case SMU_DCLK:
966 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
967 if (ret)
968 goto failed;
969 break;
970 default:
971 ret = -EINVAL;
972 goto failed;
973 }
974 }
975 if (min) {
976 ret = vangogh_get_profiling_clk_mask(smu,
977 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,
978 NULL,
979 NULL,
980 &mclk_mask,
981 &fclk_mask,
982 &soc_mask);
983 if (ret)
984 goto failed;
985
986 vclk_mask = dclk_mask = 0;
987
988 switch (clk_type) {
989 case SMU_UCLK:
990 case SMU_MCLK:
991 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
992 if (ret)
993 goto failed;
994 break;
995 case SMU_SOCCLK:
996 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
997 if (ret)
998 goto failed;
999 break;
1000 case SMU_FCLK:
1001 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1002 if (ret)
1003 goto failed;
1004 break;
1005 case SMU_VCLK:
1006 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1007 if (ret)
1008 goto failed;
1009 break;
1010 case SMU_DCLK:
1011 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1012 if (ret)
1013 goto failed;
1014 break;
1015 default:
1016 ret = -EINVAL;
1017 goto failed;
1018 }
1019 }
1020 failed:
1021 return ret;
1022 }
1023
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1024 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1025 char *buf)
1026 {
1027 uint32_t i, size = 0;
1028 int16_t workload_type = 0;
1029
1030 if (!buf)
1031 return -EINVAL;
1032
1033 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1034 /*
1035 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1036 * Not all profile modes are supported on vangogh.
1037 */
1038 workload_type = smu_cmn_to_asic_specific_index(smu,
1039 CMN2ASIC_MAPPING_WORKLOAD,
1040 i);
1041
1042 if (workload_type < 0)
1043 continue;
1044
1045 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1046 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1047 }
1048
1049 return size;
1050 }
1051
vangogh_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1052 static int vangogh_set_power_profile_mode(struct smu_context *smu,
1053 u32 workload_mask,
1054 long *custom_params,
1055 u32 custom_params_max_idx)
1056 {
1057 u32 backend_workload_mask = 0;
1058 int ret;
1059
1060 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1061 &backend_workload_mask);
1062
1063 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1064 backend_workload_mask,
1065 NULL);
1066 if (ret) {
1067 dev_err_once(smu->adev->dev, "Fail to set workload mask 0x%08x\n",
1068 workload_mask);
1069 return ret;
1070 }
1071
1072 return ret;
1073 }
1074
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1075 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1076 enum smu_clk_type clk_type,
1077 uint32_t min,
1078 uint32_t max,
1079 bool automatic)
1080 {
1081 int ret = 0;
1082
1083 if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1084 return 0;
1085
1086 switch (clk_type) {
1087 case SMU_GFXCLK:
1088 case SMU_SCLK:
1089 ret = smu_cmn_send_smc_msg_with_param(smu,
1090 SMU_MSG_SetHardMinGfxClk,
1091 min, NULL);
1092 if (ret)
1093 return ret;
1094
1095 ret = smu_cmn_send_smc_msg_with_param(smu,
1096 SMU_MSG_SetSoftMaxGfxClk,
1097 max, NULL);
1098 if (ret)
1099 return ret;
1100 break;
1101 case SMU_FCLK:
1102 ret = smu_cmn_send_smc_msg_with_param(smu,
1103 SMU_MSG_SetHardMinFclkByFreq,
1104 min, NULL);
1105 if (ret)
1106 return ret;
1107
1108 ret = smu_cmn_send_smc_msg_with_param(smu,
1109 SMU_MSG_SetSoftMaxFclkByFreq,
1110 max, NULL);
1111 if (ret)
1112 return ret;
1113 break;
1114 case SMU_SOCCLK:
1115 ret = smu_cmn_send_smc_msg_with_param(smu,
1116 SMU_MSG_SetHardMinSocclkByFreq,
1117 min, NULL);
1118 if (ret)
1119 return ret;
1120
1121 ret = smu_cmn_send_smc_msg_with_param(smu,
1122 SMU_MSG_SetSoftMaxSocclkByFreq,
1123 max, NULL);
1124 if (ret)
1125 return ret;
1126 break;
1127 case SMU_VCLK:
1128 ret = smu_cmn_send_smc_msg_with_param(smu,
1129 SMU_MSG_SetHardMinVcn,
1130 min << 16, NULL);
1131 if (ret)
1132 return ret;
1133 ret = smu_cmn_send_smc_msg_with_param(smu,
1134 SMU_MSG_SetSoftMaxVcn,
1135 max << 16, NULL);
1136 if (ret)
1137 return ret;
1138 break;
1139 case SMU_DCLK:
1140 ret = smu_cmn_send_smc_msg_with_param(smu,
1141 SMU_MSG_SetHardMinVcn,
1142 min, NULL);
1143 if (ret)
1144 return ret;
1145 ret = smu_cmn_send_smc_msg_with_param(smu,
1146 SMU_MSG_SetSoftMaxVcn,
1147 max, NULL);
1148 if (ret)
1149 return ret;
1150 break;
1151 default:
1152 return -EINVAL;
1153 }
1154
1155 return ret;
1156 }
1157
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1158 static int vangogh_force_clk_levels(struct smu_context *smu,
1159 enum smu_clk_type clk_type, uint32_t mask)
1160 {
1161 uint32_t soft_min_level = 0, soft_max_level = 0;
1162 uint32_t min_freq = 0, max_freq = 0;
1163 int ret = 0 ;
1164
1165 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1166 soft_max_level = mask ? (fls(mask) - 1) : 0;
1167
1168 switch (clk_type) {
1169 case SMU_SOCCLK:
1170 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1171 soft_min_level, &min_freq);
1172 if (ret)
1173 return ret;
1174 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1175 soft_max_level, &max_freq);
1176 if (ret)
1177 return ret;
1178 ret = smu_cmn_send_smc_msg_with_param(smu,
1179 SMU_MSG_SetSoftMaxSocclkByFreq,
1180 max_freq, NULL);
1181 if (ret)
1182 return ret;
1183 ret = smu_cmn_send_smc_msg_with_param(smu,
1184 SMU_MSG_SetHardMinSocclkByFreq,
1185 min_freq, NULL);
1186 if (ret)
1187 return ret;
1188 break;
1189 case SMU_FCLK:
1190 ret = vangogh_get_dpm_clk_limited(smu,
1191 clk_type, soft_min_level, &min_freq);
1192 if (ret)
1193 return ret;
1194 ret = vangogh_get_dpm_clk_limited(smu,
1195 clk_type, soft_max_level, &max_freq);
1196 if (ret)
1197 return ret;
1198 ret = smu_cmn_send_smc_msg_with_param(smu,
1199 SMU_MSG_SetSoftMaxFclkByFreq,
1200 max_freq, NULL);
1201 if (ret)
1202 return ret;
1203 ret = smu_cmn_send_smc_msg_with_param(smu,
1204 SMU_MSG_SetHardMinFclkByFreq,
1205 min_freq, NULL);
1206 if (ret)
1207 return ret;
1208 break;
1209 case SMU_VCLK:
1210 ret = vangogh_get_dpm_clk_limited(smu,
1211 clk_type, soft_min_level, &min_freq);
1212 if (ret)
1213 return ret;
1214
1215 ret = vangogh_get_dpm_clk_limited(smu,
1216 clk_type, soft_max_level, &max_freq);
1217 if (ret)
1218 return ret;
1219
1220
1221 ret = smu_cmn_send_smc_msg_with_param(smu,
1222 SMU_MSG_SetHardMinVcn,
1223 min_freq << 16, NULL);
1224 if (ret)
1225 return ret;
1226
1227 ret = smu_cmn_send_smc_msg_with_param(smu,
1228 SMU_MSG_SetSoftMaxVcn,
1229 max_freq << 16, NULL);
1230 if (ret)
1231 return ret;
1232
1233 break;
1234 case SMU_DCLK:
1235 ret = vangogh_get_dpm_clk_limited(smu,
1236 clk_type, soft_min_level, &min_freq);
1237 if (ret)
1238 return ret;
1239
1240 ret = vangogh_get_dpm_clk_limited(smu,
1241 clk_type, soft_max_level, &max_freq);
1242 if (ret)
1243 return ret;
1244
1245 ret = smu_cmn_send_smc_msg_with_param(smu,
1246 SMU_MSG_SetHardMinVcn,
1247 min_freq, NULL);
1248 if (ret)
1249 return ret;
1250
1251 ret = smu_cmn_send_smc_msg_with_param(smu,
1252 SMU_MSG_SetSoftMaxVcn,
1253 max_freq, NULL);
1254 if (ret)
1255 return ret;
1256
1257 break;
1258 default:
1259 break;
1260 }
1261
1262 return ret;
1263 }
1264
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1265 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1266 {
1267 int ret = 0, i = 0;
1268 uint32_t min_freq, max_freq, force_freq;
1269 enum smu_clk_type clk_type;
1270
1271 enum smu_clk_type clks[] = {
1272 SMU_SOCCLK,
1273 SMU_VCLK,
1274 SMU_DCLK,
1275 SMU_FCLK,
1276 };
1277
1278 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1279 clk_type = clks[i];
1280 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1281 if (ret)
1282 return ret;
1283
1284 force_freq = highest ? max_freq : min_freq;
1285 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);
1286 if (ret)
1287 return ret;
1288 }
1289
1290 return ret;
1291 }
1292
vangogh_unforce_dpm_levels(struct smu_context * smu)1293 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1294 {
1295 int ret = 0, i = 0;
1296 uint32_t min_freq, max_freq;
1297 enum smu_clk_type clk_type;
1298
1299 struct clk_feature_map {
1300 enum smu_clk_type clk_type;
1301 uint32_t feature;
1302 } clk_feature_map[] = {
1303 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1304 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1305 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1306 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1307 };
1308
1309 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1310
1311 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1312 continue;
1313
1314 clk_type = clk_feature_map[i].clk_type;
1315
1316 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1317
1318 if (ret)
1319 return ret;
1320
1321 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
1322
1323 if (ret)
1324 return ret;
1325 }
1326
1327 return ret;
1328 }
1329
vangogh_set_peak_clock_by_device(struct smu_context * smu)1330 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1331 {
1332 int ret = 0;
1333 uint32_t socclk_freq = 0, fclk_freq = 0;
1334 uint32_t vclk_freq = 0, dclk_freq = 0;
1335
1336 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1337 if (ret)
1338 return ret;
1339
1340 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq, false);
1341 if (ret)
1342 return ret;
1343
1344 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1345 if (ret)
1346 return ret;
1347
1348 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq, false);
1349 if (ret)
1350 return ret;
1351
1352 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1353 if (ret)
1354 return ret;
1355
1356 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq, false);
1357 if (ret)
1358 return ret;
1359
1360 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1361 if (ret)
1362 return ret;
1363
1364 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq, false);
1365 if (ret)
1366 return ret;
1367
1368 return ret;
1369 }
1370
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1371 static int vangogh_set_performance_level(struct smu_context *smu,
1372 enum amd_dpm_forced_level level)
1373 {
1374 int ret = 0, i;
1375 uint32_t soc_mask, mclk_mask, fclk_mask;
1376 uint32_t vclk_mask = 0, dclk_mask = 0;
1377
1378 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1379 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1380
1381 switch (level) {
1382 case AMD_DPM_FORCED_LEVEL_HIGH:
1383 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1384 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1385
1386
1387 ret = vangogh_force_dpm_limit_value(smu, true);
1388 if (ret)
1389 return ret;
1390 break;
1391 case AMD_DPM_FORCED_LEVEL_LOW:
1392 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1393 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1394
1395 ret = vangogh_force_dpm_limit_value(smu, false);
1396 if (ret)
1397 return ret;
1398 break;
1399 case AMD_DPM_FORCED_LEVEL_AUTO:
1400 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1401 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1402
1403 ret = vangogh_unforce_dpm_levels(smu);
1404 if (ret)
1405 return ret;
1406 break;
1407 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1408 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1409 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1410
1411 ret = vangogh_get_profiling_clk_mask(smu, level,
1412 &vclk_mask,
1413 &dclk_mask,
1414 &mclk_mask,
1415 &fclk_mask,
1416 &soc_mask);
1417 if (ret)
1418 return ret;
1419
1420 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1421 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1422 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1423 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1424 break;
1425 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1426 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1427 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1428 break;
1429 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1430 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1431 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1432
1433 ret = vangogh_get_profiling_clk_mask(smu, level,
1434 NULL,
1435 NULL,
1436 &mclk_mask,
1437 &fclk_mask,
1438 NULL);
1439 if (ret)
1440 return ret;
1441
1442 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1443 break;
1444 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1445 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1446 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1447
1448 ret = vangogh_set_peak_clock_by_device(smu);
1449 if (ret)
1450 return ret;
1451 break;
1452 case AMD_DPM_FORCED_LEVEL_MANUAL:
1453 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1454 default:
1455 return 0;
1456 }
1457
1458 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1459 smu->gfx_actual_hard_min_freq, NULL);
1460 if (ret)
1461 return ret;
1462
1463 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1464 smu->gfx_actual_soft_max_freq, NULL);
1465 if (ret)
1466 return ret;
1467
1468 if (smu->adev->pm.fw_version >= 0x43f1b00) {
1469 for (i = 0; i < smu->cpu_core_num; i++) {
1470 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1471 ((i << 20)
1472 | smu->cpu_actual_soft_min_freq),
1473 NULL);
1474 if (ret)
1475 return ret;
1476
1477 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1478 ((i << 20)
1479 | smu->cpu_actual_soft_max_freq),
1480 NULL);
1481 if (ret)
1482 return ret;
1483 }
1484 }
1485
1486 return ret;
1487 }
1488
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1489 static int vangogh_read_sensor(struct smu_context *smu,
1490 enum amd_pp_sensors sensor,
1491 void *data, uint32_t *size)
1492 {
1493 int ret = 0;
1494
1495 if (!data || !size)
1496 return -EINVAL;
1497
1498 switch (sensor) {
1499 case AMDGPU_PP_SENSOR_GPU_LOAD:
1500 ret = vangogh_common_get_smu_metrics_data(smu,
1501 METRICS_AVERAGE_GFXACTIVITY,
1502 (uint32_t *)data);
1503 *size = 4;
1504 break;
1505 case AMDGPU_PP_SENSOR_VCN_LOAD:
1506 ret = vangogh_common_get_smu_metrics_data(smu,
1507 METRICS_AVERAGE_VCNACTIVITY,
1508 (uint32_t *)data);
1509 *size = 4;
1510 break;
1511 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1512 ret = vangogh_common_get_smu_metrics_data(smu,
1513 METRICS_AVERAGE_SOCKETPOWER,
1514 (uint32_t *)data);
1515 *size = 4;
1516 break;
1517 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1518 ret = vangogh_common_get_smu_metrics_data(smu,
1519 METRICS_CURR_SOCKETPOWER,
1520 (uint32_t *)data);
1521 *size = 4;
1522 break;
1523 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1524 ret = vangogh_common_get_smu_metrics_data(smu,
1525 METRICS_TEMPERATURE_EDGE,
1526 (uint32_t *)data);
1527 *size = 4;
1528 break;
1529 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1530 ret = vangogh_common_get_smu_metrics_data(smu,
1531 METRICS_TEMPERATURE_HOTSPOT,
1532 (uint32_t *)data);
1533 *size = 4;
1534 break;
1535 case AMDGPU_PP_SENSOR_GFX_MCLK:
1536 ret = vangogh_common_get_smu_metrics_data(smu,
1537 METRICS_CURR_UCLK,
1538 (uint32_t *)data);
1539 *(uint32_t *)data *= 100;
1540 *size = 4;
1541 break;
1542 case AMDGPU_PP_SENSOR_GFX_SCLK:
1543 ret = vangogh_common_get_smu_metrics_data(smu,
1544 METRICS_CURR_GFXCLK,
1545 (uint32_t *)data);
1546 *(uint32_t *)data *= 100;
1547 *size = 4;
1548 break;
1549 case AMDGPU_PP_SENSOR_VDDGFX:
1550 ret = vangogh_common_get_smu_metrics_data(smu,
1551 METRICS_VOLTAGE_VDDGFX,
1552 (uint32_t *)data);
1553 *size = 4;
1554 break;
1555 case AMDGPU_PP_SENSOR_VDDNB:
1556 ret = vangogh_common_get_smu_metrics_data(smu,
1557 METRICS_VOLTAGE_VDDSOC,
1558 (uint32_t *)data);
1559 *size = 4;
1560 break;
1561 case AMDGPU_PP_SENSOR_CPU_CLK:
1562 ret = vangogh_common_get_smu_metrics_data(smu,
1563 METRICS_AVERAGE_CPUCLK,
1564 (uint32_t *)data);
1565 *size = smu->cpu_core_num * sizeof(uint16_t);
1566 break;
1567 default:
1568 ret = -EOPNOTSUPP;
1569 break;
1570 }
1571
1572 return ret;
1573 }
1574
vangogh_get_apu_thermal_limit(struct smu_context * smu,uint32_t * limit)1575 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
1576 {
1577 return smu_cmn_send_smc_msg_with_param(smu,
1578 SMU_MSG_GetThermalLimit,
1579 0, limit);
1580 }
1581
vangogh_set_apu_thermal_limit(struct smu_context * smu,uint32_t limit)1582 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
1583 {
1584 return smu_cmn_send_smc_msg_with_param(smu,
1585 SMU_MSG_SetReducedThermalLimit,
1586 limit, NULL);
1587 }
1588
1589
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1590 static int vangogh_set_watermarks_table(struct smu_context *smu,
1591 struct pp_smu_wm_range_sets *clock_ranges)
1592 {
1593 int i;
1594 int ret = 0;
1595 Watermarks_t *table = smu->smu_table.watermarks_table;
1596
1597 if (!table || !clock_ranges)
1598 return -EINVAL;
1599
1600 if (clock_ranges) {
1601 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1602 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1603 return -EINVAL;
1604
1605 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1606 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1607 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1608 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1609 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1610 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1611 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1612 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1613 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1614
1615 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1616 clock_ranges->reader_wm_sets[i].wm_inst;
1617 }
1618
1619 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1620 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1621 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1622 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1623 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1624 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1625 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1626 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1627 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1628
1629 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1630 clock_ranges->writer_wm_sets[i].wm_inst;
1631 }
1632
1633 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1634 }
1635
1636 /* pass data to smu controller */
1637 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1638 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1639 ret = smu_cmn_write_watermarks_table(smu);
1640 if (ret) {
1641 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1642 return ret;
1643 }
1644 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1645 }
1646
1647 return 0;
1648 }
1649
vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1650 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
1651 void **table)
1652 {
1653 struct smu_table_context *smu_table = &smu->smu_table;
1654 struct gpu_metrics_v2_3 *gpu_metrics =
1655 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1656 SmuMetrics_legacy_t metrics;
1657 int ret = 0;
1658
1659 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1660 if (ret)
1661 return ret;
1662
1663 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1664
1665 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1666 gpu_metrics->temperature_soc = metrics.SocTemperature;
1667 memcpy(&gpu_metrics->temperature_core[0],
1668 &metrics.CoreTemperature[0],
1669 sizeof(uint16_t) * 4);
1670 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1671
1672 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1673 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1674
1675 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1676 gpu_metrics->average_cpu_power = metrics.Power[0];
1677 gpu_metrics->average_soc_power = metrics.Power[1];
1678 gpu_metrics->average_gfx_power = metrics.Power[2];
1679 memcpy(&gpu_metrics->average_core_power[0],
1680 &metrics.CorePower[0],
1681 sizeof(uint16_t) * 4);
1682
1683 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1684 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1685 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1686 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1687 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1688 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1689
1690 memcpy(&gpu_metrics->current_coreclk[0],
1691 &metrics.CoreFrequency[0],
1692 sizeof(uint16_t) * 4);
1693 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1694
1695 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1696 gpu_metrics->indep_throttle_status =
1697 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1698 vangogh_throttler_map);
1699
1700 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1701
1702 *table = (void *)gpu_metrics;
1703
1704 return sizeof(struct gpu_metrics_v2_3);
1705 }
1706
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)1707 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1708 void **table)
1709 {
1710 struct smu_table_context *smu_table = &smu->smu_table;
1711 struct gpu_metrics_v2_2 *gpu_metrics =
1712 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1713 SmuMetrics_legacy_t metrics;
1714 int ret = 0;
1715
1716 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1717 if (ret)
1718 return ret;
1719
1720 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1721
1722 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1723 gpu_metrics->temperature_soc = metrics.SocTemperature;
1724 memcpy(&gpu_metrics->temperature_core[0],
1725 &metrics.CoreTemperature[0],
1726 sizeof(uint16_t) * 4);
1727 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1728
1729 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1730 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1731
1732 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1733 gpu_metrics->average_cpu_power = metrics.Power[0];
1734 gpu_metrics->average_soc_power = metrics.Power[1];
1735 gpu_metrics->average_gfx_power = metrics.Power[2];
1736 memcpy(&gpu_metrics->average_core_power[0],
1737 &metrics.CorePower[0],
1738 sizeof(uint16_t) * 4);
1739
1740 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1741 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1742 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1743 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1744 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1745 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1746
1747 memcpy(&gpu_metrics->current_coreclk[0],
1748 &metrics.CoreFrequency[0],
1749 sizeof(uint16_t) * 4);
1750 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1751
1752 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1753 gpu_metrics->indep_throttle_status =
1754 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1755 vangogh_throttler_map);
1756
1757 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1758
1759 *table = (void *)gpu_metrics;
1760
1761 return sizeof(struct gpu_metrics_v2_2);
1762 }
1763
vangogh_get_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1764 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
1765 void **table)
1766 {
1767 struct smu_table_context *smu_table = &smu->smu_table;
1768 struct gpu_metrics_v2_3 *gpu_metrics =
1769 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1770 SmuMetrics_t metrics;
1771 int ret = 0;
1772
1773 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1774 if (ret)
1775 return ret;
1776
1777 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1778
1779 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1780 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1781 memcpy(&gpu_metrics->temperature_core[0],
1782 &metrics.Current.CoreTemperature[0],
1783 sizeof(uint16_t) * 4);
1784 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1785
1786 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1787 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1788 memcpy(&gpu_metrics->average_temperature_core[0],
1789 &metrics.Average.CoreTemperature[0],
1790 sizeof(uint16_t) * 4);
1791 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1792
1793 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1794 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1795
1796 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1797 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1798 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1799 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1800 memcpy(&gpu_metrics->average_core_power[0],
1801 &metrics.Average.CorePower[0],
1802 sizeof(uint16_t) * 4);
1803
1804 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1805 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1806 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1807 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1808 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1809 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1810
1811 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1812 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1813 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1814 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1815 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1816 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1817
1818 memcpy(&gpu_metrics->current_coreclk[0],
1819 &metrics.Current.CoreFrequency[0],
1820 sizeof(uint16_t) * 4);
1821 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1822
1823 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1824 gpu_metrics->indep_throttle_status =
1825 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1826 vangogh_throttler_map);
1827
1828 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1829
1830 *table = (void *)gpu_metrics;
1831
1832 return sizeof(struct gpu_metrics_v2_3);
1833 }
1834
vangogh_get_gpu_metrics_v2_4(struct smu_context * smu,void ** table)1835 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
1836 void **table)
1837 {
1838 SmuMetrics_t metrics;
1839 struct smu_table_context *smu_table = &smu->smu_table;
1840 struct gpu_metrics_v2_4 *gpu_metrics =
1841 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table;
1842 int ret = 0;
1843
1844 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1845 if (ret)
1846 return ret;
1847
1848 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
1849
1850 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1851 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1852 memcpy(&gpu_metrics->temperature_core[0],
1853 &metrics.Current.CoreTemperature[0],
1854 sizeof(uint16_t) * 4);
1855 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1856
1857 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1858 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1859 memcpy(&gpu_metrics->average_temperature_core[0],
1860 &metrics.Average.CoreTemperature[0],
1861 sizeof(uint16_t) * 4);
1862 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1863
1864 gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity;
1865 gpu_metrics->average_mm_activity = metrics.Average.UvdActivity;
1866
1867 gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower;
1868 gpu_metrics->average_cpu_power = metrics.Average.Power[0];
1869 gpu_metrics->average_soc_power = metrics.Average.Power[1];
1870 gpu_metrics->average_gfx_power = metrics.Average.Power[2];
1871
1872 gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0];
1873 gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1];
1874 gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2];
1875
1876 gpu_metrics->average_cpu_current = metrics.Average.Current[0];
1877 gpu_metrics->average_soc_current = metrics.Average.Current[1];
1878 gpu_metrics->average_gfx_current = metrics.Average.Current[2];
1879
1880 memcpy(&gpu_metrics->average_core_power[0],
1881 &metrics.Average.CorePower[0],
1882 sizeof(uint16_t) * 4);
1883
1884 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1885 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1886 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1887 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1888 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1889 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1890
1891 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1892 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1893 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1894 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1895 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1896 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1897
1898 memcpy(&gpu_metrics->current_coreclk[0],
1899 &metrics.Current.CoreFrequency[0],
1900 sizeof(uint16_t) * 4);
1901 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1902
1903 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1904 gpu_metrics->indep_throttle_status =
1905 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1906 vangogh_throttler_map);
1907
1908 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1909
1910 *table = (void *)gpu_metrics;
1911
1912 return sizeof(struct gpu_metrics_v2_4);
1913 }
1914
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1915 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1916 void **table)
1917 {
1918 struct smu_table_context *smu_table = &smu->smu_table;
1919 struct gpu_metrics_v2_2 *gpu_metrics =
1920 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1921 SmuMetrics_t metrics;
1922 int ret = 0;
1923
1924 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1925 if (ret)
1926 return ret;
1927
1928 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1929
1930 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1931 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1932 memcpy(&gpu_metrics->temperature_core[0],
1933 &metrics.Current.CoreTemperature[0],
1934 sizeof(uint16_t) * 4);
1935 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1936
1937 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1938 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1939
1940 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1941 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1942 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1943 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1944 memcpy(&gpu_metrics->average_core_power[0],
1945 &metrics.Average.CorePower[0],
1946 sizeof(uint16_t) * 4);
1947
1948 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1949 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1950 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1951 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1952 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1953 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1954
1955 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1956 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1957 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1958 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1959 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1960 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1961
1962 memcpy(&gpu_metrics->current_coreclk[0],
1963 &metrics.Current.CoreFrequency[0],
1964 sizeof(uint16_t) * 4);
1965 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1966
1967 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1968 gpu_metrics->indep_throttle_status =
1969 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1970 vangogh_throttler_map);
1971
1972 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1973
1974 *table = (void *)gpu_metrics;
1975
1976 return sizeof(struct gpu_metrics_v2_2);
1977 }
1978
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)1979 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1980 void **table)
1981 {
1982 uint32_t smu_program;
1983 uint32_t fw_version;
1984 int ret = 0;
1985
1986 smu_program = (smu->smc_fw_version >> 24) & 0xff;
1987 fw_version = smu->smc_fw_version & 0xffffff;
1988 if (smu_program == 6) {
1989 if (fw_version >= 0x3F0800)
1990 ret = vangogh_get_gpu_metrics_v2_4(smu, table);
1991 else
1992 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
1993
1994 } else {
1995 if (smu->smc_fw_version >= 0x043F3E00) {
1996 if (smu->smc_fw_if_version < 0x3)
1997 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
1998 else
1999 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2000 } else {
2001 if (smu->smc_fw_if_version < 0x3)
2002 ret = vangogh_get_legacy_gpu_metrics(smu, table);
2003 else
2004 ret = vangogh_get_gpu_metrics(smu, table);
2005 }
2006 }
2007
2008 return ret;
2009 }
2010
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2011 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2012 long input[], uint32_t size)
2013 {
2014 int ret = 0;
2015 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2016
2017 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2018 dev_warn(smu->adev->dev,
2019 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2020 return -EINVAL;
2021 }
2022
2023 switch (type) {
2024 case PP_OD_EDIT_CCLK_VDDC_TABLE:
2025 if (size != 3) {
2026 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
2027 return -EINVAL;
2028 }
2029 if (input[0] >= smu->cpu_core_num) {
2030 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
2031 smu->cpu_core_num);
2032 }
2033 smu->cpu_core_id_select = input[0];
2034 if (input[1] == 0) {
2035 if (input[2] < smu->cpu_default_soft_min_freq) {
2036 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2037 input[2], smu->cpu_default_soft_min_freq);
2038 return -EINVAL;
2039 }
2040 smu->cpu_actual_soft_min_freq = input[2];
2041 } else if (input[1] == 1) {
2042 if (input[2] > smu->cpu_default_soft_max_freq) {
2043 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2044 input[2], smu->cpu_default_soft_max_freq);
2045 return -EINVAL;
2046 }
2047 smu->cpu_actual_soft_max_freq = input[2];
2048 } else {
2049 return -EINVAL;
2050 }
2051 break;
2052 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2053 if (size != 2) {
2054 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2055 return -EINVAL;
2056 }
2057
2058 if (input[0] == 0) {
2059 if (input[1] < smu->gfx_default_hard_min_freq) {
2060 dev_warn(smu->adev->dev,
2061 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2062 input[1], smu->gfx_default_hard_min_freq);
2063 return -EINVAL;
2064 }
2065 smu->gfx_actual_hard_min_freq = input[1];
2066 } else if (input[0] == 1) {
2067 if (input[1] > smu->gfx_default_soft_max_freq) {
2068 dev_warn(smu->adev->dev,
2069 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2070 input[1], smu->gfx_default_soft_max_freq);
2071 return -EINVAL;
2072 }
2073 smu->gfx_actual_soft_max_freq = input[1];
2074 } else {
2075 return -EINVAL;
2076 }
2077 break;
2078 case PP_OD_RESTORE_DEFAULT_TABLE:
2079 if (size != 0) {
2080 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2081 return -EINVAL;
2082 } else {
2083 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2084 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2085 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
2086 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2087 }
2088 break;
2089 case PP_OD_COMMIT_DPM_TABLE:
2090 if (size != 0) {
2091 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2092 return -EINVAL;
2093 } else {
2094 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2095 dev_err(smu->adev->dev,
2096 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2097 smu->gfx_actual_hard_min_freq,
2098 smu->gfx_actual_soft_max_freq);
2099 return -EINVAL;
2100 }
2101
2102 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2103 smu->gfx_actual_hard_min_freq, NULL);
2104 if (ret) {
2105 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2106 return ret;
2107 }
2108
2109 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2110 smu->gfx_actual_soft_max_freq, NULL);
2111 if (ret) {
2112 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2113 return ret;
2114 }
2115
2116 if (smu->adev->pm.fw_version < 0x43f1b00) {
2117 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
2118 break;
2119 }
2120
2121 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
2122 ((smu->cpu_core_id_select << 20)
2123 | smu->cpu_actual_soft_min_freq),
2124 NULL);
2125 if (ret) {
2126 dev_err(smu->adev->dev, "Set hard min cclk failed!");
2127 return ret;
2128 }
2129
2130 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
2131 ((smu->cpu_core_id_select << 20)
2132 | smu->cpu_actual_soft_max_freq),
2133 NULL);
2134 if (ret) {
2135 dev_err(smu->adev->dev, "Set soft max cclk failed!");
2136 return ret;
2137 }
2138 }
2139 break;
2140 default:
2141 return -ENOSYS;
2142 }
2143
2144 return ret;
2145 }
2146
vangogh_set_default_dpm_tables(struct smu_context * smu)2147 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2148 {
2149 struct smu_table_context *smu_table = &smu->smu_table;
2150
2151 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2152 }
2153
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)2154 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2155 {
2156 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2157
2158 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2159 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2160 smu->gfx_actual_hard_min_freq = 0;
2161 smu->gfx_actual_soft_max_freq = 0;
2162
2163 smu->cpu_default_soft_min_freq = 1400;
2164 smu->cpu_default_soft_max_freq = 3500;
2165 smu->cpu_actual_soft_min_freq = 0;
2166 smu->cpu_actual_soft_max_freq = 0;
2167
2168 return 0;
2169 }
2170
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)2171 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2172 {
2173 DpmClocks_t *table = smu->smu_table.clocks_table;
2174 int i;
2175
2176 if (!clock_table || !table)
2177 return -EINVAL;
2178
2179 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2180 clock_table->SocClocks[i].Freq = table->SocClocks[i];
2181 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2182 }
2183
2184 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2185 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2186 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2187 }
2188
2189 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2190 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2191 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2192 }
2193
2194 return 0;
2195 }
2196
vangogh_notify_rlc_state(struct smu_context * smu,bool en)2197 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2198 {
2199 struct amdgpu_device *adev = smu->adev;
2200 int ret = 0;
2201
2202 if (adev->pm.fw_version >= 0x43f1700 && !en)
2203 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
2204 RLC_STATUS_OFF, NULL);
2205
2206 return ret;
2207 }
2208
vangogh_post_smu_init(struct smu_context * smu)2209 static int vangogh_post_smu_init(struct smu_context *smu)
2210 {
2211 struct amdgpu_device *adev = smu->adev;
2212 uint32_t tmp;
2213 int ret = 0;
2214 uint8_t aon_bits = 0;
2215 /* Two CUs in one WGP */
2216 uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2217 uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2218 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2219
2220 /* allow message will be sent after enable message on Vangogh*/
2221 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2222 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2223 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2224 if (ret) {
2225 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2226 return ret;
2227 }
2228 } else {
2229 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2230 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2231 }
2232
2233 /* if all CUs are active, no need to power off any WGPs */
2234 if (total_cu == adev->gfx.cu_info.number)
2235 return 0;
2236
2237 /*
2238 * Calculate the total bits number of always on WGPs for all SA/SEs in
2239 * RLC_PG_ALWAYS_ON_WGP_MASK.
2240 */
2241 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2242 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2243
2244 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2245
2246 /* Do not request any WGPs less than set in the AON_WGP_MASK */
2247 if (aon_bits > req_active_wgps) {
2248 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2249 return 0;
2250 } else {
2251 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2252 }
2253 }
2254
vangogh_mode_reset(struct smu_context * smu,int type)2255 static int vangogh_mode_reset(struct smu_context *smu, int type)
2256 {
2257 int ret = 0, index = 0;
2258
2259 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2260 SMU_MSG_GfxDeviceDriverReset);
2261 if (index < 0)
2262 return index == -EACCES ? 0 : index;
2263
2264 mutex_lock(&smu->message_lock);
2265
2266 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2267
2268 mutex_unlock(&smu->message_lock);
2269
2270 mdelay(10);
2271
2272 return ret;
2273 }
2274
vangogh_mode2_reset(struct smu_context * smu)2275 static int vangogh_mode2_reset(struct smu_context *smu)
2276 {
2277 return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2278 }
2279
2280 /**
2281 * vangogh_get_gfxoff_status - Get gfxoff status
2282 *
2283 * @smu: amdgpu_device pointer
2284 *
2285 * Get current gfxoff status
2286 *
2287 * Return:
2288 * * 0 - GFXOFF (default if enabled).
2289 * * 1 - Transition out of GFX State.
2290 * * 2 - Not in GFXOFF.
2291 * * 3 - Transition into GFXOFF.
2292 */
vangogh_get_gfxoff_status(struct smu_context * smu)2293 static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
2294 {
2295 struct amdgpu_device *adev = smu->adev;
2296 u32 reg, gfxoff_status;
2297
2298 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
2299 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
2300 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
2301
2302 return gfxoff_status;
2303 }
2304
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2305 static int vangogh_get_power_limit(struct smu_context *smu,
2306 uint32_t *current_power_limit,
2307 uint32_t *default_power_limit,
2308 uint32_t *max_power_limit,
2309 uint32_t *min_power_limit)
2310 {
2311 struct smu_11_5_power_context *power_context =
2312 smu->smu_power.power_context;
2313 uint32_t ppt_limit;
2314 int ret = 0;
2315
2316 if (smu->adev->pm.fw_version < 0x43f1e00)
2317 return ret;
2318
2319 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2320 if (ret) {
2321 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2322 return ret;
2323 }
2324 /* convert from milliwatt to watt */
2325 if (current_power_limit)
2326 *current_power_limit = ppt_limit / 1000;
2327 if (default_power_limit)
2328 *default_power_limit = ppt_limit / 1000;
2329 if (max_power_limit)
2330 *max_power_limit = 29;
2331 if (min_power_limit)
2332 *min_power_limit = 0;
2333
2334 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2335 if (ret) {
2336 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2337 return ret;
2338 }
2339 /* convert from milliwatt to watt */
2340 power_context->current_fast_ppt_limit =
2341 power_context->default_fast_ppt_limit = ppt_limit / 1000;
2342 power_context->max_fast_ppt_limit = 30;
2343
2344 return ret;
2345 }
2346
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2347 static int vangogh_get_ppt_limit(struct smu_context *smu,
2348 uint32_t *ppt_limit,
2349 enum smu_ppt_limit_type type,
2350 enum smu_ppt_limit_level level)
2351 {
2352 struct smu_11_5_power_context *power_context =
2353 smu->smu_power.power_context;
2354
2355 if (!power_context)
2356 return -EOPNOTSUPP;
2357
2358 if (type == SMU_FAST_PPT_LIMIT) {
2359 switch (level) {
2360 case SMU_PPT_LIMIT_MAX:
2361 *ppt_limit = power_context->max_fast_ppt_limit;
2362 break;
2363 case SMU_PPT_LIMIT_CURRENT:
2364 *ppt_limit = power_context->current_fast_ppt_limit;
2365 break;
2366 case SMU_PPT_LIMIT_DEFAULT:
2367 *ppt_limit = power_context->default_fast_ppt_limit;
2368 break;
2369 default:
2370 break;
2371 }
2372 }
2373
2374 return 0;
2375 }
2376
vangogh_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t ppt_limit)2377 static int vangogh_set_power_limit(struct smu_context *smu,
2378 enum smu_ppt_limit_type limit_type,
2379 uint32_t ppt_limit)
2380 {
2381 struct smu_11_5_power_context *power_context =
2382 smu->smu_power.power_context;
2383 int ret = 0;
2384
2385 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2386 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2387 return -EOPNOTSUPP;
2388 }
2389
2390 switch (limit_type) {
2391 case SMU_DEFAULT_PPT_LIMIT:
2392 ret = smu_cmn_send_smc_msg_with_param(smu,
2393 SMU_MSG_SetSlowPPTLimit,
2394 ppt_limit * 1000, /* convert from watt to milliwatt */
2395 NULL);
2396 if (ret)
2397 return ret;
2398
2399 smu->current_power_limit = ppt_limit;
2400 break;
2401 case SMU_FAST_PPT_LIMIT:
2402 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2403 if (ppt_limit > power_context->max_fast_ppt_limit) {
2404 dev_err(smu->adev->dev,
2405 "New power limit (%d) is over the max allowed %d\n",
2406 ppt_limit, power_context->max_fast_ppt_limit);
2407 return ret;
2408 }
2409
2410 ret = smu_cmn_send_smc_msg_with_param(smu,
2411 SMU_MSG_SetFastPPTLimit,
2412 ppt_limit * 1000, /* convert from watt to milliwatt */
2413 NULL);
2414 if (ret)
2415 return ret;
2416
2417 power_context->current_fast_ppt_limit = ppt_limit;
2418 break;
2419 default:
2420 return -EINVAL;
2421 }
2422
2423 return ret;
2424 }
2425
2426 /**
2427 * vangogh_set_gfxoff_residency
2428 *
2429 * @smu: amdgpu_device pointer
2430 * @start: start/stop residency log
2431 *
2432 * This function will be used to log gfxoff residency
2433 *
2434 *
2435 * Returns standard response codes.
2436 */
vangogh_set_gfxoff_residency(struct smu_context * smu,bool start)2437 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
2438 {
2439 int ret = 0;
2440 u32 residency;
2441 struct amdgpu_device *adev = smu->adev;
2442
2443 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2444 return 0;
2445
2446 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
2447 start, &residency);
2448 if (ret)
2449 return ret;
2450
2451 if (!start)
2452 adev->gfx.gfx_off_residency = residency;
2453
2454 return ret;
2455 }
2456
2457 /**
2458 * vangogh_get_gfxoff_residency
2459 *
2460 * @smu: amdgpu_device pointer
2461 * @residency: placeholder for return value
2462 *
2463 * This function will be used to get gfxoff residency.
2464 *
2465 * Returns standard response codes.
2466 */
vangogh_get_gfxoff_residency(struct smu_context * smu,uint32_t * residency)2467 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
2468 {
2469 struct amdgpu_device *adev = smu->adev;
2470
2471 *residency = adev->gfx.gfx_off_residency;
2472
2473 return 0;
2474 }
2475
2476 /**
2477 * vangogh_get_gfxoff_entrycount - get gfxoff entry count
2478 *
2479 * @smu: amdgpu_device pointer
2480 * @entrycount: placeholder for return value
2481 *
2482 * This function will be used to get gfxoff entry count
2483 *
2484 * Returns standard response codes.
2485 */
vangogh_get_gfxoff_entrycount(struct smu_context * smu,uint64_t * entrycount)2486 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
2487 {
2488 int ret = 0, value = 0;
2489 struct amdgpu_device *adev = smu->adev;
2490
2491 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2492 return 0;
2493
2494 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
2495 *entrycount = value + adev->gfx.gfx_off_entrycount;
2496
2497 return ret;
2498 }
2499
2500 static const struct pptable_funcs vangogh_ppt_funcs = {
2501
2502 .check_fw_status = smu_v11_0_check_fw_status,
2503 .check_fw_version = smu_v11_0_check_fw_version,
2504 .init_smc_tables = vangogh_init_smc_tables,
2505 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2506 .init_power = smu_v11_0_init_power,
2507 .fini_power = smu_v11_0_fini_power,
2508 .register_irq_handler = smu_v11_0_register_irq_handler,
2509 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2510 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2511 .send_smc_msg = smu_cmn_send_smc_msg,
2512 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2513 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2514 .is_dpm_running = vangogh_is_dpm_running,
2515 .read_sensor = vangogh_read_sensor,
2516 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
2517 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
2518 .get_enabled_mask = smu_cmn_get_enabled_mask,
2519 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2520 .set_watermarks_table = vangogh_set_watermarks_table,
2521 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2522 .interrupt_work = smu_v11_0_interrupt_work,
2523 .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2524 .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2525 .print_clk_levels = vangogh_common_print_clk_levels,
2526 .set_default_dpm_table = vangogh_set_default_dpm_tables,
2527 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2528 .notify_rlc_state = vangogh_notify_rlc_state,
2529 .feature_is_enabled = smu_cmn_feature_is_enabled,
2530 .set_power_profile_mode = vangogh_set_power_profile_mode,
2531 .get_power_profile_mode = vangogh_get_power_profile_mode,
2532 .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2533 .force_clk_levels = vangogh_force_clk_levels,
2534 .set_performance_level = vangogh_set_performance_level,
2535 .post_init = vangogh_post_smu_init,
2536 .mode2_reset = vangogh_mode2_reset,
2537 .gfx_off_control = smu_v11_0_gfx_off_control,
2538 .get_gfx_off_status = vangogh_get_gfxoff_status,
2539 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
2540 .get_gfx_off_residency = vangogh_get_gfxoff_residency,
2541 .set_gfx_off_residency = vangogh_set_gfxoff_residency,
2542 .get_ppt_limit = vangogh_get_ppt_limit,
2543 .get_power_limit = vangogh_get_power_limit,
2544 .set_power_limit = vangogh_set_power_limit,
2545 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2546 };
2547
vangogh_set_ppt_funcs(struct smu_context * smu)2548 void vangogh_set_ppt_funcs(struct smu_context *smu)
2549 {
2550 smu->ppt_funcs = &vangogh_ppt_funcs;
2551 smu->message_map = vangogh_message_map;
2552 smu->feature_map = vangogh_feature_mask_map;
2553 smu->table_map = vangogh_table_map;
2554 smu->workload_map = vangogh_workload_map;
2555 smu->is_apu = true;
2556 smu_v11_0_set_smu_mailbox_registers(smu);
2557 }
2558