1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifndef __AMDGPU_RESET_H__
25 #define __AMDGPU_RESET_H__
26
27 #include "amdgpu.h"
28
29 #define AMDGPU_RESET_MAX_HANDLERS 5
30
31 enum AMDGPU_RESET_FLAGS {
32
33 AMDGPU_NEED_FULL_RESET = 0,
34 AMDGPU_SKIP_HW_RESET = 1,
35 AMDGPU_SKIP_COREDUMP = 2,
36 AMDGPU_HOST_FLR = 3,
37 };
38
39 enum AMDGPU_RESET_SRCS {
40 AMDGPU_RESET_SRC_UNKNOWN,
41 AMDGPU_RESET_SRC_JOB,
42 AMDGPU_RESET_SRC_RAS,
43 AMDGPU_RESET_SRC_MES,
44 AMDGPU_RESET_SRC_HWS,
45 AMDGPU_RESET_SRC_USER,
46 AMDGPU_RESET_SRC_USERQ,
47 };
48
49 struct amdgpu_reset_context {
50 enum amd_reset_method method;
51 struct amdgpu_device *reset_req_dev;
52 struct amdgpu_job *job;
53 struct amdgpu_hive_info *hive;
54 struct list_head *reset_device_list;
55 unsigned long flags;
56 enum AMDGPU_RESET_SRCS src;
57 };
58
59 struct amdgpu_reset_handler {
60 enum amd_reset_method reset_method;
61 int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
62 struct amdgpu_reset_context *context);
63 int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
64 struct amdgpu_reset_context *context);
65 int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
66 struct amdgpu_reset_context *context);
67 int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
68 struct amdgpu_reset_context *context);
69 int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
70 struct amdgpu_reset_context *context);
71
72 int (*do_reset)(struct amdgpu_device *adev);
73 };
74
75 struct amdgpu_reset_control {
76 void *handle;
77 struct work_struct reset_work;
78 struct mutex reset_lock;
79 struct amdgpu_reset_handler *(
80 *reset_handlers)[AMDGPU_RESET_MAX_HANDLERS];
81 atomic_t in_reset;
82 enum amd_reset_method active_reset;
83 struct amdgpu_reset_handler *(*get_reset_handler)(
84 struct amdgpu_reset_control *reset_ctl,
85 struct amdgpu_reset_context *context);
86 void (*async_reset)(struct work_struct *work);
87 };
88
89
90 enum amdgpu_reset_domain_type {
91 SINGLE_DEVICE,
92 XGMI_HIVE
93 };
94
95 struct amdgpu_reset_domain {
96 struct kref refcount;
97 struct workqueue_struct *wq;
98 enum amdgpu_reset_domain_type type;
99 struct rw_semaphore sem;
100 atomic_t in_gpu_reset;
101 atomic_t reset_res;
102 };
103
104 int amdgpu_reset_init(struct amdgpu_device *adev);
105 int amdgpu_reset_fini(struct amdgpu_device *adev);
106
107 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
108 struct amdgpu_reset_context *reset_context);
109
110 int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
111 struct amdgpu_reset_context *reset_context);
112
113 int amdgpu_reset_prepare_env(struct amdgpu_device *adev,
114 struct amdgpu_reset_context *reset_context);
115 int amdgpu_reset_restore_env(struct amdgpu_device *adev,
116 struct amdgpu_reset_context *reset_context);
117
118 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
119 char *wq_name);
120
121 void amdgpu_reset_destroy_reset_domain(struct kref *ref);
122
amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain * domain)123 static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
124 {
125 return kref_get_unless_zero(&domain->refcount) != 0;
126 }
127
amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain * domain)128 static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
129 {
130 if (domain)
131 kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
132 }
133
amdgpu_reset_domain_schedule(struct amdgpu_reset_domain * domain,struct work_struct * work)134 static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
135 struct work_struct *work)
136 {
137 return queue_work(domain->wq, work);
138 }
139
amdgpu_reset_pending(struct amdgpu_reset_domain * domain)140 static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain)
141 {
142 lockdep_assert_held(&domain->sem);
143 return rwsem_is_contended(&domain->sem);
144 }
145
146 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
147
148 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
149
150 void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,
151 size_t len);
152
153 #define for_each_handler(i, handler, reset_ctl) \
154 for (i = 0; (i < AMDGPU_RESET_MAX_HANDLERS) && \
155 (handler = (*reset_ctl->reset_handlers)[i]); \
156 ++i)
157
158 extern struct amdgpu_reset_handler xgmi_reset_on_init_handler;
159 int amdgpu_reset_do_xgmi_reset_on_init(
160 struct amdgpu_reset_context *reset_context);
161
162 bool amdgpu_reset_in_recovery(struct amdgpu_device *adev);
163
amdgpu_reset_set_dpc_status(struct amdgpu_device * adev,bool status)164 static inline void amdgpu_reset_set_dpc_status(struct amdgpu_device *adev,
165 bool status)
166 {
167 adev->pcie_reset_ctx.occurs_dpc = status;
168 adev->no_hw_access = status;
169 }
170
amdgpu_reset_in_dpc(struct amdgpu_device * adev)171 static inline bool amdgpu_reset_in_dpc(struct amdgpu_device *adev)
172 {
173 return adev->pcie_reset_ctx.occurs_dpc;
174 }
175
176 #endif
177