1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SG2042 MSI Controller
4 *
5 * Copyright (C) 2024 Sophgo Technology Inc.
6 * Copyright (C) 2024 Chen Wang <unicorn_wang@outlook.com>
7 */
8
9 #include <linux/cleanup.h>
10 #include <linux/io.h>
11 #include <linux/irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/msi.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/slab.h>
19
20 #include <linux/irqchip/irq-msi-lib.h>
21
22 struct sg204x_msi_chip_info {
23 const struct irq_chip *irqchip;
24 const struct msi_parent_ops *parent_ops;
25 };
26
27 /**
28 * struct sg204x_msi_chipdata - chip data for the SG204x MSI IRQ controller
29 * @reg_clr: clear reg, see TRM, 10.1.33, GP_INTR0_CLR
30 * @doorbell_addr: see TRM, 10.1.32, GP_INTR0_SET
31 * @irq_first: First vectors number that MSIs starts
32 * @num_irqs: Number of vectors for MSIs
33 * @msi_map: mapping for allocated MSI vectors.
34 * @msi_map_lock: Lock for msi_map
35 * @chip_info: chip specific infomations
36 */
37 struct sg204x_msi_chipdata {
38 void __iomem *reg_clr;
39
40 phys_addr_t doorbell_addr;
41
42 u32 irq_first;
43 u32 num_irqs;
44
45 unsigned long *msi_map;
46 struct mutex msi_map_lock;
47
48 const struct sg204x_msi_chip_info *chip_info;
49 };
50
sg204x_msi_allocate_hwirq(struct sg204x_msi_chipdata * data,int num_req)51 static int sg204x_msi_allocate_hwirq(struct sg204x_msi_chipdata *data, int num_req)
52 {
53 int first;
54
55 guard(mutex)(&data->msi_map_lock);
56 first = bitmap_find_free_region(data->msi_map, data->num_irqs,
57 get_count_order(num_req));
58 return first >= 0 ? first : -ENOSPC;
59 }
60
sg204x_msi_free_hwirq(struct sg204x_msi_chipdata * data,int hwirq,int num_req)61 static void sg204x_msi_free_hwirq(struct sg204x_msi_chipdata *data, int hwirq, int num_req)
62 {
63 guard(mutex)(&data->msi_map_lock);
64 bitmap_release_region(data->msi_map, hwirq, get_count_order(num_req));
65 }
66
sg2042_msi_irq_ack(struct irq_data * d)67 static void sg2042_msi_irq_ack(struct irq_data *d)
68 {
69 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
70 int bit_off = d->hwirq;
71
72 writel(1 << bit_off, data->reg_clr);
73
74 irq_chip_ack_parent(d);
75 }
76
sg2042_msi_irq_compose_msi_msg(struct irq_data * d,struct msi_msg * msg)77 static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
78 {
79 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
80
81 msg->address_hi = upper_32_bits(data->doorbell_addr);
82 msg->address_lo = lower_32_bits(data->doorbell_addr);
83 msg->data = 1 << d->hwirq;
84 }
85
86 static const struct irq_chip sg2042_msi_middle_irq_chip = {
87 .name = "SG2042 MSI",
88 .irq_ack = sg2042_msi_irq_ack,
89 .irq_mask = irq_chip_mask_parent,
90 .irq_unmask = irq_chip_unmask_parent,
91 #ifdef CONFIG_SMP
92 .irq_set_affinity = irq_chip_set_affinity_parent,
93 #endif
94 .irq_compose_msi_msg = sg2042_msi_irq_compose_msi_msg,
95 };
96
sg2044_msi_irq_ack(struct irq_data * d)97 static void sg2044_msi_irq_ack(struct irq_data *d)
98 {
99 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
100
101 writel(0, (u32 __iomem *)data->reg_clr + d->hwirq);
102 irq_chip_ack_parent(d);
103 }
104
sg2044_msi_irq_compose_msi_msg(struct irq_data * d,struct msi_msg * msg)105 static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
106 {
107 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
108 phys_addr_t doorbell = data->doorbell_addr + 4 * (d->hwirq / 32);
109
110 msg->address_lo = lower_32_bits(doorbell);
111 msg->address_hi = upper_32_bits(doorbell);
112 msg->data = d->hwirq % 32;
113 }
114
115 static struct irq_chip sg2044_msi_middle_irq_chip = {
116 .name = "SG2044 MSI",
117 .irq_ack = sg2044_msi_irq_ack,
118 .irq_mask = irq_chip_mask_parent,
119 .irq_unmask = irq_chip_unmask_parent,
120 #ifdef CONFIG_SMP
121 .irq_set_affinity = irq_chip_set_affinity_parent,
122 #endif
123 .irq_compose_msi_msg = sg2044_msi_irq_compose_msi_msg,
124 };
125
sg204x_msi_parent_domain_alloc(struct irq_domain * domain,unsigned int virq,int hwirq)126 static int sg204x_msi_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, int hwirq)
127 {
128 struct sg204x_msi_chipdata *data = domain->host_data;
129 struct irq_fwspec fwspec;
130 struct irq_data *d;
131 int ret;
132
133 fwspec.fwnode = domain->parent->fwnode;
134 fwspec.param_count = 2;
135 fwspec.param[0] = data->irq_first + hwirq;
136 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
137
138 ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
139 if (ret)
140 return ret;
141
142 d = irq_domain_get_irq_data(domain->parent, virq);
143 return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
144 }
145
sg204x_msi_middle_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)146 static int sg204x_msi_middle_domain_alloc(struct irq_domain *domain, unsigned int virq,
147 unsigned int nr_irqs, void *args)
148 {
149 struct sg204x_msi_chipdata *data = domain->host_data;
150 int hwirq, err, i;
151
152 hwirq = sg204x_msi_allocate_hwirq(data, nr_irqs);
153 if (hwirq < 0)
154 return hwirq;
155
156 for (i = 0; i < nr_irqs; i++) {
157 err = sg204x_msi_parent_domain_alloc(domain, virq + i, hwirq + i);
158 if (err)
159 goto err_hwirq;
160
161 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
162 data->chip_info->irqchip, data);
163 }
164 return 0;
165
166 err_hwirq:
167 sg204x_msi_free_hwirq(data, hwirq, nr_irqs);
168 irq_domain_free_irqs_parent(domain, virq, i);
169 return err;
170 }
171
sg204x_msi_middle_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)172 static void sg204x_msi_middle_domain_free(struct irq_domain *domain, unsigned int virq,
173 unsigned int nr_irqs)
174 {
175 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
176 struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
177
178 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
179 sg204x_msi_free_hwirq(data, d->hwirq, nr_irqs);
180 }
181
182 static const struct irq_domain_ops sg204x_msi_middle_domain_ops = {
183 .alloc = sg204x_msi_middle_domain_alloc,
184 .free = sg204x_msi_middle_domain_free,
185 .select = msi_lib_irq_domain_select,
186 };
187
188 #define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
189 MSI_FLAG_USE_DEF_CHIP_OPS)
190
191 #define SG2042_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK
192
193 static const struct msi_parent_ops sg2042_msi_parent_ops = {
194 .required_flags = SG2042_MSI_FLAGS_REQUIRED,
195 .supported_flags = SG2042_MSI_FLAGS_SUPPORTED,
196 .chip_flags = MSI_CHIP_FLAG_SET_ACK,
197 .bus_select_mask = MATCH_PCI_MSI,
198 .bus_select_token = DOMAIN_BUS_NEXUS,
199 .prefix = "SG2042-",
200 .init_dev_msi_info = msi_lib_init_dev_msi_info,
201 };
202
203 #define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
204 MSI_FLAG_USE_DEF_CHIP_OPS)
205
206 #define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \
207 MSI_FLAG_PCI_MSIX)
208
209 static const struct msi_parent_ops sg2044_msi_parent_ops = {
210 .required_flags = SG2044_MSI_FLAGS_REQUIRED,
211 .supported_flags = SG2044_MSI_FLAGS_SUPPORTED,
212 .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK,
213 .bus_select_mask = MATCH_PCI_MSI,
214 .bus_select_token = DOMAIN_BUS_NEXUS,
215 .prefix = "SG2044-",
216 .init_dev_msi_info = msi_lib_init_dev_msi_info,
217 };
218
sg204x_msi_init_domains(struct sg204x_msi_chipdata * data,struct irq_domain * plic_domain,struct device * dev)219 static int sg204x_msi_init_domains(struct sg204x_msi_chipdata *data,
220 struct irq_domain *plic_domain, struct device *dev)
221 {
222 struct irq_domain_info info = {
223 .ops = &sg204x_msi_middle_domain_ops,
224 .parent = plic_domain,
225 .size = data->num_irqs,
226 .fwnode = dev_fwnode(dev),
227 .host_data = data,
228 };
229
230 if (!msi_create_parent_irq_domain(&info, data->chip_info->parent_ops)) {
231 pr_err("Failed to create the MSI middle domain\n");
232 return -ENOMEM;
233 }
234 return 0;
235 }
236
sg2042_msi_probe(struct platform_device * pdev)237 static int sg2042_msi_probe(struct platform_device *pdev)
238 {
239 struct fwnode_reference_args args = { };
240 struct sg204x_msi_chipdata *data;
241 struct device *dev = &pdev->dev;
242 struct irq_domain *plic_domain;
243 struct resource *res;
244 int ret;
245
246 data = devm_kzalloc(dev, sizeof(struct sg204x_msi_chipdata), GFP_KERNEL);
247 if (!data)
248 return -ENOMEM;
249
250 data->chip_info = device_get_match_data(&pdev->dev);
251 if (!data->chip_info) {
252 dev_err(&pdev->dev, "Failed to get irqchip\n");
253 return -EINVAL;
254 }
255
256 data->reg_clr = devm_platform_ioremap_resource_byname(pdev, "clr");
257 if (IS_ERR(data->reg_clr)) {
258 dev_err(dev, "Failed to map clear register\n");
259 return PTR_ERR(data->reg_clr);
260 }
261
262 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "doorbell");
263 if (!res) {
264 dev_err(dev, "Failed get resource from set\n");
265 return -EINVAL;
266 }
267 data->doorbell_addr = res->start;
268
269 ret = fwnode_property_get_reference_args(dev_fwnode(dev), "msi-ranges",
270 "#interrupt-cells", 0, 0, &args);
271 if (ret) {
272 dev_err(dev, "Unable to parse MSI vec base\n");
273 return ret;
274 }
275 fwnode_handle_put(args.fwnode);
276
277 ret = fwnode_property_get_reference_args(dev_fwnode(dev), "msi-ranges", NULL,
278 args.nargs + 1, 0, &args);
279 if (ret) {
280 dev_err(dev, "Unable to parse MSI vec number\n");
281 return ret;
282 }
283
284 plic_domain = irq_find_matching_fwnode(args.fwnode, DOMAIN_BUS_ANY);
285 fwnode_handle_put(args.fwnode);
286 if (!plic_domain) {
287 pr_err("Failed to find the PLIC domain\n");
288 return -ENXIO;
289 }
290
291 data->irq_first = (u32)args.args[0];
292 data->num_irqs = (u32)args.args[args.nargs - 1];
293
294 mutex_init(&data->msi_map_lock);
295
296 data->msi_map = devm_bitmap_zalloc(&pdev->dev, data->num_irqs, GFP_KERNEL);
297 if (!data->msi_map) {
298 dev_err(&pdev->dev, "Unable to allocate msi mapping\n");
299 return -ENOMEM;
300 }
301
302 return sg204x_msi_init_domains(data, plic_domain, dev);
303 }
304
305 static const struct sg204x_msi_chip_info sg2042_chip_info = {
306 .irqchip = &sg2042_msi_middle_irq_chip,
307 .parent_ops = &sg2042_msi_parent_ops,
308 };
309
310 static const struct sg204x_msi_chip_info sg2044_chip_info = {
311 .irqchip = &sg2044_msi_middle_irq_chip,
312 .parent_ops = &sg2044_msi_parent_ops,
313 };
314
315 static const struct of_device_id sg2042_msi_of_match[] = {
316 { .compatible = "sophgo,sg2042-msi", .data = &sg2042_chip_info },
317 { .compatible = "sophgo,sg2044-msi", .data = &sg2044_chip_info },
318 { }
319 };
320
321 static struct platform_driver sg2042_msi_driver = {
322 .driver = {
323 .name = "sg2042-msi",
324 .of_match_table = sg2042_msi_of_match,
325 },
326 .probe = sg2042_msi_probe,
327 };
328 builtin_platform_driver(sg2042_msi_driver);
329