1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* Copyright(c) 2015-17 Intel Corporation. */ 3 4 #ifndef __SDW_INTEL_H 5 #define __SDW_INTEL_H 6 7 #include <linux/acpi.h> 8 #include <linux/irqreturn.h> 9 #include <linux/soundwire/sdw.h> 10 11 /********************************************************************* 12 * cAVS and ACE1.x definitions 13 *********************************************************************/ 14 15 #define SDW_SHIM_BASE 0x2C000 16 #define SDW_ALH_BASE 0x2C800 17 #define SDW_SHIM_BASE_ACE 0x38000 18 #define SDW_ALH_BASE_ACE 0x24000 19 #define SDW_LINK_BASE 0x30000 20 #define SDW_LINK_SIZE 0x10000 21 22 /* Intel SHIM Registers Definition */ 23 /* LCAP */ 24 #define SDW_SHIM_LCAP 0x0 25 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0) 26 #define SDW_SHIM_LCAP_MLCS_MASK BIT(8) 27 28 /* LCTL */ 29 #define SDW_SHIM_LCTL 0x4 30 31 #define SDW_SHIM_LCTL_SPA BIT(0) 32 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0) 33 #define SDW_SHIM_LCTL_CPA BIT(8) 34 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8) 35 #define SDW_SHIM_LCTL_MLCS_MASK GENMASK(29, 27) 36 #define SDW_SHIM_MLCS_XTAL_CLK 0x0 37 #define SDW_SHIM_MLCS_CARDINAL_CLK 0x1 38 #define SDW_SHIM_MLCS_AUDIO_PLL_CLK 0x2 39 40 /* SYNC */ 41 #define SDW_SHIM_SYNC 0xC 42 43 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1) 44 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576 (24576 / SDW_CADENCE_GSYNC_KHZ - 1) 45 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1) 46 #define SDW_SHIM_SYNC_SYNCPRD_VAL_96 (96000 / SDW_CADENCE_GSYNC_KHZ - 1) 47 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) 48 #define SDW_SHIM_SYNC_SYNCCPU BIT(15) 49 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) 50 #define SDW_SHIM_SYNC_CMDSYNC BIT(16) 51 #define SDW_SHIM_SYNC_SYNCGO BIT(24) 52 53 /* Control stream capabililities and channel mask */ 54 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 55 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 56 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 57 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 58 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 59 60 /* PCM Stream capabilities */ 61 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 62 63 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 64 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 65 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 66 67 /* PCM Stream Channel Map */ 68 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 69 70 /* PCM Stream Channel Count */ 71 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 72 73 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 74 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 75 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 76 #define SDW_SHIM_PCMSYCM_DIR BIT(15) 77 78 /* IO control */ 79 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 80 81 #define SDW_SHIM_IOCTL_MIF BIT(0) 82 #define SDW_SHIM_IOCTL_CO BIT(1) 83 #define SDW_SHIM_IOCTL_COE BIT(2) 84 #define SDW_SHIM_IOCTL_DO BIT(3) 85 #define SDW_SHIM_IOCTL_DOE BIT(4) 86 #define SDW_SHIM_IOCTL_BKE BIT(5) 87 #define SDW_SHIM_IOCTL_WPDD BIT(6) 88 #define SDW_SHIM_IOCTL_CIBD BIT(8) 89 #define SDW_SHIM_IOCTL_DIBD BIT(9) 90 91 /* Wake Enable*/ 92 #define SDW_SHIM_WAKEEN 0x190 93 94 #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 95 96 /* Wake Status */ 97 #define SDW_SHIM_WAKESTS 0x192 98 99 #define SDW_SHIM_WAKESTS_STATUS BIT(0) 100 101 /* AC Timing control */ 102 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 103 104 #define SDW_SHIM_CTMCTL_DACTQE BIT(0) 105 #define SDW_SHIM_CTMCTL_DODS BIT(1) 106 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 107 108 /* Intel ALH Register definitions */ 109 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) 110 #define SDW_ALH_NUM_STREAMS 64 111 112 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 113 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 114 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 115 116 /********************************************************************* 117 * ACE2.x definitions for SHIM registers - only accessible when the 118 * HDAudio extended link LCTL.SPA/CPA = 1. 119 *********************************************************************/ 120 /* x variable is link index */ 121 #define SDW_SHIM2_GENERIC_BASE(x) (0x00030000 + 0x8000 * (x)) 122 #define SDW_IP_BASE(x) (0x00030100 + 0x8000 * (x)) 123 #define SDW_SHIM2_VS_BASE(x) (0x00036000 + 0x8000 * (x)) 124 125 /* SHIM2 Generic Registers */ 126 /* Read-only capabilities */ 127 #define SDW_SHIM2_LECAP 0x00 128 #define SDW_SHIM2_LECAP_HDS BIT(0) /* unset -> Host mode */ 129 #define SDW_SHIM2_LECAP_MLC GENMASK(3, 1) /* Number of Lanes */ 130 131 /* PCM Stream capabilities */ 132 #define SDW_SHIM2_PCMSCAP 0x10 133 #define SDW_SHIM2_PCMSCAP_ISS GENMASK(3, 0) /* Input-only streams */ 134 #define SDW_SHIM2_PCMSCAP_OSS GENMASK(7, 4) /* Output-only streams */ 135 #define SDW_SHIM2_PCMSCAP_BSS GENMASK(12, 8) /* Bidirectional streams */ 136 137 /* Read-only PCM Stream Channel Count, y variable is stream */ 138 #define SDW_SHIM2_PCMSYCHC(y) (0x14 + (0x4 * (y))) 139 #define SDW_SHIM2_PCMSYCHC_CS GENMASK(3, 0) /* Channels Supported */ 140 141 /* PCM Stream Channel Map */ 142 #define SDW_SHIM2_PCMSYCHM(y) (0x16 + (0x4 * (y))) 143 #define SDW_SHIM2_PCMSYCHM_LCHAN GENMASK(3, 0) /* Lowest channel used by the FIFO port */ 144 #define SDW_SHIM2_PCMSYCHM_HCHAN GENMASK(7, 4) /* Lowest channel used by the FIFO port */ 145 #define SDW_SHIM2_PCMSYCHM_STRM GENMASK(13, 8) /* HDaudio stream tag */ 146 #define SDW_SHIM2_PCMSYCHM_DIR BIT(15) /* HDaudio stream direction */ 147 148 /* SHIM2 vendor-specific registers */ 149 #define SDW_SHIM2_INTEL_VS_LVSCTL 0x04 150 #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG BIT(26) 151 #define SDW_SHIM2_INTEL_VS_LVSCTL_MLCS GENMASK(29, 27) 152 #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD BIT(30) 153 #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD BIT(31) 154 155 #define SDW_SHIM2_MLCS_XTAL_CLK 0x0 156 #define SDW_SHIM2_MLCS_CARDINAL_CLK 0x1 157 #define SDW_SHIM2_MLCS_AUDIO_PLL_CLK 0x2 158 #define SDW_SHIM2_MLCS_MCLK_INPUT_CLK 0x3 159 #define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4 160 161 #define SDW_SHIM2_INTEL_VS_WAKEEN 0x08 162 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE BIT(0) 163 164 #define SDW_SHIM2_INTEL_VS_WAKESTS 0x0A 165 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS BIT(0) 166 167 #define SDW_SHIM2_INTEL_VS_IOCTL 0x0C 168 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF BIT(0) 169 #define SDW_SHIM2_INTEL_VS_IOCTL_CO BIT(1) 170 #define SDW_SHIM2_INTEL_VS_IOCTL_COE BIT(2) 171 #define SDW_SHIM2_INTEL_VS_IOCTL_DO BIT(3) 172 #define SDW_SHIM2_INTEL_VS_IOCTL_DOE BIT(4) 173 #define SDW_SHIM2_INTEL_VS_IOCTL_BKE BIT(5) 174 #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD BIT(6) 175 #define SDW_SHIM2_INTEL_VS_IOCTL_ODC BIT(7) 176 #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD BIT(8) 177 #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD BIT(9) 178 #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD BIT(10) 179 180 #define SDW_SHIM2_INTEL_VS_ACTMCTL 0x0E 181 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE BIT(0) 182 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS BIT(1) 183 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE BIT(2) 184 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS GENMASK(4, 3) 185 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE BIT(5) 186 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS BIT(6) 187 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS GENMASK(11, 7) 188 #define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2 GENMASK(13, 12) 189 #define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2 BIT(14) 190 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE BIT(15) 191 192 /** 193 * struct sdw_intel_stream_params_data: configuration passed during 194 * the @params_stream callback, e.g. for interaction with DSP 195 * firmware. 196 */ 197 struct sdw_intel_stream_params_data { 198 struct snd_pcm_substream *substream; 199 struct snd_soc_dai *dai; 200 struct snd_pcm_hw_params *hw_params; 201 int link_id; 202 int alh_stream_id; 203 }; 204 205 /** 206 * struct sdw_intel_stream_free_data: configuration passed during 207 * the @free_stream callback, e.g. for interaction with DSP 208 * firmware. 209 */ 210 struct sdw_intel_stream_free_data { 211 struct snd_pcm_substream *substream; 212 struct snd_soc_dai *dai; 213 int link_id; 214 }; 215 216 /** 217 * struct sdw_intel_ops: Intel audio driver callback ops 218 * 219 */ 220 struct sdw_intel_ops { 221 int (*params_stream)(struct device *dev, 222 struct sdw_intel_stream_params_data *params_data); 223 int (*free_stream)(struct device *dev, 224 struct sdw_intel_stream_free_data *free_data); 225 int (*trigger)(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai); 226 }; 227 228 /** 229 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables 230 * @handle: ACPI controller handle 231 * @count: link count found with "sdw-master-count" or "sdw-manager-list" property 232 * @link_mask: bit-wise mask listing links enabled by BIOS menu 233 * 234 * this structure could be expanded to e.g. provide all the _ADR 235 * information in case the link_mask is not sufficient to identify 236 * platform capabilities. 237 */ 238 struct sdw_intel_acpi_info { 239 acpi_handle handle; 240 int count; 241 u32 link_mask; 242 }; 243 244 struct sdw_intel_link_dev; 245 246 /* Intel clock-stop/pm_runtime quirk definitions */ 247 248 /* 249 * Force the clock to remain on during pm_runtime suspend. This might 250 * be needed if Slave devices do not have an alternate clock source or 251 * if the latency requirements are very strict. 252 */ 253 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0) 254 255 /* 256 * Stop the bus during pm_runtime suspend. If set, a complete bus 257 * reset and re-enumeration will be performed when the bus 258 * restarts. This mode shall not be used if Slave devices can generate 259 * in-band wakes. 260 */ 261 #define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1) 262 263 /* 264 * Stop the bus during pm_suspend if Slaves are not wake capable 265 * (e.g. speaker amplifiers). The clock-stop mode is typically 266 * slightly higher power than when the IP is completely powered-off. 267 */ 268 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2) 269 270 /* 271 * Require a bus reset (and complete re-enumeration) when exiting 272 * clock stop modes. This may be needed if the controller power was 273 * turned off and all context lost. This quirk shall not be used if a 274 * Slave device needs to remain enumerated and keep its context, 275 * e.g. to provide the reasons for the wake, report acoustic events or 276 * pass a history buffer. 277 */ 278 #define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3) 279 280 struct hdac_bus; 281 282 /** 283 * struct sdw_intel_ctx - context allocated by the controller 284 * driver probe 285 * @count: link count 286 * @mmio_base: mmio base of SoundWire registers, only used to check 287 * hardware capabilities after all power dependencies are settled. 288 * @link_mask: bit-wise mask listing SoundWire links reported by the 289 * Controller 290 * @handle: ACPI parent handle 291 * @ldev: information for each link (controller-specific and kept 292 * opaque here) 293 * @link_list: list to handle interrupts across all links 294 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers. 295 * @shim_mask: flags to track initialization of SHIM shared registers 296 * @shim_base: sdw shim base. 297 * @alh_base: sdw alh base. 298 * @peripherals: array representing Peripherals exposed across all enabled links 299 */ 300 struct sdw_intel_ctx { 301 int count; 302 void __iomem *mmio_base; 303 u32 link_mask; 304 acpi_handle handle; 305 struct sdw_intel_link_dev **ldev; 306 struct list_head link_list; 307 struct mutex shim_lock; /* lock for access to shared SHIM registers */ 308 u32 shim_mask; 309 u32 shim_base; 310 u32 alh_base; 311 struct sdw_peripherals *peripherals; 312 }; 313 314 /** 315 * struct sdw_intel_res - Soundwire Intel global resource structure, 316 * typically populated by the DSP driver 317 * 318 * @hw_ops: abstraction for platform ops 319 * @count: link count 320 * @mmio_base: mmio base of SoundWire registers 321 * @irq: interrupt number 322 * @handle: ACPI parent handle 323 * @parent: parent device 324 * @ops: callback ops 325 * @dev: device implementing hwparams and free callbacks 326 * @link_mask: bit-wise mask listing links selected by the DSP driver 327 * This mask may be a subset of the one reported by the controller since 328 * machine-specific quirks are handled in the DSP driver. 329 * @clock_stop_quirks: mask array of possible behaviors requested by the 330 * DSP driver. The quirks are common for all links for now. 331 * @shim_base: sdw shim base. 332 * @alh_base: sdw alh base. 333 * @ext: extended HDaudio link support 334 * @hbus: hdac_bus pointer, needed for power management 335 * @eml_lock: mutex protecting shared registers in the HDaudio multi-link 336 * space 337 */ 338 struct sdw_intel_res { 339 const struct sdw_intel_hw_ops *hw_ops; 340 int count; 341 void __iomem *mmio_base; 342 int irq; 343 acpi_handle handle; 344 struct device *parent; 345 const struct sdw_intel_ops *ops; 346 struct device *dev; 347 u32 link_mask; 348 u32 clock_stop_quirks; 349 u32 shim_base; 350 u32 alh_base; 351 bool ext; 352 struct hdac_bus *hbus; 353 struct mutex *eml_lock; 354 }; 355 356 /* 357 * On Intel platforms, the SoundWire IP has dependencies on power 358 * rails shared with the DSP, and the initialization steps are split 359 * in three. First an ACPI scan to check what the firmware describes 360 * in DSDT tables, then an allocation step (with no hardware 361 * configuration but with all the relevant devices created) and last 362 * the actual hardware configuration. The final stage is a global 363 * interrupt enable which is controlled by the DSP driver. Splitting 364 * these phases helps simplify the boot flow and make early decisions 365 * on e.g. which machine driver to select (I2S mode, HDaudio or 366 * SoundWire). 367 */ 368 int sdw_intel_acpi_scan(acpi_handle parent_handle, 369 struct sdw_intel_acpi_info *info); 370 371 void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx); 372 373 struct sdw_intel_ctx * 374 sdw_intel_probe(struct sdw_intel_res *res); 375 376 int sdw_intel_startup(struct sdw_intel_ctx *ctx); 377 378 void sdw_intel_exit(struct sdw_intel_ctx *ctx); 379 380 irqreturn_t sdw_intel_thread(int irq, void *dev_id); 381 382 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1) 383 384 struct sdw_intel; 385 386 /* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms. 387 * @debugfs_init: initialize all debugfs capabilities 388 * @debugfs_exit: close and cleanup debugfs capabilities 389 * @get_link_count: fetch link count from hardware registers 390 * @register_dai: read all PDI information and register DAIs 391 * @check_clock_stop: throw error message if clock is not stopped. 392 * @start_bus: normal start 393 * @start_bus_after_reset: start after reset 394 * @start_bus_after_clock_stop: start after mode0 clock stop 395 * @stop_bus: stop all bus 396 * @link_power_up: power-up using chip-specific helpers 397 * @link_power_down: power-down with chip-specific helpers 398 * @shim_check_wake: check if a wake was received 399 * @shim_wake: enable/disable in-band wake management 400 * @pre_bank_switch: helper for bus management 401 * @post_bank_switch: helper for bus management 402 * @sync_arm: helper for multi-link synchronization 403 * @sync_go_unlocked: helper for multi-link synchronization - 404 * shim_lock is assumed to be locked at higher level 405 * @sync_go: helper for multi-link synchronization 406 * @sync_check_cmdsync_unlocked: helper for multi-link synchronization 407 * and bank switch - shim_lock is assumed to be locked at higher level 408 * @program_sdi: helper for codec command/control based on dev_num 409 */ 410 struct sdw_intel_hw_ops { 411 void (*debugfs_init)(struct sdw_intel *sdw); 412 void (*debugfs_exit)(struct sdw_intel *sdw); 413 414 int (*get_link_count)(struct sdw_intel *sdw); 415 416 int (*register_dai)(struct sdw_intel *sdw); 417 418 void (*check_clock_stop)(struct sdw_intel *sdw); 419 int (*start_bus)(struct sdw_intel *sdw); 420 int (*start_bus_after_reset)(struct sdw_intel *sdw); 421 int (*start_bus_after_clock_stop)(struct sdw_intel *sdw); 422 int (*stop_bus)(struct sdw_intel *sdw, bool clock_stop); 423 424 int (*link_power_up)(struct sdw_intel *sdw); 425 int (*link_power_down)(struct sdw_intel *sdw); 426 427 int (*shim_check_wake)(struct sdw_intel *sdw); 428 void (*shim_wake)(struct sdw_intel *sdw, bool wake_enable); 429 430 int (*pre_bank_switch)(struct sdw_intel *sdw); 431 int (*post_bank_switch)(struct sdw_intel *sdw); 432 433 void (*sync_arm)(struct sdw_intel *sdw); 434 int (*sync_go_unlocked)(struct sdw_intel *sdw); 435 int (*sync_go)(struct sdw_intel *sdw); 436 bool (*sync_check_cmdsync_unlocked)(struct sdw_intel *sdw); 437 438 void (*program_sdi)(struct sdw_intel *sdw, int dev_num); 439 440 int (*bpt_send_async)(struct sdw_intel *sdw, struct sdw_slave *slave, 441 struct sdw_bpt_msg *msg); 442 int (*bpt_wait)(struct sdw_intel *sdw, struct sdw_slave *slave, struct sdw_bpt_msg *msg); 443 }; 444 445 extern const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops; 446 extern const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops; 447 448 /* 449 * IDA min selected to allow for 5 unconstrained devices per link, 450 * and 6 system-unique Device Numbers for wake-capable devices. 451 */ 452 453 #define SDW_INTEL_DEV_NUM_IDA_MIN 6 454 455 /* 456 * Max number of links supported in hardware 457 */ 458 #define SDW_INTEL_MAX_LINKS 5 459 460 #endif 461