1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2015 Regents of the University of California
4 * Copyright (c) 2020 Western Digital Corporation or its affiliates.
5 */
6
7 #ifndef _ASM_RISCV_SBI_H
8 #define _ASM_RISCV_SBI_H
9
10 #include <linux/types.h>
11 #include <linux/cpumask.h>
12 #include <linux/jump_label.h>
13
14 #ifdef CONFIG_RISCV_SBI
15 enum sbi_ext_id {
16 #ifdef CONFIG_RISCV_SBI_V01
17 SBI_EXT_0_1_SET_TIMER = 0x0,
18 SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
19 SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
20 SBI_EXT_0_1_CLEAR_IPI = 0x3,
21 SBI_EXT_0_1_SEND_IPI = 0x4,
22 SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
23 SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
24 SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
25 SBI_EXT_0_1_SHUTDOWN = 0x8,
26 #endif
27 SBI_EXT_BASE = 0x10,
28 SBI_EXT_TIME = 0x54494D45,
29 SBI_EXT_IPI = 0x735049,
30 SBI_EXT_RFENCE = 0x52464E43,
31 SBI_EXT_HSM = 0x48534D,
32 SBI_EXT_SRST = 0x53525354,
33 SBI_EXT_SUSP = 0x53555350,
34 SBI_EXT_PMU = 0x504D55,
35 SBI_EXT_DBCN = 0x4442434E,
36 SBI_EXT_STA = 0x535441,
37 SBI_EXT_NACL = 0x4E41434C,
38 SBI_EXT_FWFT = 0x46574654,
39 SBI_EXT_MPXY = 0x4D505859,
40
41 /* Experimentals extensions must lie within this range */
42 SBI_EXT_EXPERIMENTAL_START = 0x08000000,
43 SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
44
45 /* Vendor extensions must lie within this range */
46 SBI_EXT_VENDOR_START = 0x09000000,
47 SBI_EXT_VENDOR_END = 0x09FFFFFF,
48 };
49
50 enum sbi_ext_base_fid {
51 SBI_EXT_BASE_GET_SPEC_VERSION = 0,
52 SBI_EXT_BASE_GET_IMP_ID,
53 SBI_EXT_BASE_GET_IMP_VERSION,
54 SBI_EXT_BASE_PROBE_EXT,
55 SBI_EXT_BASE_GET_MVENDORID,
56 SBI_EXT_BASE_GET_MARCHID,
57 SBI_EXT_BASE_GET_MIMPID,
58 };
59
60 enum sbi_ext_time_fid {
61 SBI_EXT_TIME_SET_TIMER = 0,
62 };
63
64 enum sbi_ext_ipi_fid {
65 SBI_EXT_IPI_SEND_IPI = 0,
66 };
67
68 enum sbi_ext_rfence_fid {
69 SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
70 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
71 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
72 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
73 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
74 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
75 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
76 };
77
78 enum sbi_ext_hsm_fid {
79 SBI_EXT_HSM_HART_START = 0,
80 SBI_EXT_HSM_HART_STOP,
81 SBI_EXT_HSM_HART_STATUS,
82 SBI_EXT_HSM_HART_SUSPEND,
83 };
84
85 enum sbi_hsm_hart_state {
86 SBI_HSM_STATE_STARTED = 0,
87 SBI_HSM_STATE_STOPPED,
88 SBI_HSM_STATE_START_PENDING,
89 SBI_HSM_STATE_STOP_PENDING,
90 SBI_HSM_STATE_SUSPENDED,
91 SBI_HSM_STATE_SUSPEND_PENDING,
92 SBI_HSM_STATE_RESUME_PENDING,
93 };
94
95 #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
96 #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
97 #define SBI_HSM_SUSP_PLAT_BASE 0x10000000
98
99 #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
100 #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
101 #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
102 #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
103 #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
104 SBI_HSM_SUSP_PLAT_BASE)
105 #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
106 SBI_HSM_SUSP_BASE_MASK)
107
108 enum sbi_ext_srst_fid {
109 SBI_EXT_SRST_RESET = 0,
110 };
111
112 enum sbi_srst_reset_type {
113 SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
114 SBI_SRST_RESET_TYPE_COLD_REBOOT,
115 SBI_SRST_RESET_TYPE_WARM_REBOOT,
116 };
117
118 enum sbi_srst_reset_reason {
119 SBI_SRST_RESET_REASON_NONE = 0,
120 SBI_SRST_RESET_REASON_SYS_FAILURE,
121 };
122
123 enum sbi_ext_susp_fid {
124 SBI_EXT_SUSP_SYSTEM_SUSPEND = 0,
125 };
126
127 enum sbi_ext_susp_sleep_type {
128 SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0,
129 };
130
131 enum sbi_ext_pmu_fid {
132 SBI_EXT_PMU_NUM_COUNTERS = 0,
133 SBI_EXT_PMU_COUNTER_GET_INFO,
134 SBI_EXT_PMU_COUNTER_CFG_MATCH,
135 SBI_EXT_PMU_COUNTER_START,
136 SBI_EXT_PMU_COUNTER_STOP,
137 SBI_EXT_PMU_COUNTER_FW_READ,
138 SBI_EXT_PMU_COUNTER_FW_READ_HI,
139 SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
140 SBI_EXT_PMU_EVENT_GET_INFO,
141 };
142
143 union sbi_pmu_ctr_info {
144 unsigned long value;
145 struct {
146 unsigned long csr:12;
147 unsigned long width:6;
148 #if __riscv_xlen == 32
149 unsigned long reserved:13;
150 #else
151 unsigned long reserved:45;
152 #endif
153 unsigned long type:1;
154 };
155 };
156
157 /* Data structure to contain the pmu snapshot data */
158 struct riscv_pmu_snapshot_data {
159 u64 ctr_overflow_mask;
160 u64 ctr_values[64];
161 u64 reserved[447];
162 };
163
164 struct riscv_pmu_event_info {
165 u32 event_idx;
166 u32 output;
167 u64 event_data;
168 };
169
170 #define RISCV_PMU_EVENT_INFO_OUTPUT_MASK 0x01
171
172 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
173 #define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0)
174 /* SBI v3.0 allows extended hpmeventX width value */
175 #define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0)
176 #define RISCV_PMU_RAW_EVENT_IDX 0x20000
177 #define RISCV_PMU_RAW_EVENT_V2_IDX 0x30000
178 #define RISCV_PLAT_FW_EVENT 0xFFFF
179
180 /** General pmu event codes specified in SBI PMU extension */
181 enum sbi_pmu_hw_generic_events_t {
182 SBI_PMU_HW_NO_EVENT = 0,
183 SBI_PMU_HW_CPU_CYCLES = 1,
184 SBI_PMU_HW_INSTRUCTIONS = 2,
185 SBI_PMU_HW_CACHE_REFERENCES = 3,
186 SBI_PMU_HW_CACHE_MISSES = 4,
187 SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
188 SBI_PMU_HW_BRANCH_MISSES = 6,
189 SBI_PMU_HW_BUS_CYCLES = 7,
190 SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
191 SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
192 SBI_PMU_HW_REF_CPU_CYCLES = 10,
193
194 SBI_PMU_HW_GENERAL_MAX,
195 };
196
197 /**
198 * Special "firmware" events provided by the firmware, even if the hardware
199 * does not support performance events. These events are encoded as a raw
200 * event type in Linux kernel perf framework.
201 */
202 enum sbi_pmu_fw_generic_events_t {
203 SBI_PMU_FW_MISALIGNED_LOAD = 0,
204 SBI_PMU_FW_MISALIGNED_STORE = 1,
205 SBI_PMU_FW_ACCESS_LOAD = 2,
206 SBI_PMU_FW_ACCESS_STORE = 3,
207 SBI_PMU_FW_ILLEGAL_INSN = 4,
208 SBI_PMU_FW_SET_TIMER = 5,
209 SBI_PMU_FW_IPI_SENT = 6,
210 SBI_PMU_FW_IPI_RCVD = 7,
211 SBI_PMU_FW_FENCE_I_SENT = 8,
212 SBI_PMU_FW_FENCE_I_RCVD = 9,
213 SBI_PMU_FW_SFENCE_VMA_SENT = 10,
214 SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
215 SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
216 SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
217
218 SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
219 SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
220 SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
221 SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
222
223 SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
224 SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
225 SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
226 SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
227 SBI_PMU_FW_MAX,
228 };
229
230 /* SBI PMU event types */
231 enum sbi_pmu_event_type {
232 SBI_PMU_EVENT_TYPE_HW = 0x0,
233 SBI_PMU_EVENT_TYPE_CACHE = 0x1,
234 SBI_PMU_EVENT_TYPE_RAW = 0x2,
235 SBI_PMU_EVENT_TYPE_RAW_V2 = 0x3,
236 SBI_PMU_EVENT_TYPE_FW = 0xf,
237 };
238
239 /* SBI PMU event types */
240 enum sbi_pmu_ctr_type {
241 SBI_PMU_CTR_TYPE_HW = 0x0,
242 SBI_PMU_CTR_TYPE_FW,
243 };
244
245 /* Helper macros to decode event idx */
246 #define SBI_PMU_EVENT_IDX_OFFSET 20
247 #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
248 #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
249 #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
250 #define SBI_PMU_EVENT_RAW_IDX 0x20000
251 #define SBI_PMU_FIXED_CTR_MASK 0x07
252
253 #define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8
254 #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
255 #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
256
257 #define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
258 #define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
259
260 #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
261
262 /* Flags defined for config matching function */
263 #define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0)
264 #define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1)
265 #define SBI_PMU_CFG_FLAG_AUTO_START BIT(2)
266 #define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3)
267 #define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4)
268 #define SBI_PMU_CFG_FLAG_SET_UINH BIT(5)
269 #define SBI_PMU_CFG_FLAG_SET_SINH BIT(6)
270 #define SBI_PMU_CFG_FLAG_SET_MINH BIT(7)
271
272 /* Flags defined for counter start function */
273 #define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
274 #define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
275
276 /* Flags defined for counter stop function */
277 #define SBI_PMU_STOP_FLAG_RESET BIT(0)
278 #define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
279
280 enum sbi_ext_dbcn_fid {
281 SBI_EXT_DBCN_CONSOLE_WRITE = 0,
282 SBI_EXT_DBCN_CONSOLE_READ = 1,
283 SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
284 };
285
286 /* SBI STA (steal-time accounting) extension */
287 enum sbi_ext_sta_fid {
288 SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0,
289 };
290
291 struct sbi_sta_struct {
292 __le32 sequence;
293 __le32 flags;
294 __le64 steal;
295 u8 preempted;
296 u8 pad[47];
297 } __packed;
298
299 #define SBI_SHMEM_DISABLE -1
300
301 enum sbi_ext_nacl_fid {
302 SBI_EXT_NACL_PROBE_FEATURE = 0x0,
303 SBI_EXT_NACL_SET_SHMEM = 0x1,
304 SBI_EXT_NACL_SYNC_CSR = 0x2,
305 SBI_EXT_NACL_SYNC_HFENCE = 0x3,
306 SBI_EXT_NACL_SYNC_SRET = 0x4,
307 };
308
309 enum sbi_ext_nacl_feature {
310 SBI_NACL_FEAT_SYNC_CSR = 0x0,
311 SBI_NACL_FEAT_SYNC_HFENCE = 0x1,
312 SBI_NACL_FEAT_SYNC_SRET = 0x2,
313 SBI_NACL_FEAT_AUTOSWAP_CSR = 0x3,
314 };
315
316 #define SBI_NACL_SHMEM_ADDR_SHIFT 12
317 #define SBI_NACL_SHMEM_SCRATCH_OFFSET 0x0000
318 #define SBI_NACL_SHMEM_SCRATCH_SIZE 0x1000
319 #define SBI_NACL_SHMEM_SRET_OFFSET 0x0000
320 #define SBI_NACL_SHMEM_SRET_SIZE 0x0200
321 #define SBI_NACL_SHMEM_AUTOSWAP_OFFSET (SBI_NACL_SHMEM_SRET_OFFSET + \
322 SBI_NACL_SHMEM_SRET_SIZE)
323 #define SBI_NACL_SHMEM_AUTOSWAP_SIZE 0x0080
324 #define SBI_NACL_SHMEM_UNUSED_OFFSET (SBI_NACL_SHMEM_AUTOSWAP_OFFSET + \
325 SBI_NACL_SHMEM_AUTOSWAP_SIZE)
326 #define SBI_NACL_SHMEM_UNUSED_SIZE 0x0580
327 #define SBI_NACL_SHMEM_HFENCE_OFFSET (SBI_NACL_SHMEM_UNUSED_OFFSET + \
328 SBI_NACL_SHMEM_UNUSED_SIZE)
329 #define SBI_NACL_SHMEM_HFENCE_SIZE 0x0780
330 #define SBI_NACL_SHMEM_DBITMAP_OFFSET (SBI_NACL_SHMEM_HFENCE_OFFSET + \
331 SBI_NACL_SHMEM_HFENCE_SIZE)
332 #define SBI_NACL_SHMEM_DBITMAP_SIZE 0x0080
333 #define SBI_NACL_SHMEM_CSR_OFFSET (SBI_NACL_SHMEM_DBITMAP_OFFSET + \
334 SBI_NACL_SHMEM_DBITMAP_SIZE)
335 #define SBI_NACL_SHMEM_CSR_SIZE ((__riscv_xlen / 8) * 1024)
336 #define SBI_NACL_SHMEM_SIZE (SBI_NACL_SHMEM_CSR_OFFSET + \
337 SBI_NACL_SHMEM_CSR_SIZE)
338
339 #define SBI_NACL_SHMEM_CSR_INDEX(__csr_num) \
340 ((((__csr_num) & 0xc00) >> 2) | ((__csr_num) & 0xff))
341
342 #define SBI_NACL_SHMEM_HFENCE_ENTRY_SZ ((__riscv_xlen / 8) * 4)
343 #define SBI_NACL_SHMEM_HFENCE_ENTRY_MAX \
344 (SBI_NACL_SHMEM_HFENCE_SIZE / \
345 SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
346 #define SBI_NACL_SHMEM_HFENCE_ENTRY(__num) \
347 (SBI_NACL_SHMEM_HFENCE_OFFSET + \
348 (__num) * SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
349 #define SBI_NACL_SHMEM_HFENCE_ENTRY_CONFIG(__num) \
350 SBI_NACL_SHMEM_HFENCE_ENTRY(__num)
351 #define SBI_NACL_SHMEM_HFENCE_ENTRY_PNUM(__num)\
352 (SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + (__riscv_xlen / 8))
353 #define SBI_NACL_SHMEM_HFENCE_ENTRY_PCOUNT(__num)\
354 (SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + \
355 ((__riscv_xlen / 8) * 3))
356
357 #define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS 1
358 #define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT \
359 (__riscv_xlen - SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS)
360 #define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK \
361 ((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS) - 1)
362 #define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND \
363 (SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK << \
364 SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT)
365
366 #define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS 3
367 #define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT \
368 (SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT - \
369 SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS)
370
371 #define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS 4
372 #define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT \
373 (SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT - \
374 SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS)
375 #define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_MASK \
376 ((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS) - 1)
377
378 #define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA 0x0
379 #define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_ALL 0x1
380 #define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID 0x2
381 #define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID_ALL 0x3
382 #define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA 0x4
383 #define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ALL 0x5
384 #define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID 0x6
385 #define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID_ALL 0x7
386
387 #define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS 1
388 #define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT \
389 (SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT - \
390 SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS)
391
392 #define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS 7
393 #define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_SHIFT \
394 (SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT - \
395 SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS)
396 #define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_MASK \
397 ((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS) - 1)
398 #define SBI_NACL_SHMEM_HFENCE_ORDER_BASE 12
399
400 #if __riscv_xlen == 32
401 #define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 9
402 #define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 7
403 #else
404 #define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 16
405 #define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 14
406 #endif
407 #define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_SHIFT \
408 SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS
409 #define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_MASK \
410 ((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS) - 1)
411 #define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_MASK \
412 ((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS) - 1)
413
414 #define SBI_NACL_SHMEM_AUTOSWAP_FLAG_HSTATUS BIT(0)
415 #define SBI_NACL_SHMEM_AUTOSWAP_HSTATUS ((__riscv_xlen / 8) * 1)
416
417 #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
418 #define SBI_NACL_SHMEM_SRET_X_LAST 31
419
420 /* SBI function IDs for FW feature extension */
421 #define SBI_EXT_FWFT_SET 0x0
422 #define SBI_EXT_FWFT_GET 0x1
423
424 enum sbi_fwft_feature_t {
425 SBI_FWFT_MISALIGNED_EXC_DELEG = 0x0,
426 SBI_FWFT_LANDING_PAD = 0x1,
427 SBI_FWFT_SHADOW_STACK = 0x2,
428 SBI_FWFT_DOUBLE_TRAP = 0x3,
429 SBI_FWFT_PTE_AD_HW_UPDATING = 0x4,
430 SBI_FWFT_POINTER_MASKING_PMLEN = 0x5,
431 SBI_FWFT_LOCAL_RESERVED_START = 0x6,
432 SBI_FWFT_LOCAL_RESERVED_END = 0x3fffffff,
433 SBI_FWFT_LOCAL_PLATFORM_START = 0x40000000,
434 SBI_FWFT_LOCAL_PLATFORM_END = 0x7fffffff,
435
436 SBI_FWFT_GLOBAL_RESERVED_START = 0x80000000,
437 SBI_FWFT_GLOBAL_RESERVED_END = 0xbfffffff,
438 SBI_FWFT_GLOBAL_PLATFORM_START = 0xc0000000,
439 SBI_FWFT_GLOBAL_PLATFORM_END = 0xffffffff,
440 };
441
442 #define SBI_FWFT_PLATFORM_FEATURE_BIT BIT(30)
443 #define SBI_FWFT_GLOBAL_FEATURE_BIT BIT(31)
444
445 #define SBI_FWFT_SET_FLAG_LOCK BIT(0)
446
447 enum sbi_ext_mpxy_fid {
448 SBI_EXT_MPXY_GET_SHMEM_SIZE,
449 SBI_EXT_MPXY_SET_SHMEM,
450 SBI_EXT_MPXY_GET_CHANNEL_IDS,
451 SBI_EXT_MPXY_READ_ATTRS,
452 SBI_EXT_MPXY_WRITE_ATTRS,
453 SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
454 SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
455 SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS,
456 };
457
458 enum sbi_mpxy_attribute_id {
459 /* Standard channel attributes managed by MPXY framework */
460 SBI_MPXY_ATTR_MSG_PROT_ID = 0x00000000,
461 SBI_MPXY_ATTR_MSG_PROT_VER = 0x00000001,
462 SBI_MPXY_ATTR_MSG_MAX_LEN = 0x00000002,
463 SBI_MPXY_ATTR_MSG_SEND_TIMEOUT = 0x00000003,
464 SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT = 0x00000004,
465 SBI_MPXY_ATTR_CHANNEL_CAPABILITY = 0x00000005,
466 SBI_MPXY_ATTR_SSE_EVENT_ID = 0x00000006,
467 SBI_MPXY_ATTR_MSI_CONTROL = 0x00000007,
468 SBI_MPXY_ATTR_MSI_ADDR_LO = 0x00000008,
469 SBI_MPXY_ATTR_MSI_ADDR_HI = 0x00000009,
470 SBI_MPXY_ATTR_MSI_DATA = 0x0000000A,
471 SBI_MPXY_ATTR_EVENTS_STATE_CONTROL = 0x0000000B,
472 SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
473 /*
474 * Message protocol specific attributes, managed by
475 * the message protocol specification.
476 */
477 SBI_MPXY_ATTR_MSGPROTO_ATTR_START = 0x80000000,
478 SBI_MPXY_ATTR_MSGPROTO_ATTR_END = 0xffffffff
479 };
480
481 /* Possible values of MSG_PROT_ID attribute as-per SBI v3.0 (or higher) */
482 enum sbi_mpxy_msgproto_id {
483 SBI_MPXY_MSGPROTO_RPMI_ID = 0x0,
484 };
485
486 /* RPMI message protocol specific MPXY attributes */
487 enum sbi_mpxy_rpmi_attribute_id {
488 SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
489 SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
490 SBI_MPXY_RPMI_ATTR_IMPL_ID,
491 SBI_MPXY_RPMI_ATTR_IMPL_VERSION,
492 SBI_MPXY_RPMI_ATTR_MAX_ID
493 };
494
495 /* Encoding of MSG_PROT_VER attribute */
496 #define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver) upper_16_bits(__ver)
497 #define SBI_MPXY_MSG_PROT_VER_MINOR(__ver) lower_16_bits(__ver)
498 #define SBI_MPXY_MSG_PROT_MKVER(__maj, __min) (((u32)(__maj) << 16) | (u16)(__min))
499
500 /* Capabilities available through CHANNEL_CAPABILITY attribute */
501 #define SBI_MPXY_CHAN_CAP_MSI BIT(0)
502 #define SBI_MPXY_CHAN_CAP_SSE BIT(1)
503 #define SBI_MPXY_CHAN_CAP_EVENTS_STATE BIT(2)
504 #define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP BIT(3)
505 #define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP BIT(4)
506 #define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS BIT(5)
507
508 /* SBI spec version fields */
509 #define SBI_SPEC_VERSION_DEFAULT 0x1
510 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
511 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
512 #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
513
514 /* SBI return error codes */
515 #define SBI_SUCCESS 0
516 #define SBI_ERR_FAILURE -1
517 #define SBI_ERR_NOT_SUPPORTED -2
518 #define SBI_ERR_INVALID_PARAM -3
519 #define SBI_ERR_DENIED -4
520 #define SBI_ERR_INVALID_ADDRESS -5
521 #define SBI_ERR_ALREADY_AVAILABLE -6
522 #define SBI_ERR_ALREADY_STARTED -7
523 #define SBI_ERR_ALREADY_STOPPED -8
524 #define SBI_ERR_NO_SHMEM -9
525 #define SBI_ERR_INVALID_STATE -10
526 #define SBI_ERR_BAD_RANGE -11
527 #define SBI_ERR_TIMEOUT -12
528 #define SBI_ERR_IO -13
529 #define SBI_ERR_DENIED_LOCKED -14
530
531 extern unsigned long sbi_spec_version;
532 struct sbiret {
533 long error;
534 long value;
535 };
536
537 void sbi_init(void);
538 long __sbi_base_ecall(int fid);
539 struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
540 unsigned long arg2, unsigned long arg3,
541 unsigned long arg4, unsigned long arg5,
542 int fid, int ext);
543 #define sbi_ecall(e, f, a0, a1, a2, a3, a4, a5) \
544 __sbi_ecall(a0, a1, a2, a3, a4, a5, f, e)
545
546 #ifdef CONFIG_RISCV_SBI_V01
547 void sbi_console_putchar(int ch);
548 int sbi_console_getchar(void);
549 #else
sbi_console_putchar(int ch)550 static inline void sbi_console_putchar(int ch) { }
sbi_console_getchar(void)551 static inline int sbi_console_getchar(void) { return -ENOENT; }
552 #endif
553 long sbi_get_mvendorid(void);
554 long sbi_get_marchid(void);
555 long sbi_get_mimpid(void);
556 void sbi_set_timer(uint64_t stime_value);
557 void sbi_shutdown(void);
558 void sbi_send_ipi(unsigned int cpu);
559 int sbi_remote_fence_i(const struct cpumask *cpu_mask);
560
561 int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask,
562 unsigned long start,
563 unsigned long size,
564 unsigned long asid);
565 int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask,
566 unsigned long start,
567 unsigned long size);
568 int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask,
569 unsigned long start,
570 unsigned long size,
571 unsigned long vmid);
572 int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask,
573 unsigned long start,
574 unsigned long size);
575 int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
576 unsigned long start,
577 unsigned long size,
578 unsigned long asid);
579 long sbi_probe_extension(int ext);
580
581 int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags);
582 int sbi_fwft_set_cpumask(const cpumask_t *mask, u32 feature,
583 unsigned long value, unsigned long flags);
584 /**
585 * sbi_fwft_set_online_cpus() - Set a feature on all online cpus
586 * @feature: The feature to be set
587 * @value: The feature value to be set
588 * @flags: FWFT feature set flags
589 *
590 * Return: 0 on success, appropriate linux error code otherwise.
591 */
sbi_fwft_set_online_cpus(u32 feature,unsigned long value,unsigned long flags)592 static inline int sbi_fwft_set_online_cpus(u32 feature, unsigned long value,
593 unsigned long flags)
594 {
595 return sbi_fwft_set_cpumask(cpu_online_mask, feature, value, flags);
596 }
597
598 /* Check if current SBI specification version is 0.1 or not */
sbi_spec_is_0_1(void)599 static inline int sbi_spec_is_0_1(void)
600 {
601 return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
602 }
603
604 /* Get the major version of SBI */
sbi_major_version(void)605 static inline unsigned long sbi_major_version(void)
606 {
607 return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
608 SBI_SPEC_VERSION_MAJOR_MASK;
609 }
610
611 /* Get the minor version of SBI */
sbi_minor_version(void)612 static inline unsigned long sbi_minor_version(void)
613 {
614 return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
615 }
616
617 /* Make SBI version */
sbi_mk_version(unsigned long major,unsigned long minor)618 static inline unsigned long sbi_mk_version(unsigned long major,
619 unsigned long minor)
620 {
621 return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
622 | (minor & SBI_SPEC_VERSION_MINOR_MASK);
623 }
624
sbi_err_map_linux_errno(int err)625 static inline int sbi_err_map_linux_errno(int err)
626 {
627 switch (err) {
628 case SBI_SUCCESS:
629 return 0;
630 case SBI_ERR_DENIED:
631 case SBI_ERR_DENIED_LOCKED:
632 return -EPERM;
633 case SBI_ERR_INVALID_PARAM:
634 case SBI_ERR_INVALID_STATE:
635 return -EINVAL;
636 case SBI_ERR_BAD_RANGE:
637 return -ERANGE;
638 case SBI_ERR_INVALID_ADDRESS:
639 return -EFAULT;
640 case SBI_ERR_NO_SHMEM:
641 return -ENOMEM;
642 case SBI_ERR_TIMEOUT:
643 return -ETIMEDOUT;
644 case SBI_ERR_IO:
645 return -EIO;
646 case SBI_ERR_NOT_SUPPORTED:
647 case SBI_ERR_FAILURE:
648 default:
649 return -ENOTSUPP;
650 };
651 }
652
653 extern bool sbi_debug_console_available;
654 int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
655 int sbi_debug_console_read(char *bytes, unsigned int num_bytes);
656
657 #else /* CONFIG_RISCV_SBI */
sbi_remote_fence_i(const struct cpumask * cpu_mask)658 static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
sbi_init(void)659 static inline void sbi_init(void) {}
660 #endif /* CONFIG_RISCV_SBI */
661
662 unsigned long riscv_get_mvendorid(void);
663 unsigned long riscv_get_marchid(void);
664 unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
665 unsigned long riscv_cached_marchid(unsigned int cpu_id);
666 unsigned long riscv_cached_mimpid(unsigned int cpu_id);
667
668 #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)
669 DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence);
670 #define riscv_use_sbi_for_rfence() \
671 static_branch_unlikely(&riscv_sbi_for_rfence)
672 void sbi_ipi_init(void);
673 #else
riscv_use_sbi_for_rfence(void)674 static inline bool riscv_use_sbi_for_rfence(void) { return false; }
sbi_ipi_init(void)675 static inline void sbi_ipi_init(void) { }
676 #endif
677
678 #endif /* _ASM_RISCV_SBI_H */
679