1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Driver for Renesas RZ/G2L CRU 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8 #ifndef __RZG2L_CRU__ 9 #define __RZG2L_CRU__ 10 11 #include <linux/irqreturn.h> 12 #include <linux/reset.h> 13 14 #include <media/v4l2-async.h> 15 #include <media/v4l2-dev.h> 16 #include <media/v4l2-device.h> 17 #include <media/videobuf2-v4l2.h> 18 19 /* Number of HW buffers */ 20 #define RZG2L_CRU_HW_BUFFER_MAX 8 21 #define RZG2L_CRU_HW_BUFFER_DEFAULT 3 22 23 /* Address alignment mask for HW buffers */ 24 #define RZG2L_CRU_HW_BUFFER_MASK 0x1ff 25 26 /* Maximum number of CSI2 virtual channels */ 27 #define RZG2L_CRU_CSI2_VCHANNEL 4 28 29 #define RZG2L_CRU_MIN_INPUT_WIDTH 320 30 #define RZG2L_CRU_MIN_INPUT_HEIGHT 240 31 32 enum rzg2l_csi2_pads { 33 RZG2L_CRU_IP_SINK = 0, 34 RZG2L_CRU_IP_SOURCE, 35 }; 36 37 struct rzg2l_cru_dev; 38 39 /** 40 * enum rzg2l_cru_dma_state - DMA states 41 * @RZG2L_CRU_DMA_STOPPED: No operation in progress 42 * @RZG2L_CRU_DMA_STARTING: Capture starting up 43 * @RZG2L_CRU_DMA_RUNNING: Operation in progress have buffers 44 * @RZG2L_CRU_DMA_STOPPING: Stopping operation 45 */ 46 enum rzg2l_cru_dma_state { 47 RZG2L_CRU_DMA_STOPPED = 0, 48 RZG2L_CRU_DMA_STARTING, 49 RZG2L_CRU_DMA_RUNNING, 50 RZG2L_CRU_DMA_STOPPING, 51 }; 52 53 struct rzg2l_cru_csi { 54 struct v4l2_async_connection *asd; 55 struct v4l2_subdev *subdev; 56 }; 57 58 struct rzg2l_cru_ip { 59 struct v4l2_subdev subdev; 60 struct media_pad pads[2]; 61 struct v4l2_async_notifier notifier; 62 struct v4l2_subdev *remote; 63 }; 64 65 /** 66 * struct rzg2l_cru_ip_format - CRU IP format 67 * @codes: Array of up to four media bus codes 68 * @datatype: MIPI CSI2 data type 69 * @format: 4CC format identifier (V4L2_PIX_FMT_*) 70 * @icndmr: ICnDMR register value 71 * @yuv: Flag to indicate whether the format is YUV-based. 72 */ 73 struct rzg2l_cru_ip_format { 74 /* 75 * RAW output formats might be produced by RAW media codes with any one 76 * of the 4 common bayer patterns. 77 */ 78 u32 codes[4]; 79 u32 datatype; 80 u32 format; 81 u32 icndmr; 82 bool yuv; 83 }; 84 85 struct rzg2l_cru_info { 86 unsigned int max_width; 87 unsigned int max_height; 88 u16 image_conv; 89 const u16 *regs; 90 bool has_stride; 91 irqreturn_t (*irq_handler)(int irq, void *data); 92 void (*enable_interrupts)(struct rzg2l_cru_dev *cru); 93 void (*disable_interrupts)(struct rzg2l_cru_dev *cru); 94 bool (*fifo_empty)(struct rzg2l_cru_dev *cru); 95 void (*csi_setup)(struct rzg2l_cru_dev *cru, 96 const struct rzg2l_cru_ip_format *ip_fmt, 97 u8 csi_vc); 98 }; 99 100 /** 101 * struct rzg2l_cru_dev - Renesas CRU device structure 102 * @dev: (OF) device 103 * @base: device I/O register space remapped to virtual memory 104 * @info: info about CRU instance 105 * 106 * @presetn: CRU_PRESETN reset line 107 * @aresetn: CRU_ARESETN reset line 108 * 109 * @vclk: CRU Main clock 110 * 111 * @vdev: V4L2 video device associated with CRU 112 * @v4l2_dev: V4L2 device 113 * @num_buf: Holds the current number of buffers enabled 114 * @svc_channel: SVC0/1/2/3 to use for RZ/G3E 115 * @buf_addr: Memory addresses where current video data is written. 116 * @notifier: V4L2 asynchronous subdevs notifier 117 * 118 * @ip: Image processing subdev info 119 * @csi: CSI info 120 * @mdev: media device 121 * @mdev_lock: protects the count, notifier and csi members 122 * @pad: media pad for the video device entity 123 * 124 * @lock: protects @queue 125 * @queue: vb2 buffers queue 126 * @scratch: cpu address for scratch buffer 127 * @scratch_phys: physical address of the scratch buffer 128 * 129 * @qlock: protects @queue_buf, @buf_list, @sequence 130 * @state 131 * @queue_buf: Keeps track of buffers given to HW slot 132 * @buf_list: list of queued buffers 133 * @sequence: V4L2 buffers sequence number 134 * @state: keeps track of operation state 135 * 136 * @format: active V4L2 pixel format 137 */ 138 struct rzg2l_cru_dev { 139 struct device *dev; 140 void __iomem *base; 141 const struct rzg2l_cru_info *info; 142 143 struct reset_control *presetn; 144 struct reset_control *aresetn; 145 146 struct clk *vclk; 147 148 struct video_device vdev; 149 struct v4l2_device v4l2_dev; 150 u8 num_buf; 151 152 u8 svc_channel; 153 dma_addr_t buf_addr[RZG2L_CRU_HW_BUFFER_DEFAULT]; 154 155 struct v4l2_async_notifier notifier; 156 157 struct rzg2l_cru_ip ip; 158 struct rzg2l_cru_csi csi; 159 struct media_device mdev; 160 struct mutex mdev_lock; 161 struct media_pad pad; 162 163 struct mutex lock; 164 struct vb2_queue queue; 165 void *scratch; 166 dma_addr_t scratch_phys; 167 168 spinlock_t qlock; 169 struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX]; 170 struct list_head buf_list; 171 unsigned int sequence; 172 enum rzg2l_cru_dma_state state; 173 174 struct v4l2_pix_format format; 175 }; 176 177 int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru); 178 void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru); 179 180 int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru); 181 void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru); 182 183 int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru); 184 void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru); 185 irqreturn_t rzg2l_cru_irq(int irq, void *data); 186 irqreturn_t rzg3e_cru_irq(int irq, void *data); 187 188 const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format); 189 190 int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru); 191 void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru); 192 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru); 193 194 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code); 195 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_format_to_fmt(u32 format); 196 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_index_to_fmt(u32 index); 197 bool rzg2l_cru_ip_fmt_supports_mbus_code(const struct rzg2l_cru_ip_format *fmt, 198 unsigned int code); 199 200 void rzg2l_cru_enable_interrupts(struct rzg2l_cru_dev *cru); 201 void rzg2l_cru_disable_interrupts(struct rzg2l_cru_dev *cru); 202 void rzg3e_cru_enable_interrupts(struct rzg2l_cru_dev *cru); 203 void rzg3e_cru_disable_interrupts(struct rzg2l_cru_dev *cru); 204 205 bool rzg2l_fifo_empty(struct rzg2l_cru_dev *cru); 206 bool rzg3e_fifo_empty(struct rzg2l_cru_dev *cru); 207 void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, 208 const struct rzg2l_cru_ip_format *ip_fmt, 209 u8 csi_vc); 210 void rzg3e_cru_csi2_setup(struct rzg2l_cru_dev *cru, 211 const struct rzg2l_cru_ip_format *ip_fmt, 212 u8 csi_vc); 213 214 #endif 215