1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2024 NXP
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/device.h>
11 #include <linux/jiffies.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/units.h>
17
18 #include <drm/drm_modes.h>
19
20 #include "dc-de.h"
21 #include "dc-drv.h"
22
23 #define FGSTCTRL 0x8
24 #define FGSYNCMODE_MASK GENMASK(2, 1)
25 #define FGSYNCMODE(x) FIELD_PREP(FGSYNCMODE_MASK, (x))
26 #define SHDEN BIT(0)
27
28 #define HTCFG1 0xc
29 #define HTOTAL(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
30 #define HACT(x) FIELD_PREP(GENMASK(13, 0), (x))
31
32 #define HTCFG2 0x10
33 #define HSEN BIT(31)
34 #define HSBP(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
35 #define HSYNC(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1))
36
37 #define VTCFG1 0x14
38 #define VTOTAL(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
39 #define VACT(x) FIELD_PREP(GENMASK(13, 0), (x))
40
41 #define VTCFG2 0x18
42 #define VSEN BIT(31)
43 #define VSBP(x) FIELD_PREP(GENMASK(29, 16), ((x) - 1))
44 #define VSYNC(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1))
45
46 #define PKICKCONFIG 0x2c
47 #define SKICKCONFIG 0x30
48 #define EN BIT(31)
49 #define ROW(x) FIELD_PREP(GENMASK(29, 16), (x))
50 #define COL(x) FIELD_PREP(GENMASK(13, 0), (x))
51
52 #define PACFG 0x54
53 #define SACFG 0x58
54 #define STARTY(x) FIELD_PREP(GENMASK(29, 16), ((x) + 1))
55 #define STARTX(x) FIELD_PREP(GENMASK(13, 0), ((x) + 1))
56
57 #define FGINCTRL 0x5c
58 #define FGINCTRLPANIC 0x60
59 #define FGDM_MASK GENMASK(2, 0)
60 #define ENPRIMALPHA BIT(3)
61 #define ENSECALPHA BIT(4)
62
63 #define FGCCR 0x64
64 #define CCGREEN(x) FIELD_PREP(GENMASK(19, 10), (x))
65
66 #define FGENABLE 0x68
67 #define FGEN BIT(0)
68
69 #define FGSLR 0x6c
70 #define SHDTOKGEN BIT(0)
71
72 #define FGTIMESTAMP 0x74
73 #define FRAMEINDEX(x) FIELD_GET(GENMASK(31, 14), (x))
74 #define LINEINDEX(x) FIELD_GET(GENMASK(13, 0), (x))
75
76 #define FGCHSTAT 0x78
77 #define SECSYNCSTAT BIT(24)
78 #define SFIFOEMPTY BIT(16)
79
80 #define FGCHSTATCLR 0x7c
81 #define CLRSECSTAT BIT(16)
82
83 enum dc_fg_syncmode {
84 FG_SYNCMODE_OFF, /* No side-by-side synchronization. */
85 };
86
87 enum dc_fg_dm {
88 FG_DM_CONSTCOL = 0x1, /* Constant Color Background is shown. */
89 FG_DM_SEC_ON_TOP = 0x5, /* Both inputs overlaid with secondary on top. */
90 };
91
92 static const struct dc_subdev_info dc_fg_info[] = {
93 { .reg_start = 0x5618b800, .id = 0, },
94 { .reg_start = 0x5618d400, .id = 1, },
95 };
96
97 static const struct regmap_range dc_fg_regmap_write_ranges[] = {
98 regmap_reg_range(FGSTCTRL, VTCFG2),
99 regmap_reg_range(PKICKCONFIG, SKICKCONFIG),
100 regmap_reg_range(PACFG, FGSLR),
101 regmap_reg_range(FGCHSTATCLR, FGCHSTATCLR),
102 };
103
104 static const struct regmap_range dc_fg_regmap_read_ranges[] = {
105 regmap_reg_range(FGSTCTRL, VTCFG2),
106 regmap_reg_range(PKICKCONFIG, SKICKCONFIG),
107 regmap_reg_range(PACFG, FGENABLE),
108 regmap_reg_range(FGTIMESTAMP, FGCHSTAT),
109 };
110
111 static const struct regmap_access_table dc_fg_regmap_write_table = {
112 .yes_ranges = dc_fg_regmap_write_ranges,
113 .n_yes_ranges = ARRAY_SIZE(dc_fg_regmap_write_ranges),
114 };
115
116 static const struct regmap_access_table dc_fg_regmap_read_table = {
117 .yes_ranges = dc_fg_regmap_read_ranges,
118 .n_yes_ranges = ARRAY_SIZE(dc_fg_regmap_read_ranges),
119 };
120
121 static const struct regmap_config dc_fg_regmap_config = {
122 .reg_bits = 32,
123 .reg_stride = 4,
124 .val_bits = 32,
125 .fast_io = true,
126 .wr_table = &dc_fg_regmap_write_table,
127 .rd_table = &dc_fg_regmap_read_table,
128 .max_register = FGCHSTATCLR,
129 };
130
dc_fg_enable_shden(struct dc_fg * fg)131 static inline void dc_fg_enable_shden(struct dc_fg *fg)
132 {
133 regmap_write_bits(fg->reg, FGSTCTRL, SHDEN, SHDEN);
134 }
135
dc_fg_syncmode(struct dc_fg * fg,enum dc_fg_syncmode mode)136 static inline void dc_fg_syncmode(struct dc_fg *fg, enum dc_fg_syncmode mode)
137 {
138 regmap_write_bits(fg->reg, FGSTCTRL, FGSYNCMODE_MASK, FGSYNCMODE(mode));
139 }
140
dc_fg_cfg_videomode(struct dc_fg * fg,struct drm_display_mode * m)141 void dc_fg_cfg_videomode(struct dc_fg *fg, struct drm_display_mode *m)
142 {
143 u32 hact, htotal, hsync, hsbp;
144 u32 vact, vtotal, vsync, vsbp;
145 u32 kick_row, kick_col;
146 int ret;
147
148 hact = m->crtc_hdisplay;
149 htotal = m->crtc_htotal;
150 hsync = m->crtc_hsync_end - m->crtc_hsync_start;
151 hsbp = m->crtc_htotal - m->crtc_hsync_start;
152
153 vact = m->crtc_vdisplay;
154 vtotal = m->crtc_vtotal;
155 vsync = m->crtc_vsync_end - m->crtc_vsync_start;
156 vsbp = m->crtc_vtotal - m->crtc_vsync_start;
157
158 /* video mode */
159 regmap_write(fg->reg, HTCFG1, HACT(hact) | HTOTAL(htotal));
160 regmap_write(fg->reg, HTCFG2, HSYNC(hsync) | HSBP(hsbp) | HSEN);
161 regmap_write(fg->reg, VTCFG1, VACT(vact) | VTOTAL(vtotal));
162 regmap_write(fg->reg, VTCFG2, VSYNC(vsync) | VSBP(vsbp) | VSEN);
163
164 kick_col = hact + 1;
165 kick_row = vact;
166
167 /* pkickconfig */
168 regmap_write(fg->reg, PKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);
169
170 /* skikconfig */
171 regmap_write(fg->reg, SKICKCONFIG, COL(kick_col) | ROW(kick_row) | EN);
172
173 /* primary and secondary area position configuration */
174 regmap_write(fg->reg, PACFG, STARTX(0) | STARTY(0));
175 regmap_write(fg->reg, SACFG, STARTX(0) | STARTY(0));
176
177 /* alpha */
178 regmap_write_bits(fg->reg, FGINCTRL, ENPRIMALPHA | ENSECALPHA, 0);
179 regmap_write_bits(fg->reg, FGINCTRLPANIC, ENPRIMALPHA | ENSECALPHA, 0);
180
181 /* constant color is green(used in panic mode) */
182 regmap_write(fg->reg, FGCCR, CCGREEN(0x3ff));
183
184 ret = clk_set_rate(fg->clk_disp, m->clock * HZ_PER_KHZ);
185 if (ret < 0)
186 dev_err(fg->dev, "failed to set display clock rate: %d\n", ret);
187 }
188
dc_fg_displaymode(struct dc_fg * fg,enum dc_fg_dm mode)189 static inline void dc_fg_displaymode(struct dc_fg *fg, enum dc_fg_dm mode)
190 {
191 regmap_write_bits(fg->reg, FGINCTRL, FGDM_MASK, mode);
192 }
193
dc_fg_panic_displaymode(struct dc_fg * fg,enum dc_fg_dm mode)194 static inline void dc_fg_panic_displaymode(struct dc_fg *fg, enum dc_fg_dm mode)
195 {
196 regmap_write_bits(fg->reg, FGINCTRLPANIC, FGDM_MASK, mode);
197 }
198
dc_fg_enable(struct dc_fg * fg)199 void dc_fg_enable(struct dc_fg *fg)
200 {
201 regmap_write(fg->reg, FGENABLE, FGEN);
202 }
203
dc_fg_disable(struct dc_fg * fg)204 void dc_fg_disable(struct dc_fg *fg)
205 {
206 regmap_write(fg->reg, FGENABLE, 0);
207 }
208
dc_fg_shdtokgen(struct dc_fg * fg)209 void dc_fg_shdtokgen(struct dc_fg *fg)
210 {
211 regmap_write(fg->reg, FGSLR, SHDTOKGEN);
212 }
213
dc_fg_get_frame_index(struct dc_fg * fg)214 u32 dc_fg_get_frame_index(struct dc_fg *fg)
215 {
216 u32 val;
217
218 regmap_read(fg->reg, FGTIMESTAMP, &val);
219
220 return FRAMEINDEX(val);
221 }
222
dc_fg_get_line_index(struct dc_fg * fg)223 u32 dc_fg_get_line_index(struct dc_fg *fg)
224 {
225 u32 val;
226
227 regmap_read(fg->reg, FGTIMESTAMP, &val);
228
229 return LINEINDEX(val);
230 }
231
dc_fg_wait_for_frame_index_moving(struct dc_fg * fg)232 bool dc_fg_wait_for_frame_index_moving(struct dc_fg *fg)
233 {
234 unsigned long timeout = jiffies + msecs_to_jiffies(100);
235 u32 frame_index, last_frame_index;
236
237 frame_index = dc_fg_get_frame_index(fg);
238 do {
239 last_frame_index = frame_index;
240 frame_index = dc_fg_get_frame_index(fg);
241 } while (last_frame_index == frame_index &&
242 time_before(jiffies, timeout));
243
244 return last_frame_index != frame_index;
245 }
246
dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg * fg)247 bool dc_fg_secondary_requests_to_read_empty_fifo(struct dc_fg *fg)
248 {
249 u32 val;
250
251 regmap_read(fg->reg, FGCHSTAT, &val);
252
253 return !!(val & SFIFOEMPTY);
254 }
255
dc_fg_secondary_clear_channel_status(struct dc_fg * fg)256 void dc_fg_secondary_clear_channel_status(struct dc_fg *fg)
257 {
258 regmap_write(fg->reg, FGCHSTATCLR, CLRSECSTAT);
259 }
260
dc_fg_wait_for_secondary_syncup(struct dc_fg * fg)261 int dc_fg_wait_for_secondary_syncup(struct dc_fg *fg)
262 {
263 unsigned int val;
264
265 return regmap_read_poll_timeout(fg->reg, FGCHSTAT, val,
266 val & SECSYNCSTAT, 5, 100000);
267 }
268
dc_fg_enable_clock(struct dc_fg * fg)269 void dc_fg_enable_clock(struct dc_fg *fg)
270 {
271 int ret;
272
273 ret = clk_prepare_enable(fg->clk_disp);
274 if (ret)
275 dev_err(fg->dev, "failed to enable display clock: %d\n", ret);
276 }
277
dc_fg_disable_clock(struct dc_fg * fg)278 void dc_fg_disable_clock(struct dc_fg *fg)
279 {
280 clk_disable_unprepare(fg->clk_disp);
281 }
282
dc_fg_check_clock(struct dc_fg * fg,int clk_khz)283 enum drm_mode_status dc_fg_check_clock(struct dc_fg *fg, int clk_khz)
284 {
285 unsigned long rounded_rate;
286
287 rounded_rate = clk_round_rate(fg->clk_disp, clk_khz * HZ_PER_KHZ);
288
289 if (rounded_rate != clk_khz * HZ_PER_KHZ)
290 return MODE_NOCLOCK;
291
292 return MODE_OK;
293 }
294
dc_fg_init(struct dc_fg * fg)295 void dc_fg_init(struct dc_fg *fg)
296 {
297 dc_fg_enable_shden(fg);
298 dc_fg_syncmode(fg, FG_SYNCMODE_OFF);
299 dc_fg_displaymode(fg, FG_DM_SEC_ON_TOP);
300 dc_fg_panic_displaymode(fg, FG_DM_CONSTCOL);
301 }
302
dc_fg_bind(struct device * dev,struct device * master,void * data)303 static int dc_fg_bind(struct device *dev, struct device *master, void *data)
304 {
305 struct platform_device *pdev = to_platform_device(dev);
306 struct dc_drm_device *dc_drm = data;
307 struct resource *res;
308 void __iomem *base;
309 struct dc_fg *fg;
310 int id;
311
312 fg = devm_kzalloc(dev, sizeof(*fg), GFP_KERNEL);
313 if (!fg)
314 return -ENOMEM;
315
316 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
317 if (IS_ERR(base))
318 return PTR_ERR(base);
319
320 fg->reg = devm_regmap_init_mmio(dev, base, &dc_fg_regmap_config);
321 if (IS_ERR(fg->reg))
322 return PTR_ERR(fg->reg);
323
324 fg->clk_disp = devm_clk_get(dev, NULL);
325 if (IS_ERR(fg->clk_disp))
326 return dev_err_probe(dev, PTR_ERR(fg->clk_disp),
327 "failed to get display clock\n");
328
329 id = dc_subdev_get_id(dc_fg_info, ARRAY_SIZE(dc_fg_info), res);
330 if (id < 0) {
331 dev_err(dev, "failed to get instance number: %d\n", id);
332 return id;
333 }
334
335 fg->dev = dev;
336 dc_drm->fg[id] = fg;
337
338 return 0;
339 }
340
341 static const struct component_ops dc_fg_ops = {
342 .bind = dc_fg_bind,
343 };
344
dc_fg_probe(struct platform_device * pdev)345 static int dc_fg_probe(struct platform_device *pdev)
346 {
347 int ret;
348
349 ret = component_add(&pdev->dev, &dc_fg_ops);
350 if (ret)
351 return dev_err_probe(&pdev->dev, ret,
352 "failed to add component\n");
353
354 return 0;
355 }
356
dc_fg_remove(struct platform_device * pdev)357 static void dc_fg_remove(struct platform_device *pdev)
358 {
359 component_del(&pdev->dev, &dc_fg_ops);
360 }
361
362 static const struct of_device_id dc_fg_dt_ids[] = {
363 { .compatible = "fsl,imx8qxp-dc-framegen" },
364 { /* sentinel */ }
365 };
366 MODULE_DEVICE_TABLE(of, dc_fg_dt_ids);
367
368 struct platform_driver dc_fg_driver = {
369 .probe = dc_fg_probe,
370 .remove = dc_fg_remove,
371 .driver = {
372 .name = "imx8-dc-framegen",
373 .suppress_bind_attrs = true,
374 .of_match_table = dc_fg_dt_ids,
375 },
376 };
377