1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/block/flash.h"
19 #include "hw/i2c/i2c_mux_pca954x.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/gpio/pca9552.h"
22 #include "hw/gpio/pca9554.h"
23 #include "hw/nvram/eeprom_at24c.h"
24 #include "hw/sensor/tmp105.h"
25 #include "hw/misc/led.h"
26 #include "hw/qdev-properties.h"
27 #include "system/block-backend.h"
28 #include "system/reset.h"
29 #include "hw/loader.h"
30 #include "qemu/error-report.h"
31 #include "qemu/datadir.h"
32 #include "qemu/units.h"
33 #include "hw/qdev-clock.h"
34 #include "system/system.h"
35
36 static struct arm_boot_info aspeed_board_binfo = {
37 .board_id = -1, /* device-tree-only board */
38 };
39
40 struct AspeedMachineState {
41 /* Private */
42 MachineState parent_obj;
43 /* Public */
44
45 AspeedSoCState *soc;
46 MemoryRegion boot_rom;
47 bool mmio_exec;
48 uint32_t uart_chosen;
49 char *fmc_model;
50 char *spi_model;
51 uint32_t hw_strap1;
52 };
53
54 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
55 #if HOST_LONG_BITS == 32
56 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
57 #else
58 #define ASPEED_RAM_SIZE(sz) (sz)
59 #endif
60
61 /* Palmetto hardware value: 0x120CE416 */
62 #define PALMETTO_BMC_HW_STRAP1 ( \
63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
65 SCU_AST2400_HW_STRAP_ACPI_DIS | \
66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
67 SCU_HW_STRAP_VGA_CLASS_CODE | \
68 SCU_HW_STRAP_LPC_RESET_PIN | \
69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
71 SCU_HW_STRAP_SPI_WIDTH | \
72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
74
75 /* TODO: Find the actual hardware value */
76 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
77 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
78 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
79 SCU_AST2400_HW_STRAP_ACPI_DIS | \
80 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
81 SCU_HW_STRAP_VGA_CLASS_CODE | \
82 SCU_HW_STRAP_LPC_RESET_PIN | \
83 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
84 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
85 SCU_HW_STRAP_SPI_WIDTH | \
86 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
87 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
88
89 /* TODO: Find the actual hardware value */
90 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
91 AST2500_HW_STRAP1_DEFAULTS | \
92 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
93 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
94 SCU_AST2500_HW_STRAP_UART_DEBUG | \
95 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
96 SCU_HW_STRAP_SPI_WIDTH | \
97 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
98
99 /* AST2500 evb hardware value: 0xF100C2E6 */
100 #define AST2500_EVB_HW_STRAP1 (( \
101 AST2500_HW_STRAP1_DEFAULTS | \
102 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
103 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
104 SCU_AST2500_HW_STRAP_UART_DEBUG | \
105 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
106 SCU_HW_STRAP_MAC1_RGMII | \
107 SCU_HW_STRAP_MAC0_RGMII) & \
108 ~SCU_HW_STRAP_2ND_BOOT_WDT)
109
110 /* Romulus hardware value: 0xF10AD206 */
111 #define ROMULUS_BMC_HW_STRAP1 ( \
112 AST2500_HW_STRAP1_DEFAULTS | \
113 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
114 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
115 SCU_AST2500_HW_STRAP_UART_DEBUG | \
116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
119
120 /* Sonorapass hardware value: 0xF100D216 */
121 #define SONORAPASS_BMC_HW_STRAP1 ( \
122 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
123 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
124 SCU_AST2500_HW_STRAP_UART_DEBUG | \
125 SCU_AST2500_HW_STRAP_RESERVED28 | \
126 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
127 SCU_HW_STRAP_VGA_CLASS_CODE | \
128 SCU_HW_STRAP_LPC_RESET_PIN | \
129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
131 SCU_HW_STRAP_VGA_BIOS_ROM | \
132 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
133 SCU_AST2500_HW_STRAP_RESERVED1)
134
135 #define G220A_BMC_HW_STRAP1 ( \
136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
138 SCU_AST2500_HW_STRAP_UART_DEBUG | \
139 SCU_AST2500_HW_STRAP_RESERVED28 | \
140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
141 SCU_HW_STRAP_2ND_BOOT_WDT | \
142 SCU_HW_STRAP_VGA_CLASS_CODE | \
143 SCU_HW_STRAP_LPC_RESET_PIN | \
144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
145 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
147 SCU_AST2500_HW_STRAP_RESERVED1)
148
149 /* FP5280G2 hardware value: 0XF100D286 */
150 #define FP5280G2_BMC_HW_STRAP1 ( \
151 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
152 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
153 SCU_AST2500_HW_STRAP_UART_DEBUG | \
154 SCU_AST2500_HW_STRAP_RESERVED28 | \
155 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
156 SCU_HW_STRAP_VGA_CLASS_CODE | \
157 SCU_HW_STRAP_LPC_RESET_PIN | \
158 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
159 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
160 SCU_HW_STRAP_MAC1_RGMII | \
161 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
162 SCU_AST2500_HW_STRAP_RESERVED1)
163
164 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
165 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
166
167 /* Quanta-Q71l hardware value */
168 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
169 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
170 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
171 SCU_AST2400_HW_STRAP_ACPI_DIS | \
172 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
173 SCU_HW_STRAP_VGA_CLASS_CODE | \
174 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
175 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
176 SCU_HW_STRAP_SPI_WIDTH | \
177 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
178 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
179
180 /* AST2600 evb hardware value */
181 #define AST2600_EVB_HW_STRAP1 0x000000C0
182 #define AST2600_EVB_HW_STRAP2 0x00000003
183
184 #ifdef TARGET_AARCH64
185 /* AST2700 evb hardware value */
186 /* SCU HW Strap1 */
187 #define AST2700_EVB_HW_STRAP1 0x00000800
188 /* SCUIO HW Strap1 */
189 #define AST2700_EVB_HW_STRAP2 0x00000700
190 #endif
191
192 /* Rainier hardware value: (QEMU prototype) */
193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
194 #define RAINIER_BMC_HW_STRAP2 0x80000848
195
196 /* Fuji hardware value */
197 #define FUJI_BMC_HW_STRAP1 0x00000000
198 #define FUJI_BMC_HW_STRAP2 0x00000000
199
200 /* Bletchley hardware value */
201 #define BLETCHLEY_BMC_HW_STRAP1 0x00002000
202 #define BLETCHLEY_BMC_HW_STRAP2 0x00000801
203
204 /* GB200NVL hardware value */
205 #define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
206 #define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
207
208 /* Qualcomm DC-SCM hardware value */
209 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
210 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
211
212 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
213 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
214 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
215 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
216 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
217 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
218 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
219
aspeed_write_smpboot(ARMCPU * cpu,const struct arm_boot_info * info)220 static void aspeed_write_smpboot(ARMCPU *cpu,
221 const struct arm_boot_info *info)
222 {
223 AddressSpace *as = arm_boot_address_space(cpu, info);
224 static const ARMInsnFixup poll_mailbox_ready[] = {
225 /*
226 * r2 = per-cpu go sign value
227 * r1 = AST_SMP_MBOX_FIELD_ENTRY
228 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
229 */
230 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
231 { 0xe21000ff }, /* ands r0, r0, #255 */
232 { 0xe59f201c }, /* ldr r2, [pc, #28] */
233 { 0xe1822000 }, /* orr r2, r2, r0 */
234
235 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
236 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
237
238 { 0xe320f002 }, /* wfe */
239 { 0xe5904000 }, /* ldr r4, [r0] */
240 { 0xe1520004 }, /* cmp r2, r4 */
241 { 0x1afffffb }, /* bne <wfe> */
242 { 0xe591f000 }, /* ldr pc, [r1] */
243 { AST_SMP_MBOX_GOSIGN },
244 { AST_SMP_MBOX_FIELD_ENTRY },
245 { AST_SMP_MBOX_FIELD_GOSIGN },
246 { 0, FIXUP_TERMINATOR }
247 };
248 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
249
250 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
251 poll_mailbox_ready, fixupcontext);
252 }
253
aspeed_reset_secondary(ARMCPU * cpu,const struct arm_boot_info * info)254 static void aspeed_reset_secondary(ARMCPU *cpu,
255 const struct arm_boot_info *info)
256 {
257 AddressSpace *as = arm_boot_address_space(cpu, info);
258 CPUState *cs = CPU(cpu);
259
260 /* info->smp_bootreg_addr */
261 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
262 MEMTXATTRS_UNSPECIFIED, NULL);
263 cpu_set_pc(cs, info->smp_loader_start);
264 }
265
write_boot_rom(BlockBackend * blk,hwaddr addr,size_t rom_size,Error ** errp)266 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
267 Error **errp)
268 {
269 g_autofree void *storage = NULL;
270 int64_t size;
271
272 /*
273 * The block backend size should have already been 'validated' by
274 * the creation of the m25p80 object.
275 */
276 size = blk_getlength(blk);
277 if (size <= 0) {
278 error_setg(errp, "failed to get flash size");
279 return;
280 }
281
282 if (rom_size > size) {
283 rom_size = size;
284 }
285
286 storage = g_malloc0(rom_size);
287 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
288 error_setg(errp, "failed to read the initial flash content");
289 return;
290 }
291
292 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
293 }
294
295 /*
296 * Create a ROM and copy the flash contents at the expected address
297 * (0x0). Boots faster than execute-in-place.
298 */
aspeed_install_boot_rom(AspeedMachineState * bmc,BlockBackend * blk,uint64_t rom_size)299 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
300 uint64_t rom_size)
301 {
302 AspeedSoCState *soc = bmc->soc;
303 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
304
305 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
306 &error_abort);
307 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
308 &bmc->boot_rom, 1);
309 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
310 rom_size, &error_abort);
311 }
312
313 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
314
315 /*
316 * This function locates the vbootrom image file specified via the command line
317 * using the -bios option. It loads the specified image into the vbootrom
318 * memory region and handles errors if the file cannot be found or loaded.
319 */
aspeed_load_vbootrom(AspeedMachineState * bmc,const char * bios_name,Error ** errp)320 static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name,
321 Error **errp)
322 {
323 g_autofree char *filename = NULL;
324 AspeedSoCState *soc = bmc->soc;
325 int ret;
326
327 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
328 if (!filename) {
329 error_setg(errp, "Could not find vbootrom image '%s'", bios_name);
330 return;
331 }
332
333 ret = load_image_mr(filename, &soc->vbootrom);
334 if (ret < 0) {
335 error_setg(errp, "Failed to load vbootrom image '%s'", bios_name);
336 return;
337 }
338 }
339
aspeed_board_init_flashes(AspeedSMCState * s,const char * flashtype,unsigned int count,int unit0)340 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
341 unsigned int count, int unit0)
342 {
343 int i;
344
345 if (!flashtype) {
346 return;
347 }
348
349 for (i = 0; i < count; ++i) {
350 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
351 DeviceState *dev;
352
353 dev = qdev_new(flashtype);
354 if (dinfo) {
355 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
356 }
357 qdev_prop_set_uint8(dev, "cs", i);
358 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
359 }
360 }
361
sdhci_attach_drive(SDHCIState * sdhci,DriveInfo * dinfo,bool emmc,bool boot_emmc)362 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
363 bool boot_emmc)
364 {
365 DeviceState *card;
366
367 if (!dinfo) {
368 return;
369 }
370 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
371
372 /*
373 * Force the boot properties of the eMMC device only when the
374 * machine is strapped to boot from eMMC. Without these
375 * settings, the machine would not boot.
376 *
377 * This also allows the machine to use an eMMC device without
378 * boot areas when booting from the flash device (or -kernel)
379 * Ideally, the device and its properties should be defined on
380 * the command line.
381 */
382 if (emmc && boot_emmc) {
383 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB);
384 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3);
385 }
386 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
387 &error_fatal);
388 qdev_realize_and_unref(card,
389 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
390 &error_fatal);
391 }
392
connect_serial_hds_to_uarts(AspeedMachineState * bmc)393 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
394 {
395 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
396 AspeedSoCState *s = bmc->soc;
397 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
398 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
399
400 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
401 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) {
402 if (uart == uart_chosen) {
403 continue;
404 }
405 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++));
406 }
407 }
408
aspeed_machine_init(MachineState * machine)409 static void aspeed_machine_init(MachineState *machine)
410 {
411 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
412 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
413 AspeedSoCClass *sc;
414 int i;
415 const char *bios_name = NULL;
416 DriveInfo *emmc0 = NULL;
417 bool boot_emmc;
418
419 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
420 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
421 object_unref(OBJECT(bmc->soc));
422 sc = ASPEED_SOC_GET_CLASS(bmc->soc);
423
424 /*
425 * This will error out if the RAM size is not supported by the
426 * memory controller of the SoC.
427 */
428 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
429 &error_fatal);
430
431 for (i = 0; i < sc->macs_num; i++) {
432 if ((amc->macs_mask & (1 << i)) &&
433 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]),
434 true, NULL)) {
435 break; /* No configs left; stop asking */
436 }
437 }
438
439 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1,
440 &error_abort);
441 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
442 &error_abort);
443 object_property_set_link(OBJECT(bmc->soc), "memory",
444 OBJECT(get_system_memory()), &error_abort);
445 object_property_set_link(OBJECT(bmc->soc), "dram",
446 OBJECT(machine->ram), &error_abort);
447 if (amc->sdhci_wp_inverted) {
448 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
449 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]),
450 "wp-inverted", true, &error_abort);
451 }
452 }
453 if (machine->kernel_filename) {
454 /*
455 * When booting with a -kernel command line there is no u-boot
456 * that runs to unlock the SCU. In this case set the default to
457 * be unlocked as the kernel expects
458 */
459 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
460 ASPEED_SCU_PROT_KEY, &error_abort);
461 }
462 connect_serial_hds_to_uarts(bmc);
463 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
464
465 if (defaults_enabled()) {
466 aspeed_board_init_flashes(&bmc->soc->fmc,
467 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
468 amc->num_cs, 0);
469 aspeed_board_init_flashes(&bmc->soc->spi[0],
470 bmc->spi_model ? bmc->spi_model : amc->spi_model,
471 1, amc->num_cs);
472 aspeed_board_init_flashes(&bmc->soc->spi[1],
473 amc->spi2_model, 1, amc->num_cs2);
474 }
475
476 if (machine->kernel_filename && sc->num_cpus > 1) {
477 /* With no u-boot we must set up a boot stub for the secondary CPU */
478 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
479 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
480 0x80, &error_abort);
481 memory_region_add_subregion(get_system_memory(),
482 AST_SMP_MAILBOX_BASE, smpboot);
483
484 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
485 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
486 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
487 }
488
489 aspeed_board_binfo.ram_size = machine->ram_size;
490 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
491
492 if (amc->i2c_init) {
493 amc->i2c_init(bmc);
494 }
495
496 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) {
497 sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
498 drive_get(IF_SD, 0, i), false, false);
499 }
500
501 boot_emmc = sc->boot_from_emmc(bmc->soc);
502
503 if (bmc->soc->emmc.num_slots && defaults_enabled()) {
504 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots);
505 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc);
506 }
507
508 if (!bmc->mmio_exec) {
509 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
510 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
511
512 if (fmc0 && !boot_emmc) {
513 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
514 aspeed_install_boot_rom(bmc, fmc0, rom_size);
515 } else if (emmc0) {
516 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB);
517 }
518 }
519
520 if (amc->vbootrom) {
521 bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
522 aspeed_load_vbootrom(bmc, bios_name, &error_abort);
523 }
524
525 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
526 }
527
palmetto_bmc_i2c_init(AspeedMachineState * bmc)528 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
529 {
530 AspeedSoCState *soc = bmc->soc;
531 DeviceState *dev;
532 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
533
534 /*
535 * The palmetto platform expects a ds3231 RTC but a ds1338 is
536 * enough to provide basic RTC features. Alarms will be missing
537 */
538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
539
540 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
541 eeprom_buf);
542
543 /* add a TMP423 temperature sensor */
544 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
545 "tmp423", 0x4c));
546 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
547 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
548 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
549 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
550 }
551
quanta_q71l_bmc_i2c_init(AspeedMachineState * bmc)552 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
553 {
554 AspeedSoCState *soc = bmc->soc;
555
556 /*
557 * The quanta-q71l platform expects tmp75s which are compatible with
558 * tmp105s.
559 */
560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
563
564 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
565 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
566 /* TODO: Add Memory Riser i2c mux and eeproms. */
567
568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
570
571 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
572
573 /* i2c-7 */
574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
575 /* - i2c@0: pmbus@59 */
576 /* - i2c@1: pmbus@58 */
577 /* - i2c@2: pmbus@58 */
578 /* - i2c@3: pmbus@59 */
579
580 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
581 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
582 }
583
ast2500_evb_i2c_init(AspeedMachineState * bmc)584 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
585 {
586 AspeedSoCState *soc = bmc->soc;
587 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
588
589 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
590 eeprom_buf);
591
592 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
593 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
594 TYPE_TMP105, 0x4d);
595 }
596
ast2600_evb_i2c_init(AspeedMachineState * bmc)597 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
598 {
599 AspeedSoCState *soc = bmc->soc;
600 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
601
602 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
603 eeprom_buf);
604
605 /* LM75 is compatible with TMP105 driver */
606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
607 TYPE_TMP105, 0x4d);
608 }
609
yosemitev2_bmc_i2c_init(AspeedMachineState * bmc)610 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
611 {
612 AspeedSoCState *soc = bmc->soc;
613
614 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
615 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
616 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
617 /* TMP421 */
618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
619 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
621
622 }
623
romulus_bmc_i2c_init(AspeedMachineState * bmc)624 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
625 {
626 AspeedSoCState *soc = bmc->soc;
627
628 /*
629 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
630 * good enough
631 */
632 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
633 }
634
tiogapass_bmc_i2c_init(AspeedMachineState * bmc)635 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
636 {
637 AspeedSoCState *soc = bmc->soc;
638
639 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
640 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
641 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
642 /* TMP421 */
643 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
644 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
645 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
646 }
647
create_pca9552(AspeedSoCState * soc,int bus_id,int addr)648 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
649 {
650 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
651 TYPE_PCA9552, addr);
652 }
653
create_pca9554(AspeedSoCState * soc,int bus_id,int addr)654 static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
655 {
656 return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
657 TYPE_PCA9554, addr);
658 }
659
sonorapass_bmc_i2c_init(AspeedMachineState * bmc)660 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
661 {
662 AspeedSoCState *soc = bmc->soc;
663
664 /* bus 2 : */
665 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
666 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
667 /* bus 2 : pca9546 @ 0x73 */
668
669 /* bus 3 : pca9548 @ 0x70 */
670
671 /* bus 4 : */
672 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
673 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
674 eeprom4_54);
675 /* PCA9539 @ 0x76, but PCA9552 is compatible */
676 create_pca9552(soc, 4, 0x76);
677 /* PCA9539 @ 0x77, but PCA9552 is compatible */
678 create_pca9552(soc, 4, 0x77);
679
680 /* bus 6 : */
681 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
683 /* bus 6 : pca9546 @ 0x73 */
684
685 /* bus 8 : */
686 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
687 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
688 eeprom8_56);
689 create_pca9552(soc, 8, 0x60);
690 create_pca9552(soc, 8, 0x61);
691 /* bus 8 : adc128d818 @ 0x1d */
692 /* bus 8 : adc128d818 @ 0x1f */
693
694 /*
695 * bus 13 : pca9548 @ 0x71
696 * - channel 3:
697 * - tmm421 @ 0x4c
698 * - tmp421 @ 0x4e
699 * - tmp421 @ 0x4f
700 */
701
702 }
703
witherspoon_bmc_i2c_init(AspeedMachineState * bmc)704 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
705 {
706 static const struct {
707 unsigned gpio_id;
708 LEDColor color;
709 const char *description;
710 bool gpio_polarity;
711 } pca1_leds[] = {
712 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
713 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
714 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
715 };
716 AspeedSoCState *soc = bmc->soc;
717 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
718 DeviceState *dev;
719 LEDState *led;
720
721 /* Bus 3: TODO bmp280@77 */
722 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
723 qdev_prop_set_string(dev, "description", "pca1");
724 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
725 aspeed_i2c_get_bus(&soc->i2c, 3),
726 &error_fatal);
727
728 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
729 led = led_create_simple(OBJECT(bmc),
730 pca1_leds[i].gpio_polarity,
731 pca1_leds[i].color,
732 pca1_leds[i].description);
733 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
734 qdev_get_gpio_in(DEVICE(led), 0));
735 }
736 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
740
741 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
742 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
743 0x4a);
744
745 /*
746 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
747 * good enough
748 */
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
750
751 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
752 eeprom_buf);
753 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
754 qdev_prop_set_string(dev, "description", "pca0");
755 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
756 aspeed_i2c_get_bus(&soc->i2c, 11),
757 &error_fatal);
758 /* Bus 11: TODO ucd90160@64 */
759 }
760
g220a_bmc_i2c_init(AspeedMachineState * bmc)761 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
762 {
763 AspeedSoCState *soc = bmc->soc;
764 DeviceState *dev;
765
766 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
767 "emc1413", 0x4c));
768 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
769 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
770 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
771
772 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
773 "emc1413", 0x4c));
774 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
775 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
776 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
777
778 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
779 "emc1413", 0x4c));
780 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
781 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
782 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
783
784 static uint8_t eeprom_buf[2 * 1024] = {
785 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
786 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
787 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
788 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
789 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
790 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
791 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
792 };
793 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
794 eeprom_buf);
795 }
796
fp5280g2_bmc_i2c_init(AspeedMachineState * bmc)797 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
798 {
799 AspeedSoCState *soc = bmc->soc;
800 I2CSlave *i2c_mux;
801
802 /* The at24c256 */
803 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
804
805 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
807 0x48);
808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
809 0x49);
810
811 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
812 "pca9546", 0x70);
813 /* It expects a TMP112 but a TMP105 is compatible */
814 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
815 0x4a);
816
817 /* It expects a ds3232 but a ds1338 is good enough */
818 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
819
820 /* It expects a pca9555 but a pca9552 is compatible */
821 create_pca9552(soc, 8, 0x30);
822 }
823
rainier_bmc_i2c_init(AspeedMachineState * bmc)824 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
825 {
826 AspeedSoCState *soc = bmc->soc;
827 I2CSlave *i2c_mux;
828
829 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
830
831 create_pca9552(soc, 3, 0x61);
832
833 /* The rainier expects a TMP275 but a TMP105 is compatible */
834 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
835 0x48);
836 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
837 0x49);
838 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
839 0x4a);
840 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
841 "pca9546", 0x70);
842 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
843 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
844 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
845 create_pca9552(soc, 4, 0x60);
846
847 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
848 0x48);
849 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
850 0x49);
851 create_pca9552(soc, 5, 0x60);
852 create_pca9552(soc, 5, 0x61);
853 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
854 "pca9546", 0x70);
855 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
856 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
857
858 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
859 0x48);
860 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
861 0x4a);
862 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
863 0x4b);
864 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
865 "pca9546", 0x70);
866 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
867 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
868 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
869 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
870
871 create_pca9552(soc, 7, 0x30);
872 create_pca9552(soc, 7, 0x31);
873 create_pca9552(soc, 7, 0x32);
874 create_pca9552(soc, 7, 0x33);
875 create_pca9552(soc, 7, 0x60);
876 create_pca9552(soc, 7, 0x61);
877 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
878 /* Bus 7: TODO si7021-a20@20 */
879 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
880 0x48);
881 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
882 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
883 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
884
885 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
886 0x48);
887 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
888 0x4a);
889 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
890 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
891 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
892 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
893 create_pca9552(soc, 8, 0x60);
894 create_pca9552(soc, 8, 0x61);
895 /* Bus 8: ucd90320@11 */
896 /* Bus 8: ucd90320@b */
897 /* Bus 8: ucd90320@c */
898
899 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
900 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
901 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
902
903 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
904 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
905 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
906
907 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
908 0x48);
909 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
910 0x49);
911 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
912 "pca9546", 0x70);
913 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
914 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
915 create_pca9552(soc, 11, 0x60);
916
917
918 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
919 create_pca9552(soc, 13, 0x60);
920
921 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
922 create_pca9552(soc, 14, 0x60);
923
924 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
925 create_pca9552(soc, 15, 0x60);
926 }
927
get_pca9548_channels(I2CBus * bus,uint8_t mux_addr,I2CBus ** channels)928 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
929 I2CBus **channels)
930 {
931 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
932 for (int i = 0; i < 8; i++) {
933 channels[i] = pca954x_i2c_get_bus(mux, i);
934 }
935 }
936
937 #define TYPE_LM75 TYPE_TMP105
938 #define TYPE_TMP75 TYPE_TMP105
939 #define TYPE_TMP422 "tmp422"
940
fuji_bmc_i2c_init(AspeedMachineState * bmc)941 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
942 {
943 AspeedSoCState *soc = bmc->soc;
944 I2CBus *i2c[144] = {};
945
946 for (int i = 0; i < 16; i++) {
947 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
948 }
949 I2CBus *i2c180 = i2c[2];
950 I2CBus *i2c480 = i2c[8];
951 I2CBus *i2c600 = i2c[11];
952
953 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
954 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
955 /* NOTE: The device tree skips [32, 40) in the alias numbering */
956 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
957 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
958 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
959 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
960 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
961 for (int i = 0; i < 8; i++) {
962 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
963 }
964
965 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
966 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
967
968 /*
969 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
970 * 24c02 size is 2Kbits or 256 bytes
971 */
972 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
973 at24c_eeprom_init(i2c[20], 0x50, 256);
974 at24c_eeprom_init(i2c[22], 0x52, 256);
975
976 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
977 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
978 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
979 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
980
981 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
982 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
983
984 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
985 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
986 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
987 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
988
989 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
990 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
991
992 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
993 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
994 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
995 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
996 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
997 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
998 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
999
1000 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
1001 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
1002 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
1003 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
1004 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
1005 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
1006 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
1007 at24c_eeprom_init(i2c[28], 0x50, 256);
1008
1009 for (int i = 0; i < 8; i++) {
1010 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
1011 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
1012 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
1013 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
1014 }
1015 }
1016
1017 #define TYPE_TMP421 "tmp421"
1018 #define TYPE_DS1338 "ds1338"
1019
1020 /* Catalina hardware value */
1021 #define CATALINA_BMC_HW_STRAP1 0x00002002
1022 #define CATALINA_BMC_HW_STRAP2 0x00000800
1023
1024 #define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1025
catalina_bmc_i2c_init(AspeedMachineState * bmc)1026 static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
1027 {
1028 /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */
1029
1030 AspeedSoCState *soc = bmc->soc;
1031 I2CBus *i2c[16] = {};
1032 I2CSlave *i2c_mux;
1033
1034 /* busses 0-15 are all used. */
1035 for (int i = 0; i < ARRAY_SIZE(i2c); i++) {
1036 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1037 }
1038
1039 /* &i2c0 */
1040 /* i2c-mux@71 (PCA9546) on i2c0 */
1041 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71);
1042
1043 /* i2c-mux@72 (PCA9546) on i2c0 */
1044 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72);
1045
1046 /* i2c0mux1ch1 */
1047 /* io_expander7 - pca9535@20 */
1048 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
1049 TYPE_PCA9552, 0x20);
1050 /* eeprom@50 */
1051 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
1052
1053 /* i2c-mux@73 (PCA9546) on i2c0 */
1054 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73);
1055
1056 /* i2c-mux@75 (PCA9546) on i2c0 */
1057 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75);
1058
1059 /* i2c-mux@76 (PCA9546) on i2c0 */
1060 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76);
1061
1062 /* i2c0mux4ch1 */
1063 /* io_expander8 - pca9535@21 */
1064 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
1065 TYPE_PCA9552, 0x21);
1066 /* eeprom@50 */
1067 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
1068
1069 /* i2c-mux@77 (PCA9546) on i2c0 */
1070 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77);
1071
1072
1073 /* &i2c1 */
1074 /* i2c-mux@70 (PCA9548) on i2c1 */
1075 i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70);
1076 /* i2c1mux0ch0 */
1077 /* ina238@41 - no model */
1078 /* ina238@42 - no model */
1079 /* ina238@44 - no model */
1080 /* i2c1mux0ch1 */
1081 /* ina238@41 - no model */
1082 /* ina238@43 - no model */
1083 /* i2c1mux0ch4 */
1084 /* ltc4287@42 - no model */
1085 /* ltc4287@43 - no model */
1086
1087 /* i2c1mux0ch5 */
1088 /* eeprom@54 */
1089 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB);
1090 /* tpm75@4f */
1091 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f);
1092
1093 /* i2c1mux0ch6 */
1094 /* io_expander5 - pca9554@27 */
1095 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
1096 TYPE_PCA9554, 0x27);
1097 /* io_expander6 - pca9555@25 */
1098 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
1099 TYPE_PCA9552, 0x25);
1100 /* eeprom@51 */
1101 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB);
1102
1103 /* i2c1mux0ch7 */
1104 /* eeprom@53 */
1105 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB);
1106 /* temperature-sensor@4b - tmp75 */
1107 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b);
1108
1109 /* &i2c2 */
1110 /* io_expander0 - pca9555@20 */
1111 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20);
1112 /* io_expander0 - pca9555@21 */
1113 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21);
1114 /* io_expander0 - pca9555@27 */
1115 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27);
1116 /* eeprom@50 */
1117 at24c_eeprom_init(i2c[2], 0x50, 8 * KiB);
1118 /* eeprom@51 */
1119 at24c_eeprom_init(i2c[2], 0x51, 8 * KiB);
1120
1121 /* &i2c5 */
1122 /* i2c-mux@70 (PCA9548) on i2c5 */
1123 i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70);
1124 /* i2c5mux0ch6 */
1125 /* eeprom@52 */
1126 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB);
1127 /* i2c5mux0ch7 */
1128 /* ina230@40 - no model */
1129 /* ina230@41 - no model */
1130 /* ina230@44 - no model */
1131 /* ina230@45 - no model */
1132
1133 /* &i2c6 */
1134 /* io_expander3 - pca9555@21 */
1135 i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21);
1136 /* rtc@6f - nct3018y */
1137 i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f);
1138
1139 /* &i2c9 */
1140 /* io_expander4 - pca9555@4f */
1141 i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f);
1142 /* temperature-sensor@4b - tpm75 */
1143 i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b);
1144 /* eeprom@50 */
1145 at24c_eeprom_init(i2c[9], 0x50, 8 * KiB);
1146 /* eeprom@56 */
1147 at24c_eeprom_init(i2c[9], 0x56, 8 * KiB);
1148
1149 /* &i2c10 */
1150 /* temperature-sensor@1f - tpm421 */
1151 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f);
1152 /* eeprom@50 */
1153 at24c_eeprom_init(i2c[10], 0x50, 8 * KiB);
1154
1155 /* &i2c11 */
1156 /* ssif-bmc@10 - no model */
1157
1158 /* &i2c12 */
1159 /* eeprom@50 */
1160 at24c_eeprom_init(i2c[12], 0x50, 8 * KiB);
1161
1162 /* &i2c13 */
1163 /* eeprom@50 */
1164 at24c_eeprom_init(i2c[13], 0x50, 8 * KiB);
1165 /* eeprom@54 */
1166 at24c_eeprom_init(i2c[13], 0x54, 256);
1167 /* eeprom@55 */
1168 at24c_eeprom_init(i2c[13], 0x55, 256);
1169 /* eeprom@57 */
1170 at24c_eeprom_init(i2c[13], 0x57, 256);
1171
1172 /* &i2c14 */
1173 /* io_expander9 - pca9555@10 */
1174 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10);
1175 /* io_expander10 - pca9555@11 */
1176 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11);
1177 /* io_expander11 - pca9555@12 */
1178 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12);
1179 /* io_expander12 - pca9555@13 */
1180 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13);
1181 /* io_expander13 - pca9555@14 */
1182 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14);
1183 /* io_expander14 - pca9555@15 */
1184 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15);
1185
1186 /* &i2c15 */
1187 /* temperature-sensor@1f - tmp421 */
1188 i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f);
1189 /* eeprom@52 */
1190 at24c_eeprom_init(i2c[15], 0x52, 8 * KiB);
1191 }
1192
bletchley_bmc_i2c_init(AspeedMachineState * bmc)1193 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
1194 {
1195 AspeedSoCState *soc = bmc->soc;
1196 I2CBus *i2c[13] = {};
1197 for (int i = 0; i < 13; i++) {
1198 if ((i == 8) || (i == 11)) {
1199 continue;
1200 }
1201 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1202 }
1203
1204 /* Bus 0 - 5 all have the same config. */
1205 for (int i = 0; i < 6; i++) {
1206 /* Missing model: ti,ina230 @ 0x45 */
1207 /* Missing model: mps,mp5023 @ 0x40 */
1208 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
1209 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
1210 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
1211 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
1212 /* Missing model: fsc,fusb302 @ 0x22 */
1213 }
1214
1215 /* Bus 6 */
1216 at24c_eeprom_init(i2c[6], 0x56, 65536);
1217 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
1218 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
1219
1220
1221 /* Bus 7 */
1222 at24c_eeprom_init(i2c[7], 0x54, 65536);
1223
1224 /* Bus 9 */
1225 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
1226
1227 /* Bus 10 */
1228 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
1229 /* Missing model: ti,hdc1080 @ 0x40 */
1230 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
1231
1232 /* Bus 12 */
1233 /* Missing model: adi,adm1278 @ 0x11 */
1234 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
1235 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
1236 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
1237 }
1238
1239
gb200nvl_bmc_i2c_init(AspeedMachineState * bmc)1240 static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
1241 {
1242 AspeedSoCState *soc = bmc->soc;
1243 I2CBus *i2c[15] = {};
1244 DeviceState *dev;
1245 for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
1246 if ((i == 11) || (i == 12) || (i == 13)) {
1247 continue;
1248 }
1249 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1250 }
1251
1252 /* Bus 5 Expander */
1253 create_pca9554(soc, 4, 0x21);
1254
1255 /* Mux I2c Expanders */
1256 i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
1257 i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
1258 i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
1259 i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
1260 i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
1261 i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
1262
1263 /* Bus 10 */
1264 dev = DEVICE(create_pca9554(soc, 9, 0x20));
1265
1266 /* Set FPGA_READY */
1267 object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
1268
1269 create_pca9554(soc, 9, 0x21);
1270 at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
1271 at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
1272
1273 /* Bus 11 */
1274 at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
1275 gb200nvl_bmc_fruid_len);
1276 }
1277
fby35_i2c_init(AspeedMachineState * bmc)1278 static void fby35_i2c_init(AspeedMachineState *bmc)
1279 {
1280 AspeedSoCState *soc = bmc->soc;
1281 I2CBus *i2c[16];
1282
1283 for (int i = 0; i < 16; i++) {
1284 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1285 }
1286
1287 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
1288 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
1289 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
1290 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
1291 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
1292 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
1293
1294 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
1295 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
1296 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
1297 fby35_nic_fruid_len);
1298 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
1299 fby35_bb_fruid_len);
1300 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
1301 fby35_bmc_fruid_len);
1302
1303 /*
1304 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1305 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1306 * each.
1307 */
1308 }
1309
qcom_dc_scm_bmc_i2c_init(AspeedMachineState * bmc)1310 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1311 {
1312 AspeedSoCState *soc = bmc->soc;
1313
1314 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1315 }
1316
qcom_dc_scm_firework_i2c_init(AspeedMachineState * bmc)1317 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1318 {
1319 AspeedSoCState *soc = bmc->soc;
1320 I2CSlave *therm_mux, *cpuvr_mux;
1321
1322 /* Create the generic DC-SCM hardware */
1323 qcom_dc_scm_bmc_i2c_init(bmc);
1324
1325 /* Now create the Firework specific hardware */
1326
1327 /* I2C7 CPUVR MUX */
1328 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1329 "pca9546", 0x70);
1330 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1331 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1332 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1333 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1334
1335 /* I2C8 Thermal Diodes*/
1336 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1337 "pca9548", 0x70);
1338 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1339 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1340 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1341 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1342 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1343
1344 /* I2C9 Fan Controller (MAX31785) */
1345 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1346 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1347 }
1348
aspeed_get_mmio_exec(Object * obj,Error ** errp)1349 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1350 {
1351 return ASPEED_MACHINE(obj)->mmio_exec;
1352 }
1353
aspeed_set_mmio_exec(Object * obj,bool value,Error ** errp)1354 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1355 {
1356 ASPEED_MACHINE(obj)->mmio_exec = value;
1357 }
1358
aspeed_machine_instance_init(Object * obj)1359 static void aspeed_machine_instance_init(Object *obj)
1360 {
1361 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj);
1362
1363 ASPEED_MACHINE(obj)->mmio_exec = false;
1364 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1;
1365 }
1366
aspeed_get_fmc_model(Object * obj,Error ** errp)1367 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1368 {
1369 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1370 return g_strdup(bmc->fmc_model);
1371 }
1372
aspeed_set_fmc_model(Object * obj,const char * value,Error ** errp)1373 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1374 {
1375 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1376
1377 g_free(bmc->fmc_model);
1378 bmc->fmc_model = g_strdup(value);
1379 }
1380
aspeed_get_spi_model(Object * obj,Error ** errp)1381 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1382 {
1383 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1384 return g_strdup(bmc->spi_model);
1385 }
1386
aspeed_set_spi_model(Object * obj,const char * value,Error ** errp)1387 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1388 {
1389 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1390
1391 g_free(bmc->spi_model);
1392 bmc->spi_model = g_strdup(value);
1393 }
1394
aspeed_get_bmc_console(Object * obj,Error ** errp)1395 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1396 {
1397 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1398 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1399 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1400
1401 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen));
1402 }
1403
aspeed_set_bmc_console(Object * obj,const char * value,Error ** errp)1404 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1405 {
1406 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1407 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1408 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1409 int val;
1410 int uart_first = aspeed_uart_first(sc);
1411 int uart_last = aspeed_uart_last(sc);
1412
1413 if (sscanf(value, "uart%u", &val) != 1) {
1414 error_setg(errp, "Bad value for \"uart\" property");
1415 return;
1416 }
1417
1418 /* The number of UART depends on the SoC */
1419 if (val < uart_first || val > uart_last) {
1420 error_setg(errp, "\"uart\" should be in range [%d - %d]",
1421 uart_first, uart_last);
1422 return;
1423 }
1424 bmc->uart_chosen = val + ASPEED_DEV_UART0;
1425 }
1426
aspeed_machine_class_props_init(ObjectClass * oc)1427 static void aspeed_machine_class_props_init(ObjectClass *oc)
1428 {
1429 object_class_property_add_bool(oc, "execute-in-place",
1430 aspeed_get_mmio_exec,
1431 aspeed_set_mmio_exec);
1432 object_class_property_set_description(oc, "execute-in-place",
1433 "boot directly from CE0 flash device");
1434
1435 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1436 aspeed_set_bmc_console);
1437 object_class_property_set_description(oc, "bmc-console",
1438 "Change the default UART to \"uartX\"");
1439
1440 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1441 aspeed_set_fmc_model);
1442 object_class_property_set_description(oc, "fmc-model",
1443 "Change the FMC Flash model");
1444 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1445 aspeed_set_spi_model);
1446 object_class_property_set_description(oc, "spi-model",
1447 "Change the SPI Flash model");
1448 }
1449
aspeed_machine_class_init_cpus_defaults(MachineClass * mc)1450 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
1451 {
1452 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
1453 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1454
1455 mc->default_cpus = sc->num_cpus;
1456 mc->min_cpus = sc->num_cpus;
1457 mc->max_cpus = sc->num_cpus;
1458 mc->valid_cpu_types = sc->valid_cpu_types;
1459 }
1460
aspeed_machine_ast2600_get_boot_from_emmc(Object * obj,Error ** errp)1461 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp)
1462 {
1463 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1464
1465 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
1466 }
1467
aspeed_machine_ast2600_set_boot_from_emmc(Object * obj,bool value,Error ** errp)1468 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value,
1469 Error **errp)
1470 {
1471 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1472
1473 if (value) {
1474 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1475 } else {
1476 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1477 }
1478 }
1479
aspeed_machine_ast2600_class_emmc_init(ObjectClass * oc)1480 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
1481 {
1482 object_class_property_add_bool(oc, "boot-emmc",
1483 aspeed_machine_ast2600_get_boot_from_emmc,
1484 aspeed_machine_ast2600_set_boot_from_emmc);
1485 object_class_property_set_description(oc, "boot-emmc",
1486 "Set or unset boot from EMMC");
1487 }
1488
aspeed_machine_class_init(ObjectClass * oc,const void * data)1489 static void aspeed_machine_class_init(ObjectClass *oc, const void *data)
1490 {
1491 MachineClass *mc = MACHINE_CLASS(oc);
1492 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1493
1494 mc->init = aspeed_machine_init;
1495 mc->no_floppy = 1;
1496 mc->no_cdrom = 1;
1497 mc->no_parallel = 1;
1498 mc->default_ram_id = "ram";
1499 amc->macs_mask = ASPEED_MAC0_ON;
1500 amc->uart_default = ASPEED_DEV_UART5;
1501
1502 aspeed_machine_class_props_init(oc);
1503 }
1504
aspeed_machine_palmetto_class_init(ObjectClass * oc,const void * data)1505 static void aspeed_machine_palmetto_class_init(ObjectClass *oc,
1506 const void *data)
1507 {
1508 MachineClass *mc = MACHINE_CLASS(oc);
1509 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1510
1511 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1512 amc->soc_name = "ast2400-a1";
1513 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1514 amc->fmc_model = "n25q256a";
1515 amc->spi_model = "mx25l25635f";
1516 amc->num_cs = 1;
1517 amc->i2c_init = palmetto_bmc_i2c_init;
1518 mc->auto_create_sdcard = true;
1519 mc->default_ram_size = 256 * MiB;
1520 aspeed_machine_class_init_cpus_defaults(mc);
1521 };
1522
aspeed_machine_quanta_q71l_class_init(ObjectClass * oc,const void * data)1523 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc,
1524 const void *data)
1525 {
1526 MachineClass *mc = MACHINE_CLASS(oc);
1527 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1528
1529 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1530 amc->soc_name = "ast2400-a1";
1531 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1532 amc->fmc_model = "n25q256a";
1533 amc->spi_model = "mx25l25635e";
1534 amc->num_cs = 1;
1535 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1536 mc->auto_create_sdcard = true;
1537 mc->default_ram_size = 128 * MiB;
1538 aspeed_machine_class_init_cpus_defaults(mc);
1539 }
1540
aspeed_machine_supermicrox11_bmc_class_init(ObjectClass * oc,const void * data)1541 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1542 const void *data)
1543 {
1544 MachineClass *mc = MACHINE_CLASS(oc);
1545 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1546
1547 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1548 amc->soc_name = "ast2400-a1";
1549 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1550 amc->fmc_model = "mx25l25635e";
1551 amc->spi_model = "mx25l25635e";
1552 amc->num_cs = 1;
1553 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1554 amc->i2c_init = palmetto_bmc_i2c_init;
1555 mc->auto_create_sdcard = true;
1556 mc->default_ram_size = 256 * MiB;
1557 aspeed_machine_class_init_cpus_defaults(mc);
1558 }
1559
aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass * oc,const void * data)1560 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1561 const void *data)
1562 {
1563 MachineClass *mc = MACHINE_CLASS(oc);
1564 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1565
1566 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1567 amc->soc_name = "ast2500-a1";
1568 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1569 amc->fmc_model = "mx25l25635e";
1570 amc->spi_model = "mx25l25635e";
1571 amc->num_cs = 1;
1572 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1573 amc->i2c_init = palmetto_bmc_i2c_init;
1574 mc->auto_create_sdcard = true;
1575 mc->default_ram_size = 512 * MiB;
1576 aspeed_machine_class_init_cpus_defaults(mc);
1577 }
1578
aspeed_machine_ast2500_evb_class_init(ObjectClass * oc,const void * data)1579 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc,
1580 const void *data)
1581 {
1582 MachineClass *mc = MACHINE_CLASS(oc);
1583 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1584
1585 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1586 amc->soc_name = "ast2500-a1";
1587 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1588 amc->fmc_model = "mx25l25635e";
1589 amc->spi_model = "mx25l25635f";
1590 amc->num_cs = 1;
1591 amc->i2c_init = ast2500_evb_i2c_init;
1592 mc->auto_create_sdcard = true;
1593 mc->default_ram_size = 512 * MiB;
1594 aspeed_machine_class_init_cpus_defaults(mc);
1595 };
1596
aspeed_machine_yosemitev2_class_init(ObjectClass * oc,const void * data)1597 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc,
1598 const void *data)
1599 {
1600 MachineClass *mc = MACHINE_CLASS(oc);
1601 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1602
1603 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1604 amc->soc_name = "ast2500-a1";
1605 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1606 amc->hw_strap2 = 0;
1607 amc->fmc_model = "n25q256a";
1608 amc->spi_model = "mx25l25635e";
1609 amc->num_cs = 2;
1610 amc->i2c_init = yosemitev2_bmc_i2c_init;
1611 mc->auto_create_sdcard = true;
1612 mc->default_ram_size = 512 * MiB;
1613 aspeed_machine_class_init_cpus_defaults(mc);
1614 };
1615
aspeed_machine_romulus_class_init(ObjectClass * oc,const void * data)1616 static void aspeed_machine_romulus_class_init(ObjectClass *oc,
1617 const void *data)
1618 {
1619 MachineClass *mc = MACHINE_CLASS(oc);
1620 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1621
1622 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1623 amc->soc_name = "ast2500-a1";
1624 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1625 amc->fmc_model = "n25q256a";
1626 amc->spi_model = "mx66l1g45g";
1627 amc->num_cs = 2;
1628 amc->i2c_init = romulus_bmc_i2c_init;
1629 mc->auto_create_sdcard = true;
1630 mc->default_ram_size = 512 * MiB;
1631 aspeed_machine_class_init_cpus_defaults(mc);
1632 };
1633
aspeed_machine_tiogapass_class_init(ObjectClass * oc,const void * data)1634 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc,
1635 const void *data)
1636 {
1637 MachineClass *mc = MACHINE_CLASS(oc);
1638 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1639
1640 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1641 amc->soc_name = "ast2500-a1";
1642 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1643 amc->hw_strap2 = 0;
1644 amc->fmc_model = "n25q256a";
1645 amc->spi_model = "mx25l25635e";
1646 amc->num_cs = 2;
1647 amc->i2c_init = tiogapass_bmc_i2c_init;
1648 mc->auto_create_sdcard = true;
1649 mc->default_ram_size = 1 * GiB;
1650 aspeed_machine_class_init_cpus_defaults(mc);
1651 };
1652
aspeed_machine_sonorapass_class_init(ObjectClass * oc,const void * data)1653 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc,
1654 const void *data)
1655 {
1656 MachineClass *mc = MACHINE_CLASS(oc);
1657 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1658
1659 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1660 amc->soc_name = "ast2500-a1";
1661 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1662 amc->fmc_model = "mx66l1g45g";
1663 amc->spi_model = "mx66l1g45g";
1664 amc->num_cs = 2;
1665 amc->i2c_init = sonorapass_bmc_i2c_init;
1666 mc->auto_create_sdcard = true;
1667 mc->default_ram_size = 512 * MiB;
1668 aspeed_machine_class_init_cpus_defaults(mc);
1669 };
1670
aspeed_machine_witherspoon_class_init(ObjectClass * oc,const void * data)1671 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc,
1672 const void *data)
1673 {
1674 MachineClass *mc = MACHINE_CLASS(oc);
1675 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1676
1677 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1678 amc->soc_name = "ast2500-a1";
1679 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1680 amc->fmc_model = "mx25l25635f";
1681 amc->spi_model = "mx66l1g45g";
1682 amc->num_cs = 2;
1683 amc->i2c_init = witherspoon_bmc_i2c_init;
1684 mc->auto_create_sdcard = true;
1685 mc->default_ram_size = 512 * MiB;
1686 aspeed_machine_class_init_cpus_defaults(mc);
1687 };
1688
aspeed_machine_ast2600_evb_class_init(ObjectClass * oc,const void * data)1689 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
1690 const void *data)
1691 {
1692 MachineClass *mc = MACHINE_CLASS(oc);
1693 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1694
1695 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1696 amc->soc_name = "ast2600-a3";
1697 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1698 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1699 amc->fmc_model = "mx66u51235f";
1700 amc->spi_model = "mx66u51235f";
1701 amc->num_cs = 1;
1702 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1703 ASPEED_MAC3_ON;
1704 amc->sdhci_wp_inverted = true;
1705 amc->i2c_init = ast2600_evb_i2c_init;
1706 mc->auto_create_sdcard = true;
1707 mc->default_ram_size = 1 * GiB;
1708 aspeed_machine_class_init_cpus_defaults(mc);
1709 aspeed_machine_ast2600_class_emmc_init(oc);
1710 };
1711
aspeed_machine_g220a_class_init(ObjectClass * oc,const void * data)1712 static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data)
1713 {
1714 MachineClass *mc = MACHINE_CLASS(oc);
1715 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1716
1717 mc->desc = "Bytedance G220A BMC (ARM1176)";
1718 amc->soc_name = "ast2500-a1";
1719 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1720 amc->fmc_model = "n25q512a";
1721 amc->spi_model = "mx25l25635e";
1722 amc->num_cs = 2;
1723 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1724 amc->i2c_init = g220a_bmc_i2c_init;
1725 mc->auto_create_sdcard = true;
1726 mc->default_ram_size = 1024 * MiB;
1727 aspeed_machine_class_init_cpus_defaults(mc);
1728 };
1729
aspeed_machine_fp5280g2_class_init(ObjectClass * oc,const void * data)1730 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc,
1731 const void *data)
1732 {
1733 MachineClass *mc = MACHINE_CLASS(oc);
1734 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1735
1736 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1737 amc->soc_name = "ast2500-a1";
1738 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1739 amc->fmc_model = "n25q512a";
1740 amc->spi_model = "mx25l25635e";
1741 amc->num_cs = 2;
1742 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1743 amc->i2c_init = fp5280g2_bmc_i2c_init;
1744 mc->auto_create_sdcard = true;
1745 mc->default_ram_size = 512 * MiB;
1746 aspeed_machine_class_init_cpus_defaults(mc);
1747 };
1748
aspeed_machine_rainier_class_init(ObjectClass * oc,const void * data)1749 static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data)
1750 {
1751 MachineClass *mc = MACHINE_CLASS(oc);
1752 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1753
1754 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1755 amc->soc_name = "ast2600-a3";
1756 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1757 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1758 amc->fmc_model = "mx66l1g45g";
1759 amc->spi_model = "mx66l1g45g";
1760 amc->num_cs = 2;
1761 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1762 amc->i2c_init = rainier_bmc_i2c_init;
1763 mc->auto_create_sdcard = true;
1764 mc->default_ram_size = 1 * GiB;
1765 aspeed_machine_class_init_cpus_defaults(mc);
1766 aspeed_machine_ast2600_class_emmc_init(oc);
1767 };
1768
1769 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1770
aspeed_machine_fuji_class_init(ObjectClass * oc,const void * data)1771 static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data)
1772 {
1773 MachineClass *mc = MACHINE_CLASS(oc);
1774 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1775
1776 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1777 amc->soc_name = "ast2600-a3";
1778 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1779 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1780 amc->fmc_model = "mx66l1g45g";
1781 amc->spi_model = "mx66l1g45g";
1782 amc->num_cs = 2;
1783 amc->macs_mask = ASPEED_MAC3_ON;
1784 amc->i2c_init = fuji_bmc_i2c_init;
1785 amc->uart_default = ASPEED_DEV_UART1;
1786 mc->auto_create_sdcard = true;
1787 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1788 aspeed_machine_class_init_cpus_defaults(mc);
1789 };
1790
1791 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1792
aspeed_machine_bletchley_class_init(ObjectClass * oc,const void * data)1793 static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
1794 const void *data)
1795 {
1796 MachineClass *mc = MACHINE_CLASS(oc);
1797 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1798
1799 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1800 amc->soc_name = "ast2600-a3";
1801 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1802 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1803 amc->fmc_model = "w25q01jvq";
1804 amc->spi_model = NULL;
1805 amc->num_cs = 2;
1806 amc->macs_mask = ASPEED_MAC2_ON;
1807 amc->i2c_init = bletchley_bmc_i2c_init;
1808 mc->auto_create_sdcard = true;
1809 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1810 aspeed_machine_class_init_cpus_defaults(mc);
1811 }
1812
aspeed_machine_catalina_class_init(ObjectClass * oc,const void * data)1813 static void aspeed_machine_catalina_class_init(ObjectClass *oc,
1814 const void *data)
1815 {
1816 MachineClass *mc = MACHINE_CLASS(oc);
1817 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1818
1819 mc->desc = "Facebook Catalina BMC (Cortex-A7)";
1820 amc->soc_name = "ast2600-a3";
1821 amc->hw_strap1 = CATALINA_BMC_HW_STRAP1;
1822 amc->hw_strap2 = CATALINA_BMC_HW_STRAP2;
1823 amc->fmc_model = "w25q01jvq";
1824 amc->spi_model = NULL;
1825 amc->num_cs = 2;
1826 amc->macs_mask = ASPEED_MAC2_ON;
1827 amc->i2c_init = catalina_bmc_i2c_init;
1828 mc->auto_create_sdcard = true;
1829 mc->default_ram_size = CATALINA_BMC_RAM_SIZE;
1830 aspeed_machine_class_init_cpus_defaults(mc);
1831 aspeed_machine_ast2600_class_emmc_init(oc);
1832 }
1833
1834 #define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
1835
aspeed_machine_gb200nvl_class_init(ObjectClass * oc,const void * data)1836 static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
1837 const void *data)
1838 {
1839 MachineClass *mc = MACHINE_CLASS(oc);
1840 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1841
1842 mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)";
1843 amc->soc_name = "ast2600-a3";
1844 amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
1845 amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
1846 amc->fmc_model = "mx66u51235f";
1847 amc->spi_model = "mx66u51235f";
1848 amc->num_cs = 2;
1849
1850 amc->spi2_model = "mx66u51235f";
1851 amc->num_cs2 = 1;
1852 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1853 amc->i2c_init = gb200nvl_bmc_i2c_init;
1854 mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
1855 aspeed_machine_class_init_cpus_defaults(mc);
1856 aspeed_machine_ast2600_class_emmc_init(oc);
1857 }
1858
fby35_reset(MachineState * state,ResetType type)1859 static void fby35_reset(MachineState *state, ResetType type)
1860 {
1861 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1862 AspeedGPIOState *gpio = &bmc->soc->gpio;
1863
1864 qemu_devices_reset(type);
1865
1866 /* Board ID: 7 (Class-1, 4 slots) */
1867 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1868 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1869 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1870 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1871
1872 /* Slot presence pins, inverse polarity. (False means present) */
1873 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1874 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1875 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1876 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1877
1878 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1879 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1880 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1881 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1882 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1883 }
1884
aspeed_machine_fby35_class_init(ObjectClass * oc,const void * data)1885 static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data)
1886 {
1887 MachineClass *mc = MACHINE_CLASS(oc);
1888 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1889
1890 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1891 mc->reset = fby35_reset;
1892 amc->fmc_model = "mx66l1g45g";
1893 amc->num_cs = 2;
1894 amc->macs_mask = ASPEED_MAC3_ON;
1895 amc->i2c_init = fby35_i2c_init;
1896 mc->auto_create_sdcard = true;
1897 /* FIXME: Replace this macro with something more general */
1898 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1899 aspeed_machine_class_init_cpus_defaults(mc);
1900 }
1901
1902 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1903 /* Main SYSCLK frequency in Hz (200MHz) */
1904 #define SYSCLK_FRQ 200000000ULL
1905
aspeed_minibmc_machine_init(MachineState * machine)1906 static void aspeed_minibmc_machine_init(MachineState *machine)
1907 {
1908 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1909 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1910 Clock *sysclk;
1911
1912 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1913 clock_set_hz(sysclk, SYSCLK_FRQ);
1914
1915 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
1916 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
1917 object_unref(OBJECT(bmc->soc));
1918 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
1919
1920 object_property_set_link(OBJECT(bmc->soc), "memory",
1921 OBJECT(get_system_memory()), &error_abort);
1922 connect_serial_hds_to_uarts(bmc);
1923 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
1924
1925 if (defaults_enabled()) {
1926 aspeed_board_init_flashes(&bmc->soc->fmc,
1927 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1928 amc->num_cs,
1929 0);
1930
1931 aspeed_board_init_flashes(&bmc->soc->spi[0],
1932 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1933 amc->num_cs, amc->num_cs);
1934
1935 aspeed_board_init_flashes(&bmc->soc->spi[1],
1936 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1937 amc->num_cs, (amc->num_cs * 2));
1938 }
1939
1940 if (amc->i2c_init) {
1941 amc->i2c_init(bmc);
1942 }
1943
1944 armv7m_load_kernel(ARM_CPU(first_cpu),
1945 machine->kernel_filename,
1946 0,
1947 AST1030_INTERNAL_FLASH_SIZE);
1948 }
1949
ast1030_evb_i2c_init(AspeedMachineState * bmc)1950 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1951 {
1952 AspeedSoCState *soc = bmc->soc;
1953
1954 /* U10 24C08 connects to SDA/SCL Group 1 by default */
1955 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1956 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1957
1958 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1959 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1960 }
1961
aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass * oc,const void * data)1962 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1963 const void *data)
1964 {
1965 MachineClass *mc = MACHINE_CLASS(oc);
1966 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1967
1968 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1969 amc->soc_name = "ast1030-a1";
1970 amc->hw_strap1 = 0;
1971 amc->hw_strap2 = 0;
1972 mc->init = aspeed_minibmc_machine_init;
1973 amc->i2c_init = ast1030_evb_i2c_init;
1974 mc->default_ram_size = 0;
1975 amc->fmc_model = "w25q80bl";
1976 amc->spi_model = "w25q256";
1977 amc->num_cs = 2;
1978 amc->macs_mask = 0;
1979 aspeed_machine_class_init_cpus_defaults(mc);
1980 }
1981
1982 #ifdef TARGET_AARCH64
ast2700_evb_i2c_init(AspeedMachineState * bmc)1983 static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
1984 {
1985 AspeedSoCState *soc = bmc->soc;
1986
1987 /* LM75 is compatible with TMP105 driver */
1988 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
1989 TYPE_TMP105, 0x4d);
1990 }
1991
aspeed_machine_ast2700a0_evb_class_init(ObjectClass * oc,const void * data)1992 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc,
1993 const void *data)
1994 {
1995 MachineClass *mc = MACHINE_CLASS(oc);
1996 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1997
1998 mc->alias = "ast2700-evb";
1999 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
2000 amc->soc_name = "ast2700-a0";
2001 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
2002 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
2003 amc->fmc_model = "w25q01jvq";
2004 amc->spi_model = "w25q512jv";
2005 amc->num_cs = 2;
2006 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
2007 amc->uart_default = ASPEED_DEV_UART12;
2008 amc->i2c_init = ast2700_evb_i2c_init;
2009 amc->vbootrom = true;
2010 mc->auto_create_sdcard = true;
2011 mc->default_ram_size = 1 * GiB;
2012 aspeed_machine_class_init_cpus_defaults(mc);
2013 }
2014
aspeed_machine_ast2700a1_evb_class_init(ObjectClass * oc,const void * data)2015 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
2016 const void *data)
2017 {
2018 MachineClass *mc = MACHINE_CLASS(oc);
2019 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
2020
2021 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
2022 amc->soc_name = "ast2700-a1";
2023 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
2024 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
2025 amc->fmc_model = "w25q01jvq";
2026 amc->spi_model = "w25q512jv";
2027 amc->num_cs = 2;
2028 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
2029 amc->uart_default = ASPEED_DEV_UART12;
2030 amc->i2c_init = ast2700_evb_i2c_init;
2031 amc->vbootrom = true;
2032 mc->auto_create_sdcard = true;
2033 mc->default_ram_size = 1 * GiB;
2034 aspeed_machine_class_init_cpus_defaults(mc);
2035 }
2036 #endif
2037
aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass * oc,const void * data)2038 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
2039 const void *data)
2040 {
2041 MachineClass *mc = MACHINE_CLASS(oc);
2042 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
2043
2044 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
2045 amc->soc_name = "ast2600-a3";
2046 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
2047 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
2048 amc->fmc_model = "n25q512a";
2049 amc->spi_model = "n25q512a";
2050 amc->num_cs = 2;
2051 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
2052 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
2053 mc->auto_create_sdcard = true;
2054 mc->default_ram_size = 1 * GiB;
2055 aspeed_machine_class_init_cpus_defaults(mc);
2056 };
2057
aspeed_machine_qcom_firework_class_init(ObjectClass * oc,const void * data)2058 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
2059 const void *data)
2060 {
2061 MachineClass *mc = MACHINE_CLASS(oc);
2062 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
2063
2064 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
2065 amc->soc_name = "ast2600-a3";
2066 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
2067 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
2068 amc->fmc_model = "n25q512a";
2069 amc->spi_model = "n25q512a";
2070 amc->num_cs = 2;
2071 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
2072 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
2073 mc->auto_create_sdcard = true;
2074 mc->default_ram_size = 1 * GiB;
2075 aspeed_machine_class_init_cpus_defaults(mc);
2076 };
2077
2078 static const TypeInfo aspeed_machine_types[] = {
2079 {
2080 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
2081 .parent = TYPE_ASPEED_MACHINE,
2082 .class_init = aspeed_machine_palmetto_class_init,
2083 }, {
2084 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
2085 .parent = TYPE_ASPEED_MACHINE,
2086 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
2087 }, {
2088 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
2089 .parent = TYPE_ASPEED_MACHINE,
2090 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
2091 }, {
2092 .name = MACHINE_TYPE_NAME("ast2500-evb"),
2093 .parent = TYPE_ASPEED_MACHINE,
2094 .class_init = aspeed_machine_ast2500_evb_class_init,
2095 }, {
2096 .name = MACHINE_TYPE_NAME("romulus-bmc"),
2097 .parent = TYPE_ASPEED_MACHINE,
2098 .class_init = aspeed_machine_romulus_class_init,
2099 }, {
2100 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
2101 .parent = TYPE_ASPEED_MACHINE,
2102 .class_init = aspeed_machine_sonorapass_class_init,
2103 }, {
2104 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
2105 .parent = TYPE_ASPEED_MACHINE,
2106 .class_init = aspeed_machine_witherspoon_class_init,
2107 }, {
2108 .name = MACHINE_TYPE_NAME("ast2600-evb"),
2109 .parent = TYPE_ASPEED_MACHINE,
2110 .class_init = aspeed_machine_ast2600_evb_class_init,
2111 }, {
2112 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
2113 .parent = TYPE_ASPEED_MACHINE,
2114 .class_init = aspeed_machine_yosemitev2_class_init,
2115 }, {
2116 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
2117 .parent = TYPE_ASPEED_MACHINE,
2118 .class_init = aspeed_machine_tiogapass_class_init,
2119 }, {
2120 .name = MACHINE_TYPE_NAME("g220a-bmc"),
2121 .parent = TYPE_ASPEED_MACHINE,
2122 .class_init = aspeed_machine_g220a_class_init,
2123 }, {
2124 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
2125 .parent = TYPE_ASPEED_MACHINE,
2126 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
2127 }, {
2128 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
2129 .parent = TYPE_ASPEED_MACHINE,
2130 .class_init = aspeed_machine_qcom_firework_class_init,
2131 }, {
2132 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
2133 .parent = TYPE_ASPEED_MACHINE,
2134 .class_init = aspeed_machine_fp5280g2_class_init,
2135 }, {
2136 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
2137 .parent = TYPE_ASPEED_MACHINE,
2138 .class_init = aspeed_machine_quanta_q71l_class_init,
2139 }, {
2140 .name = MACHINE_TYPE_NAME("rainier-bmc"),
2141 .parent = TYPE_ASPEED_MACHINE,
2142 .class_init = aspeed_machine_rainier_class_init,
2143 }, {
2144 .name = MACHINE_TYPE_NAME("fuji-bmc"),
2145 .parent = TYPE_ASPEED_MACHINE,
2146 .class_init = aspeed_machine_fuji_class_init,
2147 }, {
2148 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
2149 .parent = TYPE_ASPEED_MACHINE,
2150 .class_init = aspeed_machine_bletchley_class_init,
2151 }, {
2152 .name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
2153 .parent = TYPE_ASPEED_MACHINE,
2154 .class_init = aspeed_machine_gb200nvl_class_init,
2155 }, {
2156 .name = MACHINE_TYPE_NAME("catalina-bmc"),
2157 .parent = TYPE_ASPEED_MACHINE,
2158 .class_init = aspeed_machine_catalina_class_init,
2159 }, {
2160 .name = MACHINE_TYPE_NAME("fby35-bmc"),
2161 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
2162 .class_init = aspeed_machine_fby35_class_init,
2163 }, {
2164 .name = MACHINE_TYPE_NAME("ast1030-evb"),
2165 .parent = TYPE_ASPEED_MACHINE,
2166 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
2167 #ifdef TARGET_AARCH64
2168 }, {
2169 .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
2170 .parent = TYPE_ASPEED_MACHINE,
2171 .class_init = aspeed_machine_ast2700a0_evb_class_init,
2172 }, {
2173 .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
2174 .parent = TYPE_ASPEED_MACHINE,
2175 .class_init = aspeed_machine_ast2700a1_evb_class_init,
2176 #endif
2177 }, {
2178 .name = TYPE_ASPEED_MACHINE,
2179 .parent = TYPE_MACHINE,
2180 .instance_size = sizeof(AspeedMachineState),
2181 .instance_init = aspeed_machine_instance_init,
2182 .class_size = sizeof(AspeedMachineClass),
2183 .class_init = aspeed_machine_class_init,
2184 .abstract = true,
2185 }
2186 };
2187
2188 DEFINE_TYPES(aspeed_machine_types)
2189