1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) Rockchip Electronics Co., Ltd.
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #ifndef _ROCKCHIP_DRM_VOP2_H
8 #define _ROCKCHIP_DRM_VOP2_H
9
10 #include <linux/regmap.h>
11 #include <drm/drm_modes.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include "rockchip_drm_drv.h"
14 #include "rockchip_drm_vop.h"
15
16 #define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build))
17
18 /* The VOP version of new SoC is bigger than the old */
19 #define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
20 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
21 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
22 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
23 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765)
24
25 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0)
26
27 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0)
28 #define VOP2_FEATURE_HAS_VO0_GRF BIT(1)
29 #define VOP2_FEATURE_HAS_VO1_GRF BIT(2)
30 #define VOP2_FEATURE_HAS_VOP_GRF BIT(3)
31 #define VOP2_FEATURE_HAS_SYS_PMU BIT(4)
32
33 #define WIN_FEATURE_AFBDC BIT(0)
34 #define WIN_FEATURE_CLUSTER BIT(1)
35
36 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l)))
37 /*
38 * the delay number of a window in different mode.
39 */
40 enum win_dly_mode {
41 VOP2_DLY_MODE_DEFAULT, /**< default mode */
42 VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
43 VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
44 VOP2_DLY_MODE_MAX,
45 };
46
47 enum vop2_dly_module {
48 VOP2_DLY_WIN, /** Win delay cycle for this VP */
49 VOP2_DLY_LAYER_MIX, /** Layer Mix delay cycle for this VP */
50 VOP2_DLY_HDR_MIX, /** HDR delay cycle for this VP */
51 VOP2_DLY_MAX,
52 };
53
54 enum vop2_scale_up_mode {
55 VOP2_SCALE_UP_NRST_NBOR,
56 VOP2_SCALE_UP_BIL,
57 VOP2_SCALE_UP_BIC,
58 };
59
60 enum vop2_scale_down_mode {
61 VOP2_SCALE_DOWN_NRST_NBOR,
62 VOP2_SCALE_DOWN_BIL,
63 VOP2_SCALE_DOWN_AVG,
64 };
65
66 /*
67 * vop2 internal power domain id,
68 * should be all none zero, 0 will be treat as invalid;
69 */
70 #define VOP2_PD_CLUSTER0 BIT(0)
71 #define VOP2_PD_CLUSTER1 BIT(1)
72 #define VOP2_PD_CLUSTER2 BIT(2)
73 #define VOP2_PD_CLUSTER3 BIT(3)
74 #define VOP2_PD_DSC_8K BIT(5)
75 #define VOP2_PD_DSC_4K BIT(6)
76 #define VOP2_PD_ESMART BIT(7)
77
78 #define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
79 (x) == ROCKCHIP_VOP2_EP_HDMI1)
80
81 #define vop2_output_if_is_dp(x) ((x) == ROCKCHIP_VOP2_EP_DP0 || \
82 (x) == ROCKCHIP_VOP2_EP_DP1)
83
84 #define vop2_output_if_is_edp(x) ((x) == ROCKCHIP_VOP2_EP_EDP0 || \
85 (x) == ROCKCHIP_VOP2_EP_EDP1)
86
87 #define vop2_output_if_is_mipi(x) ((x) == ROCKCHIP_VOP2_EP_MIPI0 || \
88 (x) == ROCKCHIP_VOP2_EP_MIPI1)
89
90 #define vop2_output_if_is_lvds(x) ((x) == ROCKCHIP_VOP2_EP_LVDS0 || \
91 (x) == ROCKCHIP_VOP2_EP_LVDS1)
92
93 #define vop2_output_if_is_dpi(x) ((x) == ROCKCHIP_VOP2_EP_RGB0)
94
95 enum vop2_win_regs {
96 VOP2_WIN_ENABLE,
97 VOP2_WIN_FORMAT,
98 VOP2_WIN_CSC_MODE,
99 VOP2_WIN_XMIRROR,
100 VOP2_WIN_YMIRROR,
101 VOP2_WIN_RB_SWAP,
102 VOP2_WIN_UV_SWAP,
103 VOP2_WIN_ACT_INFO,
104 VOP2_WIN_DSP_INFO,
105 VOP2_WIN_DSP_ST,
106 VOP2_WIN_YRGB_MST,
107 VOP2_WIN_UV_MST,
108 VOP2_WIN_YRGB_VIR,
109 VOP2_WIN_UV_VIR,
110 VOP2_WIN_YUV_CLIP,
111 VOP2_WIN_Y2R_EN,
112 VOP2_WIN_R2Y_EN,
113 VOP2_WIN_COLOR_KEY,
114 VOP2_WIN_COLOR_KEY_EN,
115 VOP2_WIN_DITHER_UP,
116 VOP2_WIN_AXI_BUS_ID,
117 VOP2_WIN_AXI_YRGB_R_ID,
118 VOP2_WIN_AXI_UV_R_ID,
119
120 /* scale regs */
121 VOP2_WIN_SCALE_YRGB_X,
122 VOP2_WIN_SCALE_YRGB_Y,
123 VOP2_WIN_SCALE_CBCR_X,
124 VOP2_WIN_SCALE_CBCR_Y,
125 VOP2_WIN_YRGB_HOR_SCL_MODE,
126 VOP2_WIN_YRGB_HSCL_FILTER_MODE,
127 VOP2_WIN_YRGB_VER_SCL_MODE,
128 VOP2_WIN_YRGB_VSCL_FILTER_MODE,
129 VOP2_WIN_CBCR_VER_SCL_MODE,
130 VOP2_WIN_CBCR_HSCL_FILTER_MODE,
131 VOP2_WIN_CBCR_HOR_SCL_MODE,
132 VOP2_WIN_CBCR_VSCL_FILTER_MODE,
133 VOP2_WIN_VSD_CBCR_GT2,
134 VOP2_WIN_VSD_CBCR_GT4,
135 VOP2_WIN_VSD_YRGB_GT2,
136 VOP2_WIN_VSD_YRGB_GT4,
137 VOP2_WIN_BIC_COE_SEL,
138
139 /* cluster regs */
140 VOP2_WIN_CLUSTER_ENABLE,
141 VOP2_WIN_AFBC_ENABLE,
142 VOP2_WIN_CLUSTER_LB_MODE,
143
144 /* afbc regs */
145 VOP2_WIN_AFBC_FORMAT,
146 VOP2_WIN_AFBC_RB_SWAP,
147 VOP2_WIN_AFBC_UV_SWAP,
148 VOP2_WIN_AFBC_AUTO_GATING_EN,
149 VOP2_WIN_AFBC_BLOCK_SPLIT_EN,
150 VOP2_WIN_AFBC_PLD_OFFSET_EN,
151 VOP2_WIN_AFBC_PIC_VIR_WIDTH,
152 VOP2_WIN_AFBC_TILE_NUM,
153 VOP2_WIN_AFBC_PIC_OFFSET,
154 VOP2_WIN_AFBC_PIC_SIZE,
155 VOP2_WIN_AFBC_DSP_OFFSET,
156 VOP2_WIN_AFBC_PLD_OFFSET,
157 VOP2_WIN_TRANSFORM_OFFSET,
158 VOP2_WIN_AFBC_HDR_PTR,
159 VOP2_WIN_AFBC_HALF_BLOCK_EN,
160 VOP2_WIN_AFBC_ROTATE_270,
161 VOP2_WIN_AFBC_ROTATE_90,
162
163 VOP2_WIN_VP_SEL,
164 VOP2_WIN_DLY_NUM,
165
166 VOP2_WIN_MAX_REG,
167 };
168
169 struct vop2_regs_dump {
170 const char *name;
171 u32 base;
172 u32 size;
173 u32 en_reg;
174 u32 en_val;
175 u32 en_mask;
176 };
177
178 struct vop2_win_data {
179 const char *name;
180 unsigned int phys_id;
181
182 u32 base;
183 u32 possible_vp_mask;
184 enum drm_plane_type type;
185
186 u32 nformats;
187 const u32 *formats;
188 const uint64_t *format_modifiers;
189 const unsigned int supported_rotations;
190
191 /**
192 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL or PORTn_LAYER_SEL
193 */
194 unsigned int layer_sel_id[ROCKCHIP_MAX_CRTC];
195 uint64_t feature;
196
197 uint8_t axi_bus_id;
198 uint8_t axi_yrgb_r_id;
199 uint8_t axi_uv_r_id;
200
201 unsigned int max_upscale_factor;
202 unsigned int max_downscale_factor;
203 const u8 dly[VOP2_DLY_MODE_MAX];
204 };
205
206 struct vop2_win {
207 struct vop2 *vop2;
208 struct drm_plane base;
209 const struct vop2_win_data *data;
210 struct regmap_field *reg[VOP2_WIN_MAX_REG];
211
212 /**
213 * @win_id: graphic window id, a cluster may be split into two
214 * graphics windows.
215 */
216 u8 win_id;
217 u8 delay;
218 u32 offset;
219
220 enum drm_plane_type type;
221 };
222
223 struct vop2_video_port_data {
224 unsigned int id;
225 u32 feature;
226 u16 gamma_lut_len;
227 u16 cubic_lut_len;
228 struct vop_rect max_output;
229 const u8 pre_scan_max_dly[4];
230 unsigned int offset;
231 /**
232 * @pixel_rate: pixel per cycle
233 */
234 u8 pixel_rate;
235 };
236
237 struct vop2_video_port {
238 struct drm_crtc crtc;
239 struct vop2 *vop2;
240 struct clk *dclk;
241 struct clk *dclk_src;
242 unsigned int id;
243 const struct vop2_video_port_data *data;
244
245 struct completion dsp_hold_completion;
246
247 /**
248 * @win_mask: Bitmask of windows attached to the video port;
249 */
250 u32 win_mask;
251
252 struct vop2_win *primary_plane;
253 struct drm_pending_vblank_event *event;
254
255 unsigned int nlayers;
256 };
257
258 /**
259 * struct vop2_ops - helper operations for vop2 hardware
260 *
261 * These hooks are used by the common part of the vop2 driver to
262 * implement the proper behaviour of different variants.
263 */
264 struct vop2_ops {
265 unsigned long (*setup_intf_mux)(struct vop2_video_port *vp, int ep_id, u32 polflags);
266 void (*setup_bg_dly)(struct vop2_video_port *vp);
267 void (*setup_overlay)(struct vop2_video_port *vp);
268 };
269
270 struct vop2_data {
271 u8 nr_vps;
272 u64 feature;
273 u32 version;
274 const struct vop2_ops *ops;
275 const struct vop2_win_data *win;
276 const struct vop2_video_port_data *vp;
277 const struct reg_field *cluster_reg;
278 const struct reg_field *smart_reg;
279 const struct vop2_regs_dump *regs_dump;
280 struct vop_rect max_input;
281 struct vop_rect max_output;
282
283 unsigned int nr_cluster_regs;
284 unsigned int nr_smart_regs;
285 unsigned int win_size;
286 unsigned int regs_dump_size;
287 unsigned int soc_id;
288 };
289
290 struct vop2 {
291 u32 version;
292 struct device *dev;
293 struct drm_device *drm;
294 struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
295
296 const struct vop2_data *data;
297 const struct vop2_ops *ops;
298 /*
299 * Number of windows that are registered as plane, may be less than the
300 * total number of hardware windows.
301 */
302 u32 registered_num_wins;
303
304 struct resource *res;
305 void __iomem *regs;
306 struct regmap *map;
307
308 struct regmap *sys_grf;
309 struct regmap *vop_grf;
310 struct regmap *vo1_grf;
311 struct regmap *sys_pmu;
312
313 /* physical map length of vop2 register */
314 u32 len;
315
316 void __iomem *lut_regs;
317
318 /* protects crtc enable/disable */
319 struct mutex vop2_lock;
320
321 int irq;
322
323 /*
324 * Some global resources are shared between all video ports(crtcs), so
325 * we need a ref counter here.
326 */
327 unsigned int enable_count;
328 struct clk *hclk;
329 struct clk *aclk;
330 struct clk *pclk;
331 struct clk *pll_hdmiphy0;
332 struct clk *pll_hdmiphy1;
333
334 /* optional internal rgb encoder */
335 struct rockchip_rgb *rgb;
336
337 /*
338 * Used to record layer selection configuration on rk356x/rk3588
339 * as register RK3568_OVL_LAYER_SEL and RK3568_OVL_PORT_SEL are
340 * shared for all the Video Ports.
341 */
342 u32 old_layer_sel;
343 u32 old_port_sel;
344 /*
345 * Ensure that the updates to these two registers(RKK3568_OVL_LAYER_SEL/RK3568_OVL_PORT_SEL)
346 * take effect in sequence.
347 */
348 struct mutex ovl_lock;
349
350 /* must be put at the end of the struct */
351 struct vop2_win win[];
352 };
353
354 /* interrupt define */
355 #define FS_NEW_INTR BIT(4)
356 #define ADDR_SAME_INTR BIT(5)
357 #define LINE_FLAG1_INTR BIT(6)
358 #define WIN0_EMPTY_INTR BIT(7)
359 #define WIN1_EMPTY_INTR BIT(8)
360 #define WIN2_EMPTY_INTR BIT(9)
361 #define WIN3_EMPTY_INTR BIT(10)
362 #define HWC_EMPTY_INTR BIT(11)
363 #define POST_BUF_EMPTY_INTR BIT(12)
364 #define PWM_GEN_INTR BIT(13)
365 #define DMA_FINISH_INTR BIT(14)
366 #define FS_FIELD_INTR BIT(15)
367 #define FE_INTR BIT(16)
368 #define WB_UV_FIFO_FULL_INTR BIT(17)
369 #define WB_YRGB_FIFO_FULL_INTR BIT(18)
370 #define WB_COMPLETE_INTR BIT(19)
371
372
373 enum vop_csc_format {
374 CSC_BT601L,
375 CSC_BT709L,
376 CSC_BT601F,
377 CSC_BT2020,
378 };
379
380 enum src_factor_mode {
381 SRC_FAC_ALPHA_ZERO,
382 SRC_FAC_ALPHA_ONE,
383 SRC_FAC_ALPHA_DST,
384 SRC_FAC_ALPHA_DST_INVERSE,
385 SRC_FAC_ALPHA_SRC,
386 SRC_FAC_ALPHA_SRC_GLOBAL,
387 };
388
389 enum dst_factor_mode {
390 DST_FAC_ALPHA_ZERO,
391 DST_FAC_ALPHA_ONE,
392 DST_FAC_ALPHA_SRC,
393 DST_FAC_ALPHA_SRC_INVERSE,
394 DST_FAC_ALPHA_DST,
395 DST_FAC_ALPHA_DST_GLOBAL,
396 };
397
398 #define RK3568_GRF_VO_CON1 0x0364
399
400 #define RK3588_GRF_SOC_CON1 0x0304
401 #define RK3588_GRF_VOP_CON2 0x08
402 #define RK3588_GRF_VO1_CON0 0x00
403
404 /* System registers definition */
405 #define RK3568_REG_CFG_DONE 0x000
406 #define RK3568_VERSION_INFO 0x004
407 #define RK3568_SYS_AUTO_GATING_CTRL 0x008
408 #define RK3576_SYS_MMU_CTRL_IMD 0x020
409 #define RK3568_SYS_AXI_LUT_CTRL 0x024
410 #define RK3568_DSP_IF_EN 0x028
411 #define RK3576_SYS_PORT_CTRL_IMD 0x028
412 #define RK3568_DSP_IF_CTRL 0x02c
413 #define RK3568_DSP_IF_POL 0x030
414 #define RK3576_SYS_CLUSTER_PD_CTRL_IMD 0x030
415 #define RK3588_SYS_PD_CTRL 0x034
416 #define RK3568_WB_CTRL 0x40
417 #define RK3568_WB_XSCAL_FACTOR 0x44
418 #define RK3568_WB_YRGB_MST 0x48
419 #define RK3568_WB_CBR_MST 0x4C
420 #define RK3568_OTP_WIN_EN 0x050
421 #define RK3568_LUT_PORT_SEL 0x058
422 #define RK3568_SYS_STATUS0 0x060
423 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4)
424 #define RK3568_SYS0_INT_EN 0x80
425 #define RK3568_SYS0_INT_CLR 0x84
426 #define RK3568_SYS0_INT_STATUS 0x88
427 #define RK3568_SYS1_INT_EN 0x90
428 #define RK3568_SYS1_INT_CLR 0x94
429 #define RK3568_SYS1_INT_STATUS 0x98
430 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10)
431 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10)
432 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10)
433 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10)
434 #define RK3576_WB_CTRL 0x100
435 #define RK3576_WB_XSCAL_FACTOR 0x104
436 #define RK3576_WB_YRGB_MST 0x108
437 #define RK3576_WB_CBR_MST 0x10C
438 #define RK3576_WB_VIR_STRIDE 0x110
439 #define RK3576_WB_TIMEOUT_CTRL 0x114
440 #define RK3576_MIPI0_IF_CTRL 0x180
441 #define RK3576_HDMI0_IF_CTRL 0x184
442 #define RK3576_EDP0_IF_CTRL 0x188
443 #define RK3576_DP0_IF_CTRL 0x18C
444 #define RK3576_RGB_IF_CTRL 0x194
445 #define RK3576_DP1_IF_CTRL 0x1A4
446 #define RK3576_DP2_IF_CTRL 0x1B0
447
448 /* Extra OVL register definition */
449 #define RK3576_SYS_EXTRA_ALPHA_CTRL 0x500
450 #define RK3576_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530
451 #define RK3576_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
452 #define RK3576_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
453 #define RK3576_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
454 #define RK3576_CLUSTER1_MIX_SRC_COLOR_CTRL 0x540
455 #define RK3576_CLUSTER1_MIX_DST_COLOR_CTRL 0x544
456 #define RK3576_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x548
457 #define RK3576_CLUSTER1_MIX_DST_ALPHA_CTRL 0x54c
458
459 /* OVL registers for Video Port definition */
460 #define RK3576_OVL_CTRL(vp) (0x600 + (vp) * 0x100)
461 #define RK3576_OVL_LAYER_SEL(vp) (0x604 + (vp) * 0x100)
462 #define RK3576_OVL_MIX0_SRC_COLOR_CTRL(vp) (0x620 + (vp) * 0x100)
463 #define RK3576_OVL_MIX0_DST_COLOR_CTRL(vp) (0x624 + (vp) * 0x100)
464 #define RK3576_OVL_MIX0_SRC_ALPHA_CTRL(vp) (0x628 + (vp) * 0x100)
465 #define RK3576_OVL_MIX0_DST_ALPHA_CTRL(vp) (0x62C + (vp) * 0x100)
466 #define RK3576_OVL_MIX1_SRC_COLOR_CTRL(vp) (0x630 + (vp) * 0x100)
467 #define RK3576_OVL_MIX1_DST_COLOR_CTRL(vp) (0x634 + (vp) * 0x100)
468 #define RK3576_OVL_MIX1_SRC_ALPHA_CTRL(vp) (0x638 + (vp) * 0x100)
469 #define RK3576_OVL_MIX1_DST_ALPHA_CTRL(vp) (0x63C + (vp) * 0x100)
470 #define RK3576_OVL_MIX2_SRC_COLOR_CTRL(vp) (0x640 + (vp) * 0x100)
471 #define RK3576_OVL_MIX2_DST_COLOR_CTRL(vp) (0x644 + (vp) * 0x100)
472 #define RK3576_OVL_MIX2_SRC_ALPHA_CTRL(vp) (0x648 + (vp) * 0x100)
473 #define RK3576_OVL_MIX2_DST_ALPHA_CTRL(vp) (0x64C + (vp) * 0x100)
474 #define RK3576_EXTRA_OVL_SRC_COLOR_CTRL(vp) (0x650 + (vp) * 0x100)
475 #define RK3576_EXTRA_OVL_DST_COLOR_CTRL(vp) (0x654 + (vp) * 0x100)
476 #define RK3576_EXTRA_OVL_SRC_ALPHA_CTRL(vp) (0x658 + (vp) * 0x100)
477 #define RK3576_EXTRA_OVL_DST_ALPHA_CTRL(vp) (0x65C + (vp) * 0x100)
478 #define RK3576_OVL_HDR_SRC_COLOR_CTRL(vp) (0x660 + (vp) * 0x100)
479 #define RK3576_OVL_HDR_DST_COLOR_CTRL(vp) (0x664 + (vp) * 0x100)
480 #define RK3576_OVL_HDR_SRC_ALPHA_CTRL(vp) (0x668 + (vp) * 0x100)
481 #define RK3576_OVL_HDR_DST_ALPHA_CTRL(vp) (0x66C + (vp) * 0x100)
482 #define RK3576_OVL_BG_MIX_CTRL(vp) (0x670 + (vp) * 0x100)
483
484 /* Video Port registers definition */
485 #define RK3568_VP0_CTRL_BASE 0x0C00
486 #define RK3568_VP1_CTRL_BASE 0x0D00
487 #define RK3568_VP2_CTRL_BASE 0x0E00
488 #define RK3588_VP3_CTRL_BASE 0x0F00
489 #define RK3568_VP_DSP_CTRL 0x00
490 #define RK3568_VP_MIPI_CTRL 0x04
491 #define RK3568_VP_COLOR_BAR_CTRL 0x08
492 #define RK3588_VP_CLK_CTRL 0x0C
493 #define RK3568_VP_3D_LUT_CTRL 0x10
494 #define RK3568_VP_3D_LUT_MST 0x20
495 #define RK3568_VP_DSP_BG 0x2C
496 #define RK3568_VP_PRE_SCAN_HTIMING 0x30
497 #define RK3568_VP_POST_DSP_HACT_INFO 0x34
498 #define RK3568_VP_POST_DSP_VACT_INFO 0x38
499 #define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C
500 #define RK3568_VP_POST_SCL_CTRL 0x40
501 #define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44
502 #define RK3568_VP_DSP_HTOTAL_HS_END 0x48
503 #define RK3568_VP_DSP_HACT_ST_END 0x4C
504 #define RK3568_VP_DSP_VTOTAL_VS_END 0x50
505 #define RK3568_VP_DSP_VACT_ST_END 0x54
506 #define RK3568_VP_DSP_VS_ST_END_F1 0x58
507 #define RK3568_VP_DSP_VACT_ST_END_F1 0x5C
508 #define RK3568_VP_BCSH_CTRL 0x60
509 #define RK3568_VP_BCSH_BCS 0x64
510 #define RK3568_VP_BCSH_H 0x68
511 #define RK3568_VP_BCSH_COLOR_BAR 0x6C
512
513 /* Overlay registers definition */
514 #define RK3568_OVL_CTRL 0x600
515 #define RK3568_OVL_LAYER_SEL 0x604
516 #define RK3568_OVL_PORT_SEL 0x608
517 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
518 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
519 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
520 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
521 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650
522 #define RK3568_MIX0_DST_COLOR_CTRL 0x654
523 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
524 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
525 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
526 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
527 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
528 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
529 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4)
530 #define RK3568_CLUSTER_DLY_NUM 0x6F0
531 #define RK3568_SMART_DLY_NUM 0x6F8
532
533 /* Cluster register definition, offset relative to window base */
534 #define RK3568_CLUSTER0_CTRL_BASE 0x1000
535 #define RK3568_CLUSTER1_CTRL_BASE 0x1200
536 #define RK3588_CLUSTER2_CTRL_BASE 0x1400
537 #define RK3588_CLUSTER3_CTRL_BASE 0x1600
538 #define RK3568_ESMART0_CTRL_BASE 0x1800
539 #define RK3568_ESMART1_CTRL_BASE 0x1A00
540 #define RK3568_SMART0_CTRL_BASE 0x1C00
541 #define RK3568_SMART1_CTRL_BASE 0x1E00
542 #define RK3588_ESMART2_CTRL_BASE 0x1C00
543 #define RK3588_ESMART3_CTRL_BASE 0x1E00
544
545 #define RK3568_CLUSTER_WIN_CTRL0 0x00
546 #define RK3568_CLUSTER_WIN_CTRL1 0x04
547 #define RK3568_CLUSTER_WIN_CTRL2 0x08
548 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10
549 #define RK3568_CLUSTER_WIN_CBR_MST 0x14
550 #define RK3568_CLUSTER_WIN_VIR 0x18
551 #define RK3568_CLUSTER_WIN_ACT_INFO 0x20
552 #define RK3568_CLUSTER_WIN_DSP_INFO 0x24
553 #define RK3568_CLUSTER_WIN_DSP_ST 0x28
554 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30
555 #define RK3568_CLUSTER_WIN_TRANSFORM_OFFSET 0x3C
556 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50
557 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54
558 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58
559 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C
560 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60
561 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
562 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68
563 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C
564
565 #define RK3576_CLUSTER_WIN_AFBCD_PLD_PTR_OFFSET 0x78
566
567 #define RK3568_CLUSTER_CTRL 0x100
568 #define RK3576_CLUSTER_PORT_SEL_IMD 0x1F4
569 #define RK3576_CLUSTER_DLY_NUM 0x1F8
570
571 /* (E)smart register definition, offset relative to window base */
572 #define RK3568_SMART_CTRL0 0x00
573 #define RK3568_SMART_CTRL1 0x04
574 #define RK3588_SMART_AXI_CTRL 0x08
575 #define RK3568_SMART_REGION0_CTRL 0x10
576 #define RK3568_SMART_REGION0_YRGB_MST 0x14
577 #define RK3568_SMART_REGION0_CBR_MST 0x18
578 #define RK3568_SMART_REGION0_VIR 0x1C
579 #define RK3568_SMART_REGION0_ACT_INFO 0x20
580 #define RK3568_SMART_REGION0_DSP_INFO 0x24
581 #define RK3568_SMART_REGION0_DSP_ST 0x28
582 #define RK3568_SMART_REGION0_SCL_CTRL 0x30
583 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34
584 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38
585 #define RK3568_SMART_REGION0_SCL_OFFSET 0x3C
586 #define RK3568_SMART_REGION1_CTRL 0x40
587 #define RK3568_SMART_REGION1_YRGB_MST 0x44
588 #define RK3568_SMART_REGION1_CBR_MST 0x48
589 #define RK3568_SMART_REGION1_VIR 0x4C
590 #define RK3568_SMART_REGION1_ACT_INFO 0x50
591 #define RK3568_SMART_REGION1_DSP_INFO 0x54
592 #define RK3568_SMART_REGION1_DSP_ST 0x58
593 #define RK3568_SMART_REGION1_SCL_CTRL 0x60
594 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
595 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68
596 #define RK3568_SMART_REGION1_SCL_OFFSET 0x6C
597 #define RK3568_SMART_REGION2_CTRL 0x70
598 #define RK3568_SMART_REGION2_YRGB_MST 0x74
599 #define RK3568_SMART_REGION2_CBR_MST 0x78
600 #define RK3568_SMART_REGION2_VIR 0x7C
601 #define RK3568_SMART_REGION2_ACT_INFO 0x80
602 #define RK3568_SMART_REGION2_DSP_INFO 0x84
603 #define RK3568_SMART_REGION2_DSP_ST 0x88
604 #define RK3568_SMART_REGION2_SCL_CTRL 0x90
605 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94
606 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98
607 #define RK3568_SMART_REGION2_SCL_OFFSET 0x9C
608 #define RK3568_SMART_REGION3_CTRL 0xA0
609 #define RK3568_SMART_REGION3_YRGB_MST 0xA4
610 #define RK3568_SMART_REGION3_CBR_MST 0xA8
611 #define RK3568_SMART_REGION3_VIR 0xAC
612 #define RK3568_SMART_REGION3_ACT_INFO 0xB0
613 #define RK3568_SMART_REGION3_DSP_INFO 0xB4
614 #define RK3568_SMART_REGION3_DSP_ST 0xB8
615 #define RK3568_SMART_REGION3_SCL_CTRL 0xC0
616 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4
617 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8
618 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC
619 #define RK3568_SMART_COLOR_KEY_CTRL 0xD0
620 #define RK3576_SMART_ALPHA_MAP 0xD8
621 #define RK3576_SMART_PORT_SEL_IMD 0xF4
622 #define RK3576_SMART_DLY_NUM 0xF8
623
624 /* HDR register definition */
625 #define RK3568_HDR_LUT_CTRL 0x2000
626 #define RK3568_HDR_LUT_MST 0x2004
627 #define RK3568_SDR2HDR_CTRL 0x2010
628 #define RK3568_HDR2SDR_CTRL 0x2020
629 #define RK3568_HDR2SDR_SRC_RANGE 0x2024
630 #define RK3568_HDR2SDR_NORMFACEETF 0x2028
631 #define RK3568_HDR2SDR_DST_RANGE 0x202C
632 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030
633 #define RK3568_HDR_EETF_OETF_Y0 0x203C
634 #define RK3568_HDR_SAT_Y0 0x20C0
635 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0
636 #define RK3568_HDR_OETF_DX_POW1 0x2200
637 #define RK3568_HDR_OETF_XN1 0x2300
638
639 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15)
640
641 #define RK3568_VP_DSP_CTRL__STANDBY BIT(31)
642 #define RK3568_VP_DSP_CTRL__DSP_LUT_EN BIT(28)
643 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20)
644 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18)
645 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17)
646 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16)
647 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15)
648 #define RK3568_VP_DSP_CTRL__DSP_RG_SWAP BIT(10)
649 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9)
650 #define RK3568_VP_DSP_CTRL__DSP_BG_SWAP BIT(8)
651 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7)
652 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6)
653 #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5)
654 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4)
655 #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0)
656
657 #define RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN BIT(22)
658
659 #define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2)
660 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0)
661
662 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1)
663 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
664
665 #define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25)
666 #define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24)
667 #define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21)
668 #define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20)
669 #define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18)
670 #define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16)
671 #define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14)
672 #define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10)
673 #define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8)
674 #define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5)
675 #define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4)
676 #define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3)
677 #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1)
678 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
679
680 #define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21)
681 #define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(20, 20)
682 #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX GENMASK(19, 18)
683 #define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX GENMASK(17, 16)
684 #define RK3588_SYS_DSP_INFACE_EN_DP1_MUX GENMASK(15, 14)
685 #define RK3588_SYS_DSP_INFACE_EN_DP0_MUX GENMASK(13, 12)
686 #define RK3588_SYS_DSP_INFACE_EN_DPI GENMASK(9, 8)
687 #define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7)
688 #define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6)
689 #define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5)
690 #define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4)
691 #define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3)
692 #define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2)
693 #define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1)
694 #define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0)
695
696 #define RK3588_DSP_IF_MIPI1_PCLK_DIV GENMASK(27, 26)
697 #define RK3588_DSP_IF_MIPI0_PCLK_DIV GENMASK(25, 24)
698 #define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV GENMASK(22, 22)
699 #define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV GENMASK(21, 20)
700 #define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV GENMASK(18, 18)
701 #define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV GENMASK(17, 16)
702
703 #define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16)
704 #define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12)
705 #define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4)
706 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0)
707
708 #define RK3588_DSP_IF_POL__DP1_PIN_POL GENMASK(14, 12)
709 #define RK3588_DSP_IF_POL__DP0_PIN_POL GENMASK(10, 8)
710
711 #define RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL GENMASK(13, 12)
712
713 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5)
714 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4)
715
716 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31)
717
718 #define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28)
719
720 #define VOP2_SYS_AXI_BUS_NUM 2
721
722 #define VOP2_CLUSTER_YUV444_10 0x12
723
724 #define VOP2_COLOR_KEY_MASK BIT(31)
725
726 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL GENMASK(31, 30)
727 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28)
728 #define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp)
729
730 #define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24)
731
732 #define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16)
733 #define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30)
734 #define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28)
735 #define RK3588_OVL_PORT_SEL__ESMART3 GENMASK(31, 30)
736 #define RK3588_OVL_PORT_SEL__ESMART2 GENMASK(29, 28)
737 #define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26)
738 #define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24)
739 #define RK3588_OVL_PORT_SEL__CLUSTER3 GENMASK(23, 22)
740 #define RK3588_OVL_PORT_SEL__CLUSTER2 GENMASK(21, 20)
741 #define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18)
742 #define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16)
743 #define RK3588_OVL_PORT_SET__PORT3_MUX GENMASK(15, 12)
744 #define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8)
745 #define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4)
746 #define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0)
747 #define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4))
748
749 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24)
750 #define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16)
751 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8)
752 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0)
753
754 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0)
755
756 #define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0)
757
758 #define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24)
759 #define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16)
760 #define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8)
761 #define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0)
762
763 #define VP_INT_DSP_HOLD_VALID BIT(6)
764 #define VP_INT_FS_FIELD BIT(5)
765 #define VP_INT_POST_BUF_EMPTY BIT(4)
766 #define VP_INT_LINE_FLAG1 BIT(3)
767 #define VP_INT_LINE_FLAG0 BIT(2)
768 #define VOP2_INT_BUS_ERRPR BIT(1)
769 #define VP_INT_FS BIT(0)
770
771 #define POLFLAG_DCLK_INV BIT(3)
772
773 #define RK3576_OVL_CTRL__YUV_MODE BIT(0)
774 #define RK3576_OVL_BG_MIX_CTRL__BG_DLY GENMASK(31, 24)
775
776 #define RK3576_DSP_IF_CFG_DONE_IMD BIT(31)
777 #define RK3576_DSP_IF_DCLK_SEL_OUT BIT(21)
778 #define RK3576_DSP_IF_PCLK_DIV BIT(20)
779 #define RK3576_DSP_IF_PIN_POL GENMASK(5, 4)
780 #define RK3576_DSP_IF_MUX GENMASK(3, 2)
781 #define RK3576_DSP_IF_CLK_OUT_EN BIT(1)
782 #define RK3576_DSP_IF_EN BIT(0)
783
784 enum vop2_layer_phy_id {
785 ROCKCHIP_VOP2_CLUSTER0 = 0,
786 ROCKCHIP_VOP2_CLUSTER1,
787 ROCKCHIP_VOP2_ESMART0,
788 ROCKCHIP_VOP2_ESMART1,
789 ROCKCHIP_VOP2_SMART0,
790 ROCKCHIP_VOP2_SMART1,
791 ROCKCHIP_VOP2_CLUSTER2,
792 ROCKCHIP_VOP2_CLUSTER3,
793 ROCKCHIP_VOP2_ESMART2,
794 ROCKCHIP_VOP2_ESMART3,
795 ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
796 };
797
798 extern const struct component_ops vop2_component_ops;
799
vop2_writel(struct vop2 * vop2,u32 offset,u32 v)800 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
801 {
802 regmap_write(vop2->map, offset, v);
803 }
804
vop2_vp_write(struct vop2_video_port * vp,u32 offset,u32 v)805 static inline void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
806 {
807 regmap_write(vp->vop2->map, vp->data->offset + offset, v);
808 }
809
vop2_readl(struct vop2 * vop2,u32 offset)810 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset)
811 {
812 u32 val;
813
814 regmap_read(vop2->map, offset, &val);
815
816 return val;
817 }
818
vop2_vp_read(struct vop2_video_port * vp,u32 offset)819 static inline u32 vop2_vp_read(struct vop2_video_port *vp, u32 offset)
820 {
821 u32 val;
822
823 regmap_read(vp->vop2->map, vp->data->offset + offset, &val);
824
825 return val;
826 }
827
vop2_win_write(const struct vop2_win * win,unsigned int reg,u32 v)828 static inline void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
829 {
830 regmap_field_write(win->reg[reg], v);
831 }
832
vop2_cluster_window(const struct vop2_win * win)833 static inline bool vop2_cluster_window(const struct vop2_win *win)
834 {
835 return win->data->feature & WIN_FEATURE_CLUSTER;
836 }
837
to_vop2_video_port(struct drm_crtc * crtc)838 static inline struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
839 {
840 return container_of(crtc, struct vop2_video_port, crtc);
841 }
842
to_vop2_win(struct drm_plane * p)843 static inline struct vop2_win *to_vop2_win(struct drm_plane *p)
844 {
845 return container_of(p, struct vop2_win, base);
846 }
847
848 /*
849 * Note:
850 * The write mask function is documented but missing on rk3566/8, writes
851 * to these bits have no effect. For newer soc(rk3588 and following) the
852 * write mask is needed for register writes.
853 *
854 * GLB_CFG_DONE_EN has no write mask bit.
855 *
856 */
vop2_cfg_done(struct vop2_video_port * vp)857 static inline void vop2_cfg_done(struct vop2_video_port *vp)
858 {
859 struct vop2 *vop2 = vp->vop2;
860 u32 val = RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN;
861
862 val |= BIT(vp->id) | (BIT(vp->id) << 16);
863
864 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val);
865 }
866
867 #endif /* _ROCKCHIP_DRM_VOP2_H */
868