1 /* 2 * RISC-V cpu parameters for qemu. 3 * 4 * Copyright (c) 2017-2018 SiFive, Inc. 5 * SPDX-License-Identifier: GPL-2.0-or-later 6 */ 7 8 #ifndef RISCV_CPU_PARAM_H 9 #define RISCV_CPU_PARAM_H 10 11 #if defined(TARGET_RISCV64) 12 # define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ 13 # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ 14 #elif defined(TARGET_RISCV32) 15 # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ 16 # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ 17 #endif 18 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ 19 20 /* 21 * RISC-V-specific extra insn start words: 22 * 1: Original instruction opcode 23 * 2: more information about instruction 24 */ 25 #define TARGET_INSN_START_EXTRA_WORDS 2 26 27 /* 28 * The current MMU Modes are: 29 * - U mode 0b000 30 * - S mode 0b001 31 * - M mode 0b011 32 * - U mode HLV/HLVX/HSV 0b100 33 * - S mode HLV/HLVX/HSV 0b101 34 * - M mode HLV/HLVX/HSV 0b111 35 */ 36 37 #endif 38