1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2024 Intel Corporation */ 3 4 #ifndef _QUICKSPI_DEV_H_ 5 #define _QUICKSPI_DEV_H_ 6 7 #include <linux/bits.h> 8 #include <linux/hid-over-spi.h> 9 #include <linux/sizes.h> 10 #include <linux/wait.h> 11 12 #include "quickspi-protocol.h" 13 14 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT1 0x7E49 15 #define PCI_DEVICE_ID_INTEL_THC_MTL_DEVICE_ID_SPI_PORT2 0x7E4B 16 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT1 0xA849 17 #define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_SPI_PORT2 0xA84B 18 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT1 0xE349 19 #define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_SPI_PORT2 0xE34B 20 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT1 0xE449 21 #define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_SPI_PORT2 0xE44B 22 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT1 0x4D49 23 #define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_SPI_PORT2 0x4D4B 24 #define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT1 0x7749 25 #define PCI_DEVICE_ID_INTEL_THC_ARL_DEVICE_ID_SPI_PORT2 0x774B 26 #define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT1 0xD349 27 #define PCI_DEVICE_ID_INTEL_THC_NVL_H_DEVICE_ID_SPI_PORT2 0xD34B 28 29 /* HIDSPI special ACPI parameters DSM methods */ 30 #define ACPI_QUICKSPI_REVISION_NUM 2 31 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_HDR_ADDR 1 32 #define ACPI_QUICKSPI_FUNC_NUM_INPUT_REP_BDY_ADDR 2 33 #define ACPI_QUICKSPI_FUNC_NUM_OUTPUT_REP_ADDR 3 34 #define ACPI_QUICKSPI_FUNC_NUM_READ_OPCODE 4 35 #define ACPI_QUICKSPI_FUNC_NUM_WRITE_OPCODE 5 36 #define ACPI_QUICKSPI_FUNC_NUM_IO_MODE 6 37 38 /* QickSPI device special ACPI parameters DSM methods */ 39 #define ACPI_QUICKSPI_FUNC_NUM_CONNECTION_SPEED 1 40 #define ACPI_QUICKSPI_FUNC_NUM_LIMIT_PACKET_SIZE 2 41 #define ACPI_QUICKSPI_FUNC_NUM_PERFORMANCE_LIMIT 3 42 43 /* Platform special ACPI parameters DSM methods */ 44 #define ACPI_QUICKSPI_FUNC_NUM_ACTIVE_LTR 1 45 #define ACPI_QUICKSPI_FUNC_NUM_LP_LTR 2 46 47 #define SPI_WRITE_IO_MODE BIT(13) 48 #define SPI_IO_MODE_OPCODE GENMASK(15, 14) 49 #define PERFORMANCE_LIMITATION GENMASK(15, 0) 50 51 /* Packet size value, the unit is 16 bytes */ 52 #define DEFAULT_MIN_PACKET_SIZE_VALUE 4 53 #define MAX_PACKET_SIZE_VALUE_MTL 128 54 #define MAX_PACKET_SIZE_VALUE_LNL 256 55 56 /* 57 * THC uses runtime auto suspend to dynamically switch between THC active LTR 58 * and low power LTR to save CPU power. 59 * Default value is 5000ms, that means if no touch event in this time, THC will 60 * change to low power LTR mode. 61 */ 62 #define DEFAULT_AUTO_SUSPEND_DELAY_MS 5000 63 64 enum quickspi_dev_state { 65 QUICKSPI_NONE, 66 QUICKSPI_INITIATED, 67 QUICKSPI_RESETING, 68 QUICKSPI_RESET, 69 QUICKSPI_ENABLED, 70 QUICKSPI_DISABLED, 71 }; 72 73 /** 74 * struct quickspi_driver_data - Driver specific data for quickspi device 75 * @max_packet_size_value: identify max packet size, unit is 16 bytes 76 */ 77 struct quickspi_driver_data { 78 u32 max_packet_size_value; 79 }; 80 81 struct device; 82 struct pci_dev; 83 struct thc_device; 84 struct hid_device; 85 struct acpi_device; 86 87 /** 88 * struct quickspi_device - THC QuickSpi device struct 89 * @dev: point to kernel device 90 * @pdev: point to PCI device 91 * @thc_hw: point to THC device 92 * @hid_dev: point to hid device 93 * @acpi_dev: point to ACPI device 94 * @driver_data: point to quickspi specific driver data 95 * @state: THC SPI device state 96 * @mem_addr: MMIO memory address 97 * @dev_desc: device descriptor for HIDSPI protocol 98 * @input_report_hdr_addr: device input report header address 99 * @input_report_bdy_addr: device input report body address 100 * @output_report_bdy_addr: device output report address 101 * @spi_freq_val: device supported max SPI frequnecy, in Hz 102 * @spi_read_io_mode: device supported SPI read io mode 103 * @spi_write_io_mode: device supported SPI write io mode 104 * @spi_read_opcode: device read opcode 105 * @spi_write_opcode: device write opcode 106 * @limit_packet_size: 1 - limit read/write packet to 64Bytes 107 * 0 - device no packet size limiation for read/write 108 * @performance_limit: delay time, in ms. 109 * if device has performance limitation, must give a delay 110 * before write operation after a read operation. 111 * @active_ltr_val: THC active LTR value 112 * @low_power_ltr_val: THC low power LTR value 113 * @report_descriptor: store a copy of device report descriptor 114 * @input_buf: store a copy of latest input report data 115 * @report_buf: store a copy of latest input/output report packet from set/get feature 116 * @report_len: the length of input/output report packet 117 * @reset_ack_wq: workqueue for waiting reset response from device 118 * @reset_ack: indicate reset response received or not 119 * @nondma_int_received_wq: workqueue for waiting THC non-DMA interrupt 120 * @nondma_int_received: indicate THC non-DMA interrupt received or not 121 * @report_desc_got_wq: workqueue for waiting device report descriptor 122 * @report_desc_got: indicate device report descritor received or not 123 * @set_power_on_wq: workqueue for waiting set power on response from device 124 * @set_power_on: indicate set power on response received or not 125 * @get_feature_cmpl_wq: workqueue for waiting get feature response from device 126 * @get_feature_cmpl: indicate get feature received or not 127 * @set_feature_cmpl_wq: workqueue for waiting set feature to device 128 * @set_feature_cmpl: indicate set feature send complete or not 129 */ 130 struct quickspi_device { 131 struct device *dev; 132 struct pci_dev *pdev; 133 struct thc_device *thc_hw; 134 struct hid_device *hid_dev; 135 struct acpi_device *acpi_dev; 136 struct quickspi_driver_data *driver_data; 137 enum quickspi_dev_state state; 138 139 void __iomem *mem_addr; 140 141 struct hidspi_dev_descriptor dev_desc; 142 u32 input_report_hdr_addr; 143 u32 input_report_bdy_addr; 144 u32 output_report_addr; 145 u32 spi_freq_val; 146 u32 spi_read_io_mode; 147 u32 spi_write_io_mode; 148 u32 spi_read_opcode; 149 u32 spi_write_opcode; 150 u32 limit_packet_size; 151 u32 spi_packet_size; 152 u32 performance_limit; 153 154 u32 active_ltr_val; 155 u32 low_power_ltr_val; 156 157 u8 *report_descriptor; 158 u8 *input_buf; 159 u8 *report_buf; 160 u32 report_len; 161 162 wait_queue_head_t reset_ack_wq; 163 bool reset_ack; 164 165 wait_queue_head_t nondma_int_received_wq; 166 bool nondma_int_received; 167 168 wait_queue_head_t report_desc_got_wq; 169 bool report_desc_got; 170 171 wait_queue_head_t get_report_cmpl_wq; 172 bool get_report_cmpl; 173 174 wait_queue_head_t set_report_cmpl_wq; 175 bool set_report_cmpl; 176 }; 177 178 #endif /* _QUICKSPI_DEV_H_ */ 179