1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU_13_0_12_PMFW_H 24 #define SMU_13_0_12_PMFW_H 25 26 #define NUM_VCLK_DPM_LEVELS 4 27 #define NUM_DCLK_DPM_LEVELS 4 28 #define NUM_SOCCLK_DPM_LEVELS 4 29 #define NUM_LCLK_DPM_LEVELS 4 30 #define NUM_UCLK_DPM_LEVELS 4 31 #define NUM_FCLK_DPM_LEVELS 4 32 #define NUM_XGMI_DPM_LEVELS 2 33 #define NUM_CXL_BITRATES 4 34 #define NUM_PCIE_BITRATES 4 35 #define NUM_XGMI_BITRATES 4 36 #define NUM_XGMI_WIDTHS 3 37 #define NUM_TDP_GROUPS 4 38 #define NUM_SOC_P2S_TABLES 6 39 #define NUM_GFX_P2S_TABLES 8 40 #define NUM_PSM_DIDT_THRESHOLDS 3 41 #define NUM_XVMIN_VMIN_THRESHOLDS 3 42 43 #define PRODUCT_MODEL_NUMBER_LEN 20 44 #define PRODUCT_NAME_LEN 64 45 #define PRODUCT_SERIAL_LEN 20 46 #define PRODUCT_MANUFACTURER_NAME_LEN 32 47 #define PRODUCT_FRU_ID_LEN 32 48 49 typedef enum { 50 /*0*/ FEATURE_DATA_CALCULATION = 0, 51 /*1*/ FEATURE_DPM_FCLK = 1, 52 /*2*/ FEATURE_DPM_GFXCLK = 2, 53 /*3*/ FEATURE_DPM_LCLK = 3, 54 /*4*/ FEATURE_DPM_SOCCLK = 4, 55 /*5*/ FEATURE_DPM_UCLK = 5, 56 /*6*/ FEATURE_DPM_VCN = 6, 57 /*7*/ FEATURE_DPM_XGMI = 7, 58 /*8*/ FEATURE_DS_FCLK = 8, 59 /*9*/ FEATURE_DS_GFXCLK = 9, 60 /*10*/ FEATURE_DS_LCLK = 10, 61 /*11*/ FEATURE_DS_MP0CLK = 11, 62 /*12*/ FEATURE_DS_MP1CLK = 12, 63 /*13*/ FEATURE_DS_MPIOCLK = 13, 64 /*14*/ FEATURE_DS_SOCCLK = 14, 65 /*15*/ FEATURE_DS_VCN = 15, 66 /*16*/ FEATURE_APCC_DFLL = 16, 67 /*17*/ FEATURE_APCC_PLUS = 17, 68 /*18*/ FEATURE_PPT = 18, 69 /*19*/ FEATURE_TDC = 19, 70 /*20*/ FEATURE_THERMAL = 20, 71 /*21*/ FEATURE_SOC_PCC = 21, 72 /*22*/ FEATURE_PROCHOT = 22, 73 /*23*/ FEATURE_FDD_AID_HBM = 23, 74 /*24*/ FEATURE_FDD_AID_SOC = 24, 75 /*25*/ FEATURE_FDD_XCD_EDC = 25, 76 /*26*/ FEATURE_FDD_XCD_XVMIN = 26, 77 /*27*/ FEATURE_FW_CTF = 27, 78 /*28*/ FEATURE_SMU_CG = 28, 79 /*29*/ FEATURE_PSI7 = 29, 80 /*30*/ FEATURE_XGMI_PER_LINK_PWR_DOWN = 30, 81 /*31*/ FEATURE_SOC_DC_RTC = 31, 82 /*32*/ FEATURE_GFX_DC_RTC = 32, 83 /*33*/ FEATURE_DVM_MIN_PSM = 33, 84 /*34*/ FEATURE_PRC = 34, 85 /*35*/ FEATURE_PSM_SQ_THROTTLER = 35, 86 /*36*/ FEATURE_PIT = 36, 87 /*37*/ FEATURE_DVO = 37, 88 /*38*/ FEATURE_XVMINORPSM_CLKSTOP_DS = 38, 89 /*39*/ FEATURE_GLOBAL_DPM = 39, 90 /*40*/ FEATURE_NODE_POWER_MANAGER = 40, 91 92 /*41*/ NUM_FEATURES = 41 93 } FEATURE_LIST_e; 94 95 //enum for MPIO PCIe gen speed msgs 96 typedef enum { 97 PCIE_LINK_SPEED_INDEX_TABLE_RESERVED, 98 PCIE_LINK_SPEED_INDEX_TABLE_GEN1, 99 PCIE_LINK_SPEED_INDEX_TABLE_GEN2, 100 PCIE_LINK_SPEED_INDEX_TABLE_GEN3, 101 PCIE_LINK_SPEED_INDEX_TABLE_GEN4, 102 PCIE_LINK_SPEED_INDEX_TABLE_GEN5, 103 PCIE_LINK_SPEED_INDEX_TABLE_COUNT 104 } PCIE_LINK_SPEED_INDEX_TABLE_e; 105 106 typedef enum { 107 GFX_GUARDBAND_OFFSET_0, 108 GFX_GUARDBAND_OFFSET_1, 109 GFX_GUARDBAND_OFFSET_2, 110 GFX_GUARDBAND_OFFSET_3, 111 GFX_GUARDBAND_OFFSET_4, 112 GFX_GUARDBAND_OFFSET_5, 113 GFX_GUARDBAND_OFFSET_6, 114 GFX_GUARDBAND_OFFSET_7, 115 GFX_GUARDBAND_OFFSET_COUNT 116 } GFX_GUARDBAND_OFFSET_e; 117 118 typedef enum { 119 GFX_DVM_MARGINHI_0, 120 GFX_DVM_MARGINHI_1, 121 GFX_DVM_MARGINHI_2, 122 GFX_DVM_MARGINHI_3, 123 GFX_DVM_MARGINHI_4, 124 GFX_DVM_MARGINHI_5, 125 GFX_DVM_MARGINHI_6, 126 GFX_DVM_MARGINHI_7, 127 GFX_DVM_MARGINLO_0, 128 GFX_DVM_MARGINLO_1, 129 GFX_DVM_MARGINLO_2, 130 GFX_DVM_MARGINLO_3, 131 GFX_DVM_MARGINLO_4, 132 GFX_DVM_MARGINLO_5, 133 GFX_DVM_MARGINLO_6, 134 GFX_DVM_MARGINLO_7, 135 GFX_DVM_MARGIN_COUNT 136 } GFX_DVM_MARGIN_e; 137 138 #define SMU_METRICS_TABLE_VERSION 0x13 139 140 typedef struct __attribute__((packed, aligned(4))) { 141 uint64_t AccumulationCounter; 142 143 //TEMPERATURE 144 uint32_t MaxSocketTemperature; 145 uint32_t MaxVrTemperature; 146 uint32_t MaxHbmTemperature; 147 uint64_t MaxSocketTemperatureAcc; 148 uint64_t MaxVrTemperatureAcc; 149 uint64_t MaxHbmTemperatureAcc; 150 151 //POWER 152 uint32_t SocketPowerLimit; 153 uint32_t SocketPower; 154 155 //ENERGY 156 uint64_t Timestamp; 157 uint64_t SocketEnergyAcc; 158 uint64_t XcdEnergyAcc; 159 uint64_t AidEnergyAcc; 160 uint64_t HbmEnergyAcc; 161 162 //FREQUENCY 163 uint32_t GfxclkFrequencyLimit; 164 uint32_t FclkFrequency; 165 uint32_t UclkFrequency; 166 uint32_t SocclkFrequency[4]; 167 uint32_t VclkFrequency[4]; 168 uint32_t DclkFrequency[4]; 169 uint32_t LclkFrequency[4]; 170 uint64_t GfxclkFrequencyAcc[8]; 171 172 //FREQUENCY RANGE 173 uint32_t MaxLclkDpmRange; 174 uint32_t MinLclkDpmRange; 175 176 //XGMI 177 uint32_t XgmiWidth; 178 uint32_t XgmiBitrate; 179 uint64_t XgmiReadBandwidthAcc[8]; 180 uint64_t XgmiWriteBandwidthAcc[8]; 181 182 //ACTIVITY 183 uint32_t SocketGfxBusy; 184 uint32_t DramBandwidthUtilization; 185 uint64_t SocketGfxBusyAcc; 186 uint64_t DramBandwidthAcc; 187 uint32_t MaxDramBandwidth; 188 uint64_t DramBandwidthUtilizationAcc; 189 uint64_t PcieBandwidthAcc[4]; 190 191 //THROTTLERS 192 uint32_t ProchotResidencyAcc; 193 uint32_t PptResidencyAcc; 194 uint32_t SocketThmResidencyAcc; 195 uint32_t VrThmResidencyAcc; 196 uint32_t HbmThmResidencyAcc; 197 uint32_t GfxLockXCDMak; 198 199 // New Items at end to maintain driver compatibility 200 uint32_t GfxclkFrequency[8]; 201 202 //XGMI Data tranfser size 203 uint64_t XgmiReadDataSizeAcc[8];//in KByte 204 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 205 206 //PCIE BW Data and error count 207 uint32_t PcieBandwidth[4]; 208 uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated 209 uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated 210 uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated 211 uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated 212 uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated 213 214 // VCN/JPEG ACTIVITY 215 uint32_t VcnBusy[4]; 216 uint32_t JpegBusy[40]; 217 218 // PCIE LINK Speed and width 219 uint32_t PCIeLinkSpeed; 220 uint32_t PCIeLinkWidth; 221 222 // PER XCD ACTIVITY 223 uint32_t GfxBusy[8]; 224 uint64_t GfxBusyAcc[8]; 225 226 //PCIE BW Data and error count 227 uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated 228 229 //Total App Clock Counter 230 uint64_t GfxclkBelowHostLimitPptAcc[8]; 231 uint64_t GfxclkBelowHostLimitThmAcc[8]; 232 uint64_t GfxclkBelowHostLimitTotalAcc[8]; 233 uint64_t GfxclkLowUtilizationAcc[8]; 234 } MetricsTable_t; 235 236 #define SMU_VF_METRICS_TABLE_MASK (1 << 31) 237 #define SMU_VF_METRICS_TABLE_VERSION (0x6 | SMU_VF_METRICS_TABLE_MASK) 238 239 typedef struct __attribute__((packed, aligned(4))) { 240 uint32_t AccumulationCounter; 241 uint32_t InstGfxclk_TargFreq; 242 uint64_t AccGfxclk_TargFreq; 243 uint64_t AccGfxRsmuDpm_Busy; 244 uint64_t AccGfxclkBelowHostLimitPpt; 245 uint64_t AccGfxclkBelowHostLimitThm; 246 uint64_t AccGfxclkBelowHostLimitTotal; 247 uint64_t AccGfxclkLowUtilization; 248 } VfMetricsTable_t; 249 250 /* FRU product information */ 251 typedef struct __attribute__((packed, aligned(4))) { 252 uint8_t ModelNumber[PRODUCT_MODEL_NUMBER_LEN]; 253 uint8_t Name[PRODUCT_NAME_LEN]; 254 uint8_t Serial[PRODUCT_SERIAL_LEN]; 255 uint8_t ManufacturerName[PRODUCT_MANUFACTURER_NAME_LEN]; 256 uint8_t FruId[PRODUCT_FRU_ID_LEN]; 257 } FRUProductInfo_t; 258 259 #pragma pack(push, 4) 260 typedef struct { 261 //FRU PRODUCT INFO 262 FRUProductInfo_t ProductInfo; 263 264 //POWER 265 uint32_t MaxSocketPowerLimit; 266 267 //FREQUENCY RANGE 268 uint32_t MaxGfxclkFrequency; 269 uint32_t MinGfxclkFrequency; 270 uint32_t FclkFrequencyTable[4]; 271 uint32_t UclkFrequencyTable[4]; 272 uint32_t SocclkFrequencyTable[4]; 273 uint32_t VclkFrequencyTable[4]; 274 uint32_t DclkFrequencyTable[4]; 275 uint32_t LclkFrequencyTable[4]; 276 277 //PSNs 278 uint64_t PublicSerialNumber_AID[4]; 279 uint64_t PublicSerialNumber_XCD[8]; 280 281 //XGMI 282 uint32_t MaxXgmiWidth; 283 uint32_t MaxXgmiBitrate; 284 285 // Telemetry 286 uint32_t InputTelemetryVoltageInmV; 287 288 // General info 289 uint32_t pldmVersion[2]; 290 } StaticMetricsTable_t; 291 #pragma pack(pop) 292 293 #endif 294