1 #ifndef _ASMX86_PAGE_H_ 2 #define _ASMX86_PAGE_H_ 3 /* 4 * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 9 10 #include <linux/const.h> 11 #include <bitops.h> 12 13 typedef unsigned long pteval_t; 14 typedef unsigned long pgd_t; 15 16 #include <asm-generic/page.h> 17 18 #ifndef __ASSEMBLER__ 19 20 #define PAGE_ALIGN(addr) ALIGN(addr, PAGE_SIZE) 21 22 #ifdef __x86_64__ 23 #define LARGE_PAGE_SIZE (512 * PAGE_SIZE) 24 #else 25 #define LARGE_PAGE_SIZE (1024 * PAGE_SIZE) 26 #endif 27 28 #ifdef CONFIG_EFI 29 /* lib/x86/amd_sev.c */ 30 extern unsigned long long get_amd_sev_c_bit_mask(void); 31 extern unsigned long long get_amd_sev_addr_upperbound(void); 32 #endif /* CONFIG_EFI */ 33 34 #define PT_PRESENT_MASK (1ull << 0) 35 #define PT_WRITABLE_MASK (1ull << 1) 36 #define PT_USER_MASK (1ull << 2) 37 #define PT_ACCESSED_MASK (1ull << 5) 38 #define PT_DIRTY_MASK (1ull << 6) 39 #define PT_PAGE_SIZE_MASK (1ull << 7) 40 #define PT_GLOBAL_MASK (1ull << 8) 41 #define PT64_NX_MASK (1ull << 63) 42 43 /* 44 * Without AMD SEV, the default address upper bound is 51 (i.e., pte bit 51 and 45 * lower bits are addresses). But with AMD SEV enabled, the upper bound is one 46 * bit lower than the c-bit position. 47 */ 48 #define PT_ADDR_UPPER_BOUND_DEFAULT (51) 49 50 #ifdef CONFIG_EFI 51 #define PT_ADDR_UPPER_BOUND (get_amd_sev_addr_upperbound()) 52 #else 53 #define PT_ADDR_UPPER_BOUND (PT_ADDR_UPPER_BOUND_DEFAULT) 54 #endif /* CONFIG_EFI */ 55 56 #define PT_ADDR_LOWER_BOUND (PAGE_SHIFT) 57 #define PT_ADDR_MASK GENMASK_ULL(PT_ADDR_UPPER_BOUND, PT_ADDR_LOWER_BOUND) 58 59 #define PDPTE64_PAGE_SIZE_MASK (1ull << 7) 60 #define PDPTE64_RSVD_MASK GENMASK_ULL(PT_ADDR_UPPER_BOUND, cpuid_maxphyaddr()) 61 62 #define PT_AD_MASK (PT_ACCESSED_MASK | PT_DIRTY_MASK) 63 64 #define PAE_PDPTE_RSVD_MASK (GENMASK_ULL(63, cpuid_maxphyaddr()) | \ 65 GENMASK_ULL(8, 5) | GENMASK_ULL(2, 1)) 66 67 68 #ifdef __x86_64__ 69 #define PAGE_LEVEL 4 70 #define PDPT_LEVEL 3 71 #define PGDIR_WIDTH 9 72 #define PGDIR_MASK 511 73 #else 74 #define PAGE_LEVEL 2 75 #define PGDIR_WIDTH 10 76 #define PGDIR_MASK 1023 77 #endif 78 79 #define PGDIR_BITS(lvl) (((lvl) - 1) * PGDIR_WIDTH + PAGE_SHIFT) 80 #define PGDIR_OFFSET(va, lvl) (((va) >> PGDIR_BITS(lvl)) & PGDIR_MASK) 81 82 #endif /* !__ASSEMBLER__ */ 83 #endif 84