1 #ifndef MMU_HASH64_H
2 #define MMU_HASH64_H
3
4 #include "exec/tswap.h"
5
6 #ifndef CONFIG_USER_ONLY
7
8 #ifdef TARGET_PPC64
9 void dump_slb(PowerPCCPU *cpu);
10 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
11 target_ulong esid, target_ulong vsid);
12 bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
13 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
14 bool guest_visible);
15 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
16 target_ulong pte_index,
17 target_ulong pte0, target_ulong pte1);
18 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
19 uint64_t pte0, uint64_t pte1);
20 void ppc_hash64_init(PowerPCCPU *cpu);
21 void ppc_hash64_finalize(PowerPCCPU *cpu);
22 #endif
23
24 /*
25 * SLB definitions
26 */
27
28 /* Bits in the SLB ESID word */
29 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
30 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
31
32 /* Bits in the SLB VSID word */
33 #define SLB_VSID_SHIFT 12
34 #define SLB_VSID_SHIFT_1T 24
35 #define SLB_VSID_SSIZE_SHIFT 62
36 #define SLB_VSID_B 0xc000000000000000ULL
37 #define SLB_VSID_B_256M 0x0000000000000000ULL
38 #define SLB_VSID_B_1T 0x4000000000000000ULL
39 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
40 #define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
41 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
42 #define SLB_VSID_KS 0x0000000000000800ULL
43 #define SLB_VSID_KP 0x0000000000000400ULL
44 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
45 #define SLB_VSID_L 0x0000000000000100ULL
46 #define SLB_VSID_L_SHIFT PPC_BIT_NR(55)
47 #define SLB_VSID_C 0x0000000000000080ULL /* class */
48 #define SLB_VSID_LP 0x0000000000000030ULL
49 #define SLB_VSID_LP_SHIFT PPC_BIT_NR(59)
50 #define SLB_VSID_ATTR 0x0000000000000FFFULL
51 #define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
52 #define SLB_VSID_4K 0x0000000000000000ULL
53 #define SLB_VSID_64K 0x0000000000000110ULL
54 #define SLB_VSID_16M 0x0000000000000100ULL
55 #define SLB_VSID_16G 0x0000000000000120ULL
56
57 /*
58 * Hash page table definitions
59 */
60
61 #define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
62 #define SDR_64_HTABSIZE 0x000000000000001FULL
63
64 #define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
65 #define PATE0_PS PPC_BITMASK(56, 58)
66 #define PATE0_GET_PS(dw0) (((dw0) & PATE0_PS) >> PPC_BIT_NR(58))
67
68 #define HPTES_PER_GROUP 8
69 #define HASH_PTE_SIZE_64 16
70 #define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
71
72 #define HPTE64_V_SSIZE SLB_VSID_B
73 #define HPTE64_V_SSIZE_256M SLB_VSID_B_256M
74 #define HPTE64_V_SSIZE_1T SLB_VSID_B_1T
75 #define HPTE64_V_SSIZE_SHIFT 62
76 #define HPTE64_V_AVPN_SHIFT 7
77 #define HPTE64_V_AVPN 0x3fffffffffffff80ULL
78 #define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
79 #define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
80 #define HPTE64_V_BOLTED 0x0000000000000010ULL
81 #define HPTE64_V_LARGE 0x0000000000000004ULL
82 #define HPTE64_V_SECONDARY 0x0000000000000002ULL
83 #define HPTE64_V_VALID 0x0000000000000001ULL
84
85 #define HPTE64_R_PP0 0x8000000000000000ULL
86 #define HPTE64_R_TS 0x4000000000000000ULL
87 #define HPTE64_R_KEY_HI 0x3000000000000000ULL
88 #define HPTE64_R_RPN_SHIFT 12
89 #define HPTE64_R_RPN 0x0ffffffffffff000ULL
90 #define HPTE64_R_FLAGS 0x00000000000003ffULL
91 #define HPTE64_R_PP 0x0000000000000003ULL
92 #define HPTE64_R_N 0x0000000000000004ULL
93 #define HPTE64_R_G 0x0000000000000008ULL
94 #define HPTE64_R_M 0x0000000000000010ULL
95 #define HPTE64_R_I 0x0000000000000020ULL
96 #define HPTE64_R_W 0x0000000000000040ULL
97 #define HPTE64_R_WIMG 0x0000000000000078ULL
98 #define HPTE64_R_C 0x0000000000000080ULL
99 #define HPTE64_R_R 0x0000000000000100ULL
100 #define HPTE64_R_KEY_LO 0x0000000000000e00ULL
101 #define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \
102 (((x) & HPTE64_R_KEY_LO) >> 9))
103
104 #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
105 #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
106
107 /* PTE offsets */
108 #define HPTE64_DW1 (HASH_PTE_SIZE_64 / 2)
109 #define HPTE64_DW1_R (HPTE64_DW1 + 6)
110 #define HPTE64_DW1_C (HPTE64_DW1 + 7)
111
112 /* Format changes for ARCH v3 */
113 #define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
114 #define HPTE64_R_3_0_SSIZE_SHIFT 58
115 #define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
116
117 struct ppc_hash_pte64 {
118 uint64_t pte0, pte1;
119 };
120
121 const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
122 hwaddr ptex, int n);
123 void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
124 hwaddr ptex, int n);
125 bool ppc_hash64_valid_ptex(PowerPCCPU *cpu, target_ulong ptex);
126
ppc_hash64_hpte0(PowerPCCPU * cpu,const ppc_hash_pte64_t * hptes,int i)127 static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
128 const ppc_hash_pte64_t *hptes, int i)
129 {
130 return ldq_p(&(hptes[i].pte0));
131 }
132
ppc_hash64_hpte1(PowerPCCPU * cpu,const ppc_hash_pte64_t * hptes,int i)133 static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
134 const ppc_hash_pte64_t *hptes, int i)
135 {
136 return ldq_p(&(hptes[i].pte1));
137 }
138
139 /*
140 * MMU Options
141 */
142
143 struct PPCHash64PageSize {
144 uint32_t page_shift; /* Page shift (or 0) */
145 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
146 };
147 typedef struct PPCHash64PageSize PPCHash64PageSize;
148
149 struct PPCHash64SegmentPageSizes {
150 uint32_t page_shift; /* Base page shift of segment (or 0) */
151 uint32_t slb_enc; /* SLB encoding for BookS */
152 PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
153 };
154
155 struct PPCHash64Options {
156 #define PPC_HASH64_1TSEG 0x00001
157 #define PPC_HASH64_AMR 0x00002
158 #define PPC_HASH64_CI_LARGEPAGE 0x00004
159 unsigned flags;
160 unsigned slb_size;
161 PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
162 };
163
164 extern const PPCHash64Options ppc_hash64_opts_basic;
165 extern const PPCHash64Options ppc_hash64_opts_POWER7;
166
ppc_hash64_has(PowerPCCPU * cpu,unsigned feature)167 static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
168 {
169 return !!(cpu->hash64_opts->flags & feature);
170 }
171
172 #endif /* CONFIG_USER_ONLY */
173
174 #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
ppc_hash64_init(PowerPCCPU * cpu)175 static inline void ppc_hash64_init(PowerPCCPU *cpu)
176 {
177 }
ppc_hash64_finalize(PowerPCCPU * cpu)178 static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
179 {
180 }
181 #endif
182
183 #endif /* MMU_HASH64_H */
184