xref: /linux/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h (revision 4cff5c05e076d2ee4e34122aa956b84a2eaac587)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
3 #define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
4 
5 /*
6  * TLB flushing for 64-bit hash-MMU CPUs
7  */
8 
9 #include <linux/percpu.h>
10 #include <asm/page.h>
11 
12 #define PPC64_TLB_BATCH_NR 192
13 
14 struct ppc64_tlb_batch {
15 	unsigned long		index;
16 	struct mm_struct	*mm;
17 	real_pte_t		pte[PPC64_TLB_BATCH_NR];
18 	unsigned long		vpn[PPC64_TLB_BATCH_NR];
19 	unsigned int		psize;
20 	int			ssize;
21 };
22 DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
23 
24 extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
25 
arch_enter_lazy_mmu_mode(void)26 static inline void arch_enter_lazy_mmu_mode(void)
27 {
28 	if (radix_enabled())
29 		return;
30 	/*
31 	 * apply_to_page_range can call us this preempt enabled when
32 	 * operating on kernel page tables.
33 	 */
34 	preempt_disable();
35 }
36 
arch_flush_lazy_mmu_mode(void)37 static inline void arch_flush_lazy_mmu_mode(void)
38 {
39 	struct ppc64_tlb_batch *batch;
40 
41 	if (radix_enabled())
42 		return;
43 	batch = this_cpu_ptr(&ppc64_tlb_batch);
44 
45 	if (batch->index)
46 		__flush_tlb_pending(batch);
47 }
48 
arch_leave_lazy_mmu_mode(void)49 static inline void arch_leave_lazy_mmu_mode(void)
50 {
51 	if (radix_enabled())
52 		return;
53 
54 	arch_flush_lazy_mmu_mode();
55 	preempt_enable();
56 }
57 
58 extern void hash__tlbiel_all(unsigned int action);
59 
60 extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
61 			    int ssize, unsigned long flags);
62 extern void flush_hash_range(unsigned long number, int local);
63 extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
64 				pmd_t *pmdp, unsigned int psize, int ssize,
65 				unsigned long flags);
66 
67 struct mmu_gather;
68 extern void hash__tlb_flush(struct mmu_gather *tlb);
69 
70 #ifdef CONFIG_PPC_64S_HASH_MMU
71 /* Private function for use by PCI IO mapping code */
72 extern void __flush_hash_table_range(unsigned long start, unsigned long end);
73 void flush_hash_table_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr);
74 #else
__flush_hash_table_range(unsigned long start,unsigned long end)75 static inline void __flush_hash_table_range(unsigned long start, unsigned long end) { }
76 #endif
77 #endif /*  _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */
78