xref: /linux/include/linux/mfd/88pm886.h (revision 3422b4bc606eee2ba7758ea9347c83332eeec3e3)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef __MFD_88PM886_H
3 #define __MFD_88PM886_H
4 
5 #include <linux/i2c.h>
6 #include <linux/regmap.h>
7 
8 #define PM886_A1_CHIP_ID		0xa1
9 
10 #define PM886_IRQ_ONKEY			0
11 
12 #define PM886_PAGE_OFFSET_REGULATORS	1
13 #define PM886_PAGE_OFFSET_GPADC		2
14 
15 #define PM886_REG_ID			0x00
16 
17 #define PM886_REG_STATUS1		0x01
18 #define PM886_ONKEY_STS1		BIT(0)
19 
20 #define PM886_REG_INT_STATUS1		0x05
21 
22 #define PM886_REG_INT_ENA_1		0x0a
23 #define PM886_INT_ENA1_ONKEY		BIT(0)
24 
25 #define PM886_REG_MISC_CONFIG1		0x14
26 #define PM886_SW_PDOWN			BIT(5)
27 
28 #define PM886_REG_MISC_CONFIG2		0x15
29 #define PM886_INT_INV			BIT(0)
30 #define PM886_INT_CLEAR			BIT(1)
31 #define PM886_INT_RC			0x00
32 #define PM886_INT_WC			BIT(1)
33 #define PM886_INT_MASK_MODE		BIT(2)
34 
35 #define PM886_REG_RTC_CNT1		0xd1
36 #define PM886_REG_RTC_CNT2		0xd2
37 #define PM886_REG_RTC_CNT3		0xd3
38 #define PM886_REG_RTC_CNT4		0xd4
39 #define PM886_REG_RTC_SPARE1		0xea
40 #define PM886_REG_RTC_SPARE2		0xeb
41 #define PM886_REG_RTC_SPARE3		0xec
42 #define PM886_REG_RTC_SPARE4		0xed
43 #define PM886_REG_RTC_SPARE5		0xee
44 #define PM886_REG_RTC_SPARE6		0xef
45 
46 #define PM886_REG_BUCK_EN		0x08
47 #define PM886_REG_LDO_EN1		0x09
48 #define PM886_REG_LDO_EN2		0x0a
49 #define PM886_REG_LDO1_VOUT		0x20
50 #define PM886_REG_LDO2_VOUT		0x26
51 #define PM886_REG_LDO3_VOUT		0x2c
52 #define PM886_REG_LDO4_VOUT		0x32
53 #define PM886_REG_LDO5_VOUT		0x38
54 #define PM886_REG_LDO6_VOUT		0x3e
55 #define PM886_REG_LDO7_VOUT		0x44
56 #define PM886_REG_LDO8_VOUT		0x4a
57 #define PM886_REG_LDO9_VOUT		0x50
58 #define PM886_REG_LDO10_VOUT		0x56
59 #define PM886_REG_LDO11_VOUT		0x5c
60 #define PM886_REG_LDO12_VOUT		0x62
61 #define PM886_REG_LDO13_VOUT		0x68
62 #define PM886_REG_LDO14_VOUT		0x6e
63 #define PM886_REG_LDO15_VOUT		0x74
64 #define PM886_REG_LDO16_VOUT		0x7a
65 #define PM886_REG_BUCK1_VOUT		0xa5
66 #define PM886_REG_BUCK2_VOUT		0xb3
67 #define PM886_REG_BUCK3_VOUT		0xc1
68 #define PM886_REG_BUCK4_VOUT		0xcf
69 #define PM886_REG_BUCK5_VOUT		0xdd
70 
71 #define PM886_LDO_VSEL_MASK		0x0f
72 #define PM886_BUCK_VSEL_MASK		0x7f
73 
74 /* GPADC enable/disable registers */
75 #define PM886_REG_GPADC_CONFIG(n)	(n)
76 
77 #define PM886_GPADC_VSC_EN		BIT(0)
78 #define PM886_GPADC_VBAT_EN		BIT(1)
79 #define PM886_GPADC_GNDDET1_EN		BIT(3)
80 #define PM886_GPADC_VBUS_EN		BIT(4)
81 #define PM886_GPADC_VCHG_PWR_EN		BIT(5)
82 #define PM886_GPADC_VCF_OUT_EN		BIT(6)
83 #define PM886_GPADC_CONFIG1_EN_ALL	\
84 	(PM886_GPADC_VSC_EN |		\
85 	 PM886_GPADC_VBAT_EN |		\
86 	 PM886_GPADC_GNDDET1_EN |	\
87 	 PM886_GPADC_VBUS_EN |		\
88 	 PM886_GPADC_VCHG_PWR_EN |	\
89 	 PM886_GPADC_VCF_OUT_EN)
90 
91 #define PM886_GPADC_TINT_EN		BIT(0)
92 #define PM886_GPADC_PMODE_EN		BIT(1)
93 #define PM886_GPADC_GPADC0_EN		BIT(2)
94 #define PM886_GPADC_GPADC1_EN		BIT(3)
95 #define PM886_GPADC_GPADC2_EN		BIT(4)
96 #define PM886_GPADC_GPADC3_EN		BIT(5)
97 #define PM886_GPADC_MIC_DET_EN		BIT(6)
98 #define PM886_GPADC_CONFIG2_EN_ALL	\
99 	(PM886_GPADC_TINT_EN |		\
100 	 PM886_GPADC_GPADC0_EN |	\
101 	 PM886_GPADC_GPADC1_EN |	\
102 	 PM886_GPADC_GPADC2_EN |	\
103 	 PM886_GPADC_GPADC3_EN |	\
104 	 PM886_GPADC_MIC_DET_EN)
105 
106 /* No CONFIG3_EN_ALL because this is the only bit there. */
107 #define PM886_GPADC_GND_DET2_EN		BIT(0)
108 
109 /* GPADC channel registers */
110 #define PM886_REG_GPADC_VSC		0x40
111 #define PM886_REG_GPADC_VCHG_PWR	0x4c
112 #define PM886_REG_GPADC_VCF_OUT		0x4e
113 #define PM886_REG_GPADC_TINT		0x50
114 #define PM886_REG_GPADC_GPADC0		0x54
115 #define PM886_REG_GPADC_GPADC1		0x56
116 #define PM886_REG_GPADC_GPADC2		0x58
117 #define PM886_REG_GPADC_VBAT		0xa0
118 #define PM886_REG_GPADC_GND_DET1	0xa4
119 #define PM886_REG_GPADC_GND_DET2	0xa6
120 #define PM886_REG_GPADC_VBUS		0xa8
121 #define PM886_REG_GPADC_GPADC3		0xaa
122 #define PM886_REG_GPADC_MIC_DET		0xac
123 #define PM886_REG_GPADC_VBAT_SLP	0xb0
124 
125 /* VBAT_SLP is the last register and is 2 bytes wide like other channels. */
126 #define PM886_GPADC_MAX_REGISTER	(PM886_REG_GPADC_VBAT_SLP + 1)
127 
128 #define PM886_GPADC_BIAS_LEVELS		16
129 #define PM886_GPADC_INDEX_TO_BIAS_uA(i)	(1 + (i) * 5)
130 
131 struct pm886_chip {
132 	struct i2c_client *client;
133 	unsigned int chip_id;
134 	struct regmap *regmap;
135 };
136 #endif /* __MFD_88PM886_H */
137