1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Framework and drivers for configuring and reading different PHYs 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10 11 #ifndef __PHY_H 12 #define __PHY_H 13 14 #include <linux/compiler.h> 15 #include <linux/spinlock.h> 16 #include <linux/ethtool.h> 17 #include <linux/leds.h> 18 #include <linux/linkmode.h> 19 #include <linux/netlink.h> 20 #include <linux/mdio.h> 21 #include <linux/mii.h> 22 #include <linux/mii_timestamper.h> 23 #include <linux/module.h> 24 #include <linux/timer.h> 25 #include <linux/workqueue.h> 26 #include <linux/mod_devicetable.h> 27 #include <linux/u64_stats_sync.h> 28 #include <linux/irqreturn.h> 29 #include <linux/iopoll.h> 30 #include <linux/refcount.h> 31 32 #include <linux/atomic.h> 33 #include <net/eee.h> 34 35 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init; 36 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init; 37 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init; 38 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init; 39 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init; 40 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init; 41 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init; 42 extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init; 43 44 #define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features) 45 #define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features) 46 #define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features) 47 #define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features) 48 #define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features) 49 #define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features) 50 #define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features) 51 #define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features) 52 53 extern const int phy_basic_ports_array[3]; 54 55 /* 56 * Set phydev->irq to PHY_POLL if interrupts are not supported, 57 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if 58 * the attached MAC driver handles the interrupt 59 */ 60 #define PHY_POLL -1 61 #define PHY_MAC_INTERRUPT -2 62 63 #define PHY_IS_INTERNAL 0x00000001 64 #define PHY_RST_AFTER_CLK_EN 0x00000002 65 #define PHY_POLL_CABLE_TEST 0x00000004 66 #define PHY_ALWAYS_CALL_SUSPEND 0x00000008 67 #define MDIO_DEVICE_IS_PHY 0x80000000 68 69 /** 70 * enum phy_interface_t - Interface Mode definitions 71 * 72 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch 73 * @PHY_INTERFACE_MODE_INTERNAL: No interface, MAC and PHY combined 74 * @PHY_INTERFACE_MODE_MII: Media-independent interface 75 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface 76 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface 77 * @PHY_INTERFACE_MODE_TBI: Ten Bit Interface 78 * @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface 79 * @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface 80 * @PHY_INTERFACE_MODE_REVRMII: Reduced Media Independent Interface in PHY role 81 * @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface 82 * @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay 83 * @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay 84 * @PHY_INTERFACE_MODE_RGMII_TXID: RGMII with Internal TX delay 85 * @PHY_INTERFACE_MODE_RTBI: Reduced TBI 86 * @PHY_INTERFACE_MODE_SMII: Serial MII 87 * @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface 88 * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface 89 * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax 90 * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII 91 * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII 92 * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII 93 * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX 94 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX 95 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX 96 * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR 97 * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI 98 * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface 99 * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR 100 * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR 101 * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII 102 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN 103 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII 104 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN 105 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII 106 * @PHY_INTERFACE_MODE_50GBASER: 50GBase-R - with Clause 134 FEC 107 * @PHY_INTERFACE_MODE_LAUI: 50 Gigabit Attachment Unit Interface 108 * @PHY_INTERFACE_MODE_100GBASEP: 100GBase-P - with Clause 134 FEC 109 * @PHY_INTERFACE_MODE_MIILITE: MII-Lite - MII without RXER TXER CRS COL 110 * @PHY_INTERFACE_MODE_MAX: Book keeping 111 * 112 * Describes the interface between the MAC and PHY. 113 */ 114 typedef enum { 115 PHY_INTERFACE_MODE_NA, 116 PHY_INTERFACE_MODE_INTERNAL, 117 PHY_INTERFACE_MODE_MII, 118 PHY_INTERFACE_MODE_GMII, 119 PHY_INTERFACE_MODE_SGMII, 120 PHY_INTERFACE_MODE_TBI, 121 PHY_INTERFACE_MODE_REVMII, 122 PHY_INTERFACE_MODE_RMII, 123 PHY_INTERFACE_MODE_REVRMII, 124 PHY_INTERFACE_MODE_RGMII, 125 PHY_INTERFACE_MODE_RGMII_ID, 126 PHY_INTERFACE_MODE_RGMII_RXID, 127 PHY_INTERFACE_MODE_RGMII_TXID, 128 PHY_INTERFACE_MODE_RTBI, 129 PHY_INTERFACE_MODE_SMII, 130 PHY_INTERFACE_MODE_XGMII, 131 PHY_INTERFACE_MODE_XLGMII, 132 PHY_INTERFACE_MODE_MOCA, 133 PHY_INTERFACE_MODE_PSGMII, 134 PHY_INTERFACE_MODE_QSGMII, 135 PHY_INTERFACE_MODE_TRGMII, 136 PHY_INTERFACE_MODE_100BASEX, 137 PHY_INTERFACE_MODE_1000BASEX, 138 PHY_INTERFACE_MODE_2500BASEX, 139 PHY_INTERFACE_MODE_5GBASER, 140 PHY_INTERFACE_MODE_RXAUI, 141 PHY_INTERFACE_MODE_XAUI, 142 /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */ 143 PHY_INTERFACE_MODE_10GBASER, 144 PHY_INTERFACE_MODE_25GBASER, 145 PHY_INTERFACE_MODE_USXGMII, 146 /* 10GBASE-KR - with Clause 73 AN */ 147 PHY_INTERFACE_MODE_10GKR, 148 PHY_INTERFACE_MODE_QUSGMII, 149 PHY_INTERFACE_MODE_1000BASEKX, 150 PHY_INTERFACE_MODE_10G_QXGMII, 151 PHY_INTERFACE_MODE_50GBASER, 152 PHY_INTERFACE_MODE_LAUI, 153 PHY_INTERFACE_MODE_100GBASEP, 154 PHY_INTERFACE_MODE_MIILITE, 155 PHY_INTERFACE_MODE_MAX, 156 } phy_interface_t; 157 158 /* PHY interface mode bitmap handling */ 159 #define DECLARE_PHY_INTERFACE_MASK(name) \ 160 DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX) 161 162 static inline void phy_interface_zero(unsigned long *intf) 163 { 164 bitmap_zero(intf, PHY_INTERFACE_MODE_MAX); 165 } 166 167 static inline bool phy_interface_empty(const unsigned long *intf) 168 { 169 return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX); 170 } 171 172 static inline void phy_interface_copy(unsigned long *d, const unsigned long *s) 173 { 174 bitmap_copy(d, s, PHY_INTERFACE_MODE_MAX); 175 } 176 177 static inline unsigned int phy_interface_weight(const unsigned long *intf) 178 { 179 return bitmap_weight(intf, PHY_INTERFACE_MODE_MAX); 180 } 181 182 static inline void phy_interface_and(unsigned long *dst, const unsigned long *a, 183 const unsigned long *b) 184 { 185 bitmap_and(dst, a, b, PHY_INTERFACE_MODE_MAX); 186 } 187 188 static inline void phy_interface_or(unsigned long *dst, const unsigned long *a, 189 const unsigned long *b) 190 { 191 bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX); 192 } 193 194 static inline void phy_interface_set_rgmii(unsigned long *intf) 195 { 196 __set_bit(PHY_INTERFACE_MODE_RGMII, intf); 197 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf); 198 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf); 199 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf); 200 } 201 202 /** 203 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode 204 * @interface: enum phy_interface_t value 205 * 206 * Description: maps enum &phy_interface_t defined in this file 207 * into the device tree binding of 'phy-mode', so that Ethernet 208 * device driver can get PHY interface from device tree. 209 */ 210 static inline const char *phy_modes(phy_interface_t interface) 211 { 212 switch (interface) { 213 case PHY_INTERFACE_MODE_NA: 214 return ""; 215 case PHY_INTERFACE_MODE_INTERNAL: 216 return "internal"; 217 case PHY_INTERFACE_MODE_MII: 218 return "mii"; 219 case PHY_INTERFACE_MODE_GMII: 220 return "gmii"; 221 case PHY_INTERFACE_MODE_SGMII: 222 return "sgmii"; 223 case PHY_INTERFACE_MODE_TBI: 224 return "tbi"; 225 case PHY_INTERFACE_MODE_REVMII: 226 return "rev-mii"; 227 case PHY_INTERFACE_MODE_RMII: 228 return "rmii"; 229 case PHY_INTERFACE_MODE_REVRMII: 230 return "rev-rmii"; 231 case PHY_INTERFACE_MODE_RGMII: 232 return "rgmii"; 233 case PHY_INTERFACE_MODE_RGMII_ID: 234 return "rgmii-id"; 235 case PHY_INTERFACE_MODE_RGMII_RXID: 236 return "rgmii-rxid"; 237 case PHY_INTERFACE_MODE_RGMII_TXID: 238 return "rgmii-txid"; 239 case PHY_INTERFACE_MODE_RTBI: 240 return "rtbi"; 241 case PHY_INTERFACE_MODE_SMII: 242 return "smii"; 243 case PHY_INTERFACE_MODE_XGMII: 244 return "xgmii"; 245 case PHY_INTERFACE_MODE_XLGMII: 246 return "xlgmii"; 247 case PHY_INTERFACE_MODE_MOCA: 248 return "moca"; 249 case PHY_INTERFACE_MODE_PSGMII: 250 return "psgmii"; 251 case PHY_INTERFACE_MODE_QSGMII: 252 return "qsgmii"; 253 case PHY_INTERFACE_MODE_TRGMII: 254 return "trgmii"; 255 case PHY_INTERFACE_MODE_1000BASEX: 256 return "1000base-x"; 257 case PHY_INTERFACE_MODE_1000BASEKX: 258 return "1000base-kx"; 259 case PHY_INTERFACE_MODE_2500BASEX: 260 return "2500base-x"; 261 case PHY_INTERFACE_MODE_5GBASER: 262 return "5gbase-r"; 263 case PHY_INTERFACE_MODE_RXAUI: 264 return "rxaui"; 265 case PHY_INTERFACE_MODE_XAUI: 266 return "xaui"; 267 case PHY_INTERFACE_MODE_10GBASER: 268 return "10gbase-r"; 269 case PHY_INTERFACE_MODE_25GBASER: 270 return "25gbase-r"; 271 case PHY_INTERFACE_MODE_USXGMII: 272 return "usxgmii"; 273 case PHY_INTERFACE_MODE_10GKR: 274 return "10gbase-kr"; 275 case PHY_INTERFACE_MODE_100BASEX: 276 return "100base-x"; 277 case PHY_INTERFACE_MODE_QUSGMII: 278 return "qusgmii"; 279 case PHY_INTERFACE_MODE_10G_QXGMII: 280 return "10g-qxgmii"; 281 case PHY_INTERFACE_MODE_50GBASER: 282 return "50gbase-r"; 283 case PHY_INTERFACE_MODE_LAUI: 284 return "laui"; 285 case PHY_INTERFACE_MODE_100GBASEP: 286 return "100gbase-p"; 287 case PHY_INTERFACE_MODE_MIILITE: 288 return "mii-lite"; 289 default: 290 return "unknown"; 291 } 292 } 293 294 /** 295 * rgmii_clock - map link speed to the clock rate 296 * @speed: link speed value 297 * 298 * Description: maps RGMII supported link speeds into the clock rates. 299 * This can also be used for MII, GMII, and RMII interface modes as the 300 * clock rates are identical, but the caller must be aware that errors 301 * for unsupported clock rates will not be signalled. 302 * 303 * Returns: clock rate or negative errno 304 */ 305 static inline long rgmii_clock(int speed) 306 { 307 switch (speed) { 308 case SPEED_10: 309 return 2500000; 310 case SPEED_100: 311 return 25000000; 312 case SPEED_1000: 313 return 125000000; 314 default: 315 return -EINVAL; 316 } 317 } 318 319 #define PHY_MAX_ADDR 32 320 321 /* Used when trying to connect to a specific phy (mii bus id:phy device id) */ 322 #define PHY_ID_FMT "%s:%02x" 323 #define PHY_ID_SIZE (MII_BUS_ID_SIZE + 3) 324 325 #define MII_BUS_ID_SIZE 61 326 327 struct device; 328 struct kernel_hwtstamp_config; 329 struct phylink; 330 struct phy_port; 331 struct sfp_bus; 332 struct sfp_upstream_ops; 333 struct sk_buff; 334 335 /** 336 * struct mdio_bus_stats - Statistics counters for MDIO busses 337 * @transfers: Total number of transfers, i.e. @writes + @reads 338 * @errors: Number of MDIO transfers that returned an error 339 * @writes: Number of write transfers 340 * @reads: Number of read transfers 341 * @syncp: Synchronisation for incrementing statistics 342 */ 343 struct mdio_bus_stats { 344 u64_stats_t transfers; 345 u64_stats_t errors; 346 u64_stats_t writes; 347 u64_stats_t reads; 348 /* Must be last, add new statistics above */ 349 struct u64_stats_sync syncp; 350 }; 351 352 /** 353 * struct mii_bus - Represents an MDIO bus 354 * 355 * @owner: Who owns this device 356 * @name: User friendly name for this MDIO device, or driver name 357 * @id: Unique identifier for this bus, typical from bus hierarchy 358 * @priv: Driver private data 359 * 360 * The Bus class for PHYs. Devices which provide access to 361 * PHYs should register using this structure 362 */ 363 struct mii_bus { 364 struct module *owner; 365 const char *name; 366 char id[MII_BUS_ID_SIZE]; 367 void *priv; 368 /** @read: Perform a read transfer on the bus */ 369 int (*read)(struct mii_bus *bus, int addr, int regnum); 370 /** @write: Perform a write transfer on the bus */ 371 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val); 372 /** @read_c45: Perform a C45 read transfer on the bus */ 373 int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum); 374 /** @write_c45: Perform a C45 write transfer on the bus */ 375 int (*write_c45)(struct mii_bus *bus, int addr, int devnum, 376 int regnum, u16 val); 377 /** @reset: Perform a reset of the bus */ 378 int (*reset)(struct mii_bus *bus); 379 380 /** @stats: Statistic counters per device on the bus */ 381 struct mdio_bus_stats stats[PHY_MAX_ADDR]; 382 383 /** 384 * @mdio_lock: A lock to ensure that only one thing can read/write 385 * the MDIO bus at a time 386 */ 387 struct mutex mdio_lock; 388 389 /** @parent: Parent device of this bus */ 390 struct device *parent; 391 /** @state: State of bus structure */ 392 enum { 393 MDIOBUS_ALLOCATED = 1, 394 MDIOBUS_REGISTERED, 395 MDIOBUS_UNREGISTERED, 396 MDIOBUS_RELEASED, 397 } state; 398 399 /** @dev: Kernel device representation */ 400 struct device dev; 401 402 /** @mdio_map: list of all MDIO devices on bus */ 403 struct mdio_device *mdio_map[PHY_MAX_ADDR]; 404 405 /** @phy_mask: PHY addresses to be ignored when probing */ 406 u32 phy_mask; 407 408 /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */ 409 u32 phy_ignore_ta_mask; 410 411 /** 412 * @irq: An array of interrupts, each PHY's interrupt at the index 413 * matching its address 414 */ 415 int irq[PHY_MAX_ADDR]; 416 417 /** @reset_delay_us: GPIO reset pulse width in microseconds */ 418 int reset_delay_us; 419 /** @reset_post_delay_us: GPIO reset deassert delay in microseconds */ 420 int reset_post_delay_us; 421 /** @reset_gpiod: Reset GPIO descriptor pointer */ 422 struct gpio_desc *reset_gpiod; 423 424 /** @shared_lock: protect access to the shared element */ 425 struct mutex shared_lock; 426 427 #if IS_ENABLED(CONFIG_PHY_PACKAGE) 428 /** @shared: shared state across different PHYs */ 429 struct phy_package_shared *shared[PHY_MAX_ADDR]; 430 #endif 431 }; 432 #define to_mii_bus(d) container_of(d, struct mii_bus, dev) 433 434 struct mii_bus *mdiobus_alloc_size(size_t size); 435 436 /** 437 * mdiobus_alloc - Allocate an MDIO bus structure 438 * 439 * The internal state of the MDIO bus will be set of MDIOBUS_ALLOCATED ready 440 * for the driver to register the bus. 441 */ 442 static inline struct mii_bus *mdiobus_alloc(void) 443 { 444 return mdiobus_alloc_size(0); 445 } 446 447 int __mdiobus_register(struct mii_bus *bus, struct module *owner); 448 int __devm_mdiobus_register(struct device *dev, struct mii_bus *bus, 449 struct module *owner); 450 #define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE) 451 #define devm_mdiobus_register(dev, bus) \ 452 __devm_mdiobus_register(dev, bus, THIS_MODULE) 453 454 void mdiobus_unregister(struct mii_bus *bus); 455 void mdiobus_free(struct mii_bus *bus); 456 struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv); 457 static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev) 458 { 459 return devm_mdiobus_alloc_size(dev, 0); 460 } 461 462 struct mii_bus *mdio_find_bus(const char *mdio_name); 463 struct phy_device *mdiobus_scan_c22(struct mii_bus *bus, int addr); 464 465 #define PHY_INTERRUPT_DISABLED false 466 #define PHY_INTERRUPT_ENABLED true 467 468 /** 469 * enum phy_state - PHY state machine states: 470 * 471 * @PHY_DOWN: PHY device and driver are not ready for anything. probe 472 * should be called if and only if the PHY is in this state, 473 * given that the PHY device exists. 474 * - PHY driver probe function will set the state to @PHY_READY 475 * 476 * @PHY_READY: PHY is ready to send and receive packets, but the 477 * controller is not. By default, PHYs which do not implement 478 * probe will be set to this state by phy_probe(). 479 * - start will set the state to UP 480 * 481 * @PHY_UP: The PHY and attached device are ready to do work. 482 * Interrupts should be started here. 483 * - timer moves to @PHY_NOLINK or @PHY_RUNNING 484 * 485 * @PHY_NOLINK: PHY is up, but not currently plugged in. 486 * - irq or timer will set @PHY_RUNNING if link comes back 487 * - phy_stop moves to @PHY_HALTED 488 * 489 * @PHY_RUNNING: PHY is currently up, running, and possibly sending 490 * and/or receiving packets 491 * - irq or timer will set @PHY_NOLINK if link goes down 492 * - phy_stop moves to @PHY_HALTED 493 * 494 * @PHY_CABLETEST: PHY is performing a cable test. Packet reception/sending 495 * is not expected to work, carrier will be indicated as down. PHY will be 496 * poll once per second, or on interrupt for it current state. 497 * Once complete, move to UP to restart the PHY. 498 * - phy_stop aborts the running test and moves to @PHY_HALTED 499 * 500 * @PHY_HALTED: PHY is up, but no polling or interrupts are done. 501 * - phy_start moves to @PHY_UP 502 * 503 * @PHY_ERROR: PHY is up, but is in an error state. 504 * - phy_stop moves to @PHY_HALTED 505 */ 506 enum phy_state { 507 PHY_DOWN = 0, 508 PHY_READY, 509 PHY_HALTED, 510 PHY_ERROR, 511 PHY_UP, 512 PHY_RUNNING, 513 PHY_NOLINK, 514 PHY_CABLETEST, 515 }; 516 517 #define MDIO_MMD_NUM 32 518 519 /** 520 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers 521 * @devices_in_package: IEEE 802.3 devices in package register value. 522 * @mmds_present: bit vector of MMDs present. 523 * @device_ids: The device identifier for each present device. 524 */ 525 struct phy_c45_device_ids { 526 u32 devices_in_package; 527 u32 mmds_present; 528 u32 device_ids[MDIO_MMD_NUM]; 529 }; 530 531 struct macsec_context; 532 struct macsec_ops; 533 534 /** 535 * struct phy_oatc14_sqi_capability - SQI capability information for OATC14 536 * 10Base-T1S PHY 537 * @updated: Indicates whether the SQI capability fields have been updated. 538 * @sqi_max: Maximum supported Signal Quality Indicator (SQI) level reported by 539 * the PHY. 540 * @sqiplus_bits: Bits for SQI+ levels supported by the PHY. 541 * 0 - SQI+ is not supported 542 * 3 - SQI+ is supported, using 3 bits (8 levels) 543 * 4 - SQI+ is supported, using 4 bits (16 levels) 544 * 5 - SQI+ is supported, using 5 bits (32 levels) 545 * 6 - SQI+ is supported, using 6 bits (64 levels) 546 * 7 - SQI+ is supported, using 7 bits (128 levels) 547 * 8 - SQI+ is supported, using 8 bits (256 levels) 548 * 549 * This structure is used by the OATC14 10Base-T1S PHY driver to store the SQI 550 * and SQI+ capability information retrieved from the PHY. 551 */ 552 struct phy_oatc14_sqi_capability { 553 bool updated; 554 int sqi_max; 555 u8 sqiplus_bits; 556 }; 557 558 /** 559 * struct phy_device - An instance of a PHY 560 * 561 * @mdio: MDIO bus this PHY is on 562 * @drv: Pointer to the driver for this PHY instance 563 * @devlink: Create a link between phy dev and mac dev, if the external phy 564 * used by current mac interface is managed by another mac interface. 565 * @phyindex: Unique id across the phy's parent tree of phys to address the PHY 566 * from userspace, similar to ifindex. A zero index means the PHY 567 * wasn't assigned an id yet. 568 * @phy_id: UID for this device found during discovery 569 * @c45_ids: 802.3-c45 Device Identifiers if is_c45. 570 * @is_c45: Set to true if this PHY uses clause 45 addressing. 571 * @is_internal: Set to true if this PHY is internal to a MAC. 572 * @is_pseudo_fixed_link: Set to true if this PHY is an Ethernet switch, etc. 573 * @is_gigabit_capable: Set to true if PHY supports 1000Mbps 574 * @has_fixups: Set to true if this PHY has fixups/quirks. 575 * @suspended: Set to true if this PHY has been suspended successfully. 576 * @suspended_by_mdio_bus: Set to true if this PHY was suspended by MDIO bus. 577 * @sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal. 578 * @loopback_enabled: Set true if this PHY has been loopbacked successfully. 579 * @downshifted_rate: Set true if link speed has been downshifted. 580 * @is_on_sfp_module: Set true if PHY is located on an SFP module. 581 * @mac_managed_pm: Set true if MAC driver takes of suspending/resuming PHY 582 * @wol_enabled: Set to true if the PHY or the attached MAC have Wake-on-LAN 583 * enabled. 584 * @is_genphy_driven: PHY is driven by one of the generic PHY drivers 585 * @state: State of the PHY for management purposes 586 * @dev_flags: Device-specific flags used by the PHY driver. 587 * 588 * - Bits [15:0] are free to use by the PHY driver to communicate 589 * driver specific behavior. 590 * - Bits [23:16] are currently reserved for future use. 591 * - Bits [31:24] are reserved for defining generic 592 * PHY driver behavior. 593 * @irq: IRQ number of the PHY's interrupt (-1 if none) 594 * @phylink: Pointer to phylink instance for this PHY 595 * @sfp_bus_attached: Flag indicating whether the SFP bus has been attached 596 * @sfp_bus: SFP bus attached to this PHY's fiber port 597 * @attached_dev: The attached enet driver's device instance ptr 598 * @adjust_link: Callback for the enet controller to respond to changes: in the 599 * link state. 600 * @phy_link_change: Callback for phylink for notification of link change 601 * @macsec_ops: MACsec offloading ops. 602 * 603 * @speed: Current link speed 604 * @duplex: Current duplex 605 * @port: Current port 606 * @pause: Current pause 607 * @asym_pause: Current asymmetric pause 608 * @supported: Combined MAC/PHY supported linkmodes 609 * @advertising: Currently advertised linkmodes 610 * @adv_old: Saved advertised while power saving for WoL 611 * @supported_eee: supported PHY EEE linkmodes 612 * @advertising_eee: Currently advertised EEE linkmodes 613 * @enable_tx_lpi: When True, MAC should transmit LPI to PHY 614 * @eee_active: phylib private state, indicating that EEE has been negotiated 615 * @autonomous_eee_disabled: Set when autonomous EEE has been disabled, 616 * used to re-apply after PHY soft reset 617 * @eee_cfg: User configuration of EEE 618 * @lp_advertising: Current link partner advertised linkmodes 619 * @host_interfaces: PHY interface modes supported by host 620 * @eee_disabled_modes: Energy efficient ethernet modes not to be advertised 621 * @autoneg: Flag autoneg being used 622 * @rate_matching: Current rate matching mode 623 * @link: Current link state 624 * @autoneg_complete: Flag auto negotiation of the link has completed 625 * @mdix: Current crossover 626 * @mdix_ctrl: User setting of crossover 627 * @pma_extable: Cached value of PMA/PMD Extended Abilities Register 628 * @interrupts: Flag interrupts have been enabled 629 * @irq_suspended: Flag indicating PHY is suspended and therefore interrupt 630 * handling shall be postponed until PHY has resumed 631 * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended, 632 * requiring a rerun of the interrupt handler after resume 633 * @default_timestamp: Flag indicating whether we are using the phy 634 * timestamp as the default one 635 * @interface: enum phy_interface_t value 636 * @possible_interfaces: bitmap if interface modes that the attached PHY 637 * will switch between depending on media speed. 638 * @skb: Netlink message for cable diagnostics 639 * @nest: Netlink nest used for cable diagnostics 640 * @ehdr: nNtlink header for cable diagnostics 641 * @phy_led_triggers: Array of LED triggers 642 * @phy_num_led_triggers: Number of triggers in @phy_led_triggers 643 * @led_link_trigger: LED trigger for link up/down 644 * @last_triggered: last LED trigger for link speed 645 * @leds: list of PHY LED structures 646 * @master_slave_set: User requested master/slave configuration 647 * @master_slave_get: Current master/slave advertisement 648 * @master_slave_state: Current master/slave configuration 649 * @mii_ts: Pointer to time stamper callbacks 650 * @psec: Pointer to Power Sourcing Equipment control struct 651 * @ports: List of PHY ports structures 652 * @n_ports: Number of ports currently attached to the PHY 653 * @max_n_ports: Max number of ports this PHY can expose 654 * @lock: Mutex for serialization access to PHY 655 * @state_queue: Work queue for state machine 656 * @link_down_events: Number of times link was lost 657 * @shared: Pointer to private data shared by phys in one package 658 * @priv: Pointer to driver private data 659 * @oatc14_sqi_capability: SQI capability information for OATC14 10Base-T1S PHY 660 * 661 * interrupts currently only supports enabled or disabled, 662 * but could be changed in the future to support enabling 663 * and disabling specific interrupts 664 * 665 * Contains some infrastructure for polling and interrupt 666 * handling, as well as handling shifts in PHY hardware state 667 */ 668 struct phy_device { 669 struct mdio_device mdio; 670 671 /* Information about the PHY type */ 672 /* And management functions */ 673 const struct phy_driver *drv; 674 675 struct device_link *devlink; 676 677 u32 phyindex; 678 u32 phy_id; 679 680 struct phy_c45_device_ids c45_ids; 681 unsigned is_c45:1; 682 unsigned is_internal:1; 683 unsigned is_pseudo_fixed_link:1; 684 unsigned is_gigabit_capable:1; 685 unsigned has_fixups:1; 686 unsigned suspended:1; 687 unsigned suspended_by_mdio_bus:1; 688 unsigned sysfs_links:1; 689 unsigned loopback_enabled:1; 690 unsigned downshifted_rate:1; 691 unsigned is_on_sfp_module:1; 692 unsigned mac_managed_pm:1; 693 unsigned wol_enabled:1; 694 unsigned is_genphy_driven:1; 695 696 unsigned autoneg:1; 697 /* The most recently read link state */ 698 unsigned link:1; 699 unsigned autoneg_complete:1; 700 bool pause:1; 701 bool asym_pause:1; 702 703 /* Interrupts are enabled */ 704 unsigned interrupts:1; 705 unsigned irq_suspended:1; 706 unsigned irq_rerun:1; 707 708 unsigned default_timestamp:1; 709 710 int rate_matching; 711 712 enum phy_state state; 713 714 u32 dev_flags; 715 716 phy_interface_t interface; 717 DECLARE_PHY_INTERFACE_MASK(possible_interfaces); 718 719 /* 720 * forced speed & duplex (no autoneg) 721 * partner speed & duplex & pause (autoneg) 722 */ 723 int speed; 724 int duplex; 725 int port; 726 u8 master_slave_get; 727 u8 master_slave_set; 728 u8 master_slave_state; 729 730 /* Union of PHY and Attached devices' supported link modes */ 731 /* See ethtool.h for more info */ 732 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 733 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 734 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising); 735 /* used with phy_speed_down */ 736 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old); 737 /* used for eee validation and configuration*/ 738 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_eee); 739 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising_eee); 740 /* Energy efficient ethernet modes which should be prohibited */ 741 __ETHTOOL_DECLARE_LINK_MODE_MASK(eee_disabled_modes); 742 bool enable_tx_lpi; 743 bool eee_active; 744 bool autonomous_eee_disabled; 745 struct eee_config eee_cfg; 746 747 /* Host supported PHY interface types. Should be ignored if empty. */ 748 DECLARE_PHY_INTERFACE_MASK(host_interfaces); 749 750 #ifdef CONFIG_LED_TRIGGER_PHY 751 struct phy_led_trigger *phy_led_triggers; 752 unsigned int phy_num_led_triggers; 753 struct phy_led_trigger *last_triggered; 754 755 struct phy_led_trigger *led_link_trigger; 756 #endif 757 struct list_head leds; 758 759 /* 760 * Interrupt number for this PHY 761 * -1 means no interrupt 762 */ 763 int irq; 764 765 /* private data pointer */ 766 /* For use by PHYs to maintain extra state */ 767 void *priv; 768 769 #if IS_ENABLED(CONFIG_PHY_PACKAGE) 770 /* shared data pointer */ 771 /* For use by PHYs inside the same package that need a shared state. */ 772 struct phy_package_shared *shared; 773 #endif 774 775 /* Reporting cable test results */ 776 struct sk_buff *skb; 777 void *ehdr; 778 struct nlattr *nest; 779 780 /* Interrupt and Polling infrastructure */ 781 struct delayed_work state_queue; 782 783 struct mutex lock; 784 785 /* This may be modified under the rtnl lock */ 786 bool sfp_bus_attached; 787 struct sfp_bus *sfp_bus; 788 struct phylink *phylink; 789 struct net_device *attached_dev; 790 struct mii_timestamper *mii_ts; 791 struct pse_control *psec; 792 793 struct list_head ports; 794 int n_ports; 795 int max_n_ports; 796 797 u8 mdix; 798 u8 mdix_ctrl; 799 800 int pma_extable; 801 802 unsigned int link_down_events; 803 804 void (*phy_link_change)(struct phy_device *phydev, bool up); 805 void (*adjust_link)(struct net_device *dev); 806 807 #if IS_ENABLED(CONFIG_MACSEC) 808 /* MACsec management functions */ 809 const struct macsec_ops *macsec_ops; 810 #endif 811 812 struct phy_oatc14_sqi_capability oatc14_sqi_capability; 813 }; 814 815 /* Generic phy_device::dev_flags */ 816 #define PHY_F_NO_IRQ 0x80000000 817 #define PHY_F_RXC_ALWAYS_ON 0x40000000 818 #define PHY_F_KEEP_PREAMBLE_BEFORE_SFD 0x20000000 819 820 #define to_phy_device(__dev) container_of_const(to_mdio_device(__dev), struct phy_device, mdio) 821 822 #define phy_for_each_port(phydev, port) \ 823 list_for_each_entry(port, &(phydev)->ports, head) 824 825 /** 826 * struct phy_tdr_config - Configuration of a TDR raw test 827 * 828 * @first: Distance for first data collection point 829 * @last: Distance for last data collection point 830 * @step: Step between data collection points 831 * @pair: Bitmap of cable pairs to collect data for 832 * 833 * A structure containing possible configuration parameters 834 * for a TDR cable test. The driver does not need to implement 835 * all the parameters, but should report what is actually used. 836 * All distances are in centimeters. 837 */ 838 struct phy_tdr_config { 839 u32 first; 840 u32 last; 841 u32 step; 842 s8 pair; 843 }; 844 #define PHY_PAIR_ALL -1 845 846 /** 847 * enum link_inband_signalling - in-band signalling modes that are supported 848 * 849 * @LINK_INBAND_DISABLE: in-band signalling can be disabled 850 * @LINK_INBAND_ENABLE: in-band signalling can be enabled without bypass 851 * @LINK_INBAND_BYPASS: in-band signalling can be enabled with bypass 852 * 853 * The possible and required bits can only be used if the valid bit is set. 854 * If possible is clear, that means inband signalling can not be used. 855 * Required is only valid when possible is set, and means that inband 856 * signalling must be used. 857 */ 858 enum link_inband_signalling { 859 LINK_INBAND_DISABLE = BIT(0), 860 LINK_INBAND_ENABLE = BIT(1), 861 LINK_INBAND_BYPASS = BIT(2), 862 }; 863 864 /** 865 * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision 866 * Avoidance) Reconciliation Sublayer. 867 * 868 * @version: read-only PLCA register map version. -1 = not available. Ignored 869 * when setting the configuration. Format is the same as reported by the PLCA 870 * IDVER register (31.CA00). -1 = not available. 871 * @enabled: PLCA configured mode (enabled/disabled). -1 = not available / don't 872 * set. 0 = disabled, anything else = enabled. 873 * @node_id: the PLCA local node identifier. -1 = not available / don't set. 874 * Allowed values [0 .. 254]. 255 = node disabled. 875 * @node_cnt: the PLCA node count (maximum number of nodes having a TO). Only 876 * meaningful for the coordinator (node_id = 0). -1 = not available / don't 877 * set. Allowed values [1 .. 255]. 878 * @to_tmr: The value of the PLCA to_timer in bit-times, which determines the 879 * PLCA transmit opportunity window opening. See IEEE802.3 Clause 148 for 880 * more details. The to_timer shall be set equal over all nodes. 881 * -1 = not available / don't set. Allowed values [0 .. 255]. 882 * @burst_cnt: controls how many additional frames a node is allowed to send in 883 * single transmit opportunity (TO). The default value of 0 means that the 884 * node is allowed exactly one frame per TO. A value of 1 allows two frames 885 * per TO, and so on. -1 = not available / don't set. 886 * Allowed values [0 .. 255]. 887 * @burst_tmr: controls how many bit times to wait for the MAC to send a new 888 * frame before interrupting the burst. This value should be set to a value 889 * greater than the MAC inter-packet gap (which is typically 96 bits). 890 * -1 = not available / don't set. Allowed values [0 .. 255]. 891 * 892 * A structure containing configuration parameters for setting/getting the PLCA 893 * RS configuration. The driver does not need to implement all the parameters, 894 * but should report what is actually used. 895 */ 896 struct phy_plca_cfg { 897 int version; 898 int enabled; 899 int node_id; 900 int node_cnt; 901 int to_tmr; 902 int burst_cnt; 903 int burst_tmr; 904 }; 905 906 /** 907 * struct phy_plca_status - Status of the PLCA (Physical Layer Collision 908 * Avoidance) Reconciliation Sublayer. 909 * 910 * @pst: The PLCA status as reported by the PST bit in the PLCA STATUS 911 * register(31.CA03), indicating BEACON activity. 912 * 913 * A structure containing status information of the PLCA RS configuration. 914 * The driver does not need to implement all the parameters, but should report 915 * what is actually used. 916 */ 917 struct phy_plca_status { 918 bool pst; 919 }; 920 921 /* Modes for PHY LED configuration */ 922 enum phy_led_modes { 923 PHY_LED_ACTIVE_HIGH = 0, 924 PHY_LED_ACTIVE_LOW = 1, 925 PHY_LED_INACTIVE_HIGH_IMPEDANCE = 2, 926 927 /* keep it last */ 928 __PHY_LED_MODES_NUM, 929 }; 930 931 /** 932 * struct phy_led: An LED driven by the PHY 933 * 934 * @list: List of LEDs 935 * @phydev: PHY this LED is attached to 936 * @led_cdev: Standard LED class structure 937 * @index: Number of the LED 938 */ 939 struct phy_led { 940 struct list_head list; 941 struct phy_device *phydev; 942 struct led_classdev led_cdev; 943 u8 index; 944 }; 945 946 #define to_phy_led(d) container_of(d, struct phy_led, led_cdev) 947 948 /* 949 * PHY_MSE_CAP_* - Bitmask flags for Mean Square Error (MSE) capabilities 950 * 951 * These flags describe which MSE metrics and selectors are implemented 952 * by the PHY for the current link mode. They are used in 953 * struct phy_mse_capability.supported_caps. 954 * 955 * Standardization: 956 * The OPEN Alliance (OA) defines the presence of MSE/SQI/pMSE but not their 957 * numeric scaling, update intervals, or aggregation windows. See: 958 * OA 100BASE-T1 TC1 v1.0, sections 6.1.1-6.1.3 959 * OA 1000BASE-T1 TC12 v2.2, sections 6.1.1-6.1.2 960 * 961 * Description of flags: 962 * 963 * PHY_MSE_CAP_CHANNEL_A 964 * Per-pair diagnostics for Channel A are supported. Mapping to the 965 * physical wire pair may depend on MDI/MDI-X polarity. 966 * 967 * PHY_MSE_CAP_CHANNEL_B, _C, _D 968 * Same as above for channels B-D. 969 * 970 * PHY_MSE_CAP_WORST_CHANNEL 971 * The PHY or driver can identify and report the single worst-performing 972 * channel without querying each one individually. 973 * 974 * PHY_MSE_CAP_LINK 975 * The PHY provides only a link-wide aggregate measurement or cannot map 976 * results to a specific pair (for example 100BASE-TX with unknown 977 * MDI/MDI-X). 978 * 979 * PHY_MSE_CAP_AVG 980 * Average MSE (mean DCQ metric) is supported. For 100/1000BASE-T1 the OA 981 * recommends 2^16 symbols, scaled 0..511, but the exact scaling is 982 * vendor-specific. 983 * 984 * PHY_MSE_CAP_PEAK 985 * Peak MSE (current peak within the measurement window) is supported. 986 * Defined as pMSE for 100BASE-T1; vendor-specific for others. 987 * 988 * PHY_MSE_CAP_WORST_PEAK 989 * Latched worst-case peak MSE since the last read (read-to-clear if 990 * implemented). Optional in OA 100BASE-T1 TC1 6.1.3. 991 */ 992 #define PHY_MSE_CAP_CHANNEL_A BIT(0) 993 #define PHY_MSE_CAP_CHANNEL_B BIT(1) 994 #define PHY_MSE_CAP_CHANNEL_C BIT(2) 995 #define PHY_MSE_CAP_CHANNEL_D BIT(3) 996 #define PHY_MSE_CAP_WORST_CHANNEL BIT(4) 997 #define PHY_MSE_CAP_LINK BIT(5) 998 #define PHY_MSE_CAP_AVG BIT(6) 999 #define PHY_MSE_CAP_PEAK BIT(7) 1000 #define PHY_MSE_CAP_WORST_PEAK BIT(8) 1001 1002 /* 1003 * enum phy_mse_channel - Identifiers for selecting MSE measurement channels 1004 * 1005 * PHY_MSE_CHANNEL_A - PHY_MSE_CHANNEL_D 1006 * Select per-pair measurement for the corresponding channel. 1007 * 1008 * PHY_MSE_CHANNEL_WORST 1009 * Select the single worst-performing channel reported by hardware. 1010 * 1011 * PHY_MSE_CHANNEL_LINK 1012 * Select link-wide aggregate data (used when per-pair results are 1013 * unavailable). 1014 */ 1015 enum phy_mse_channel { 1016 PHY_MSE_CHANNEL_A, 1017 PHY_MSE_CHANNEL_B, 1018 PHY_MSE_CHANNEL_C, 1019 PHY_MSE_CHANNEL_D, 1020 PHY_MSE_CHANNEL_WORST, 1021 PHY_MSE_CHANNEL_LINK, 1022 }; 1023 1024 /** 1025 * struct phy_mse_capability - Capabilities of Mean Square Error (MSE) 1026 * measurement interface 1027 * 1028 * Standardization notes: 1029 * 1030 * - Presence of MSE/SQI/pMSE is defined by OPEN Alliance specs, but numeric 1031 * scaling, refresh/update rate and aggregation windows are not fixed and 1032 * are vendor-/product-specific. (OA 100BASE-T1 TC1 v1.0 6.1.*; 1033 * OA 1000BASE-T1 TC12 v2.2 6.1.*) 1034 * 1035 * - Typical recommendations: 2^16 symbols and 0..511 scaling for MSE; pMSE only 1036 * defined for 100BASE-T1 (sliding window example), others are vendor 1037 * extensions. Drivers must report actual scale/limits here. 1038 * 1039 * Describes the MSE measurement capabilities for the current link mode. These 1040 * properties are dynamic and may change when link settings are modified. 1041 * Callers should re-query this capability after any link state change to 1042 * ensure they have the most up-to-date information. 1043 * 1044 * Callers should only request measurements for channels and types that are 1045 * indicated as supported by the @supported_caps bitmask. If @supported_caps 1046 * is 0, the device provides no MSE diagnostics, and driver operations should 1047 * typically return -EOPNOTSUPP. 1048 * 1049 * Snapshot values for average and peak MSE can be normalized to a 0..1 ratio 1050 * by dividing the raw snapshot by the corresponding @max_average_mse or 1051 * @max_peak_mse value. 1052 * 1053 * @max_average_mse: The maximum value for an average MSE snapshot. This 1054 * defines the scale for the measurement. If the PHY_MSE_CAP_AVG capability is 1055 * supported, this value MUST be greater than 0. (vendor-specific units). 1056 * @max_peak_mse: The maximum value for a peak MSE snapshot. If either 1057 * PHY_MSE_CAP_PEAK or PHY_MSE_CAP_WORST_PEAK is supported, this value MUST 1058 * be greater than 0. (vendor-specific units). 1059 * @refresh_rate_ps: The typical interval, in picoseconds, between hardware 1060 * updates of the MSE values. This is an estimate, and callers should not 1061 * assume synchronous sampling. (vendor-specific units). 1062 * @num_symbols: The number of symbols aggregated per hardware sample to 1063 * calculate the MSE. (vendor-specific units). 1064 * @supported_caps: A bitmask of PHY_MSE_CAP_* values indicating which 1065 * measurement types (e.g., average, peak) and channels 1066 * (e.g., per-pair or link-wide) are supported. 1067 */ 1068 struct phy_mse_capability { 1069 u64 max_average_mse; 1070 u64 max_peak_mse; 1071 u64 refresh_rate_ps; 1072 u64 num_symbols; 1073 u32 supported_caps; 1074 }; 1075 1076 /** 1077 * struct phy_mse_snapshot - A snapshot of Mean Square Error (MSE) diagnostics 1078 * 1079 * Holds a set of MSE diagnostic values that were all captured from a single 1080 * measurement window. 1081 * 1082 * Values are raw, device-scaled and not normalized. Use struct 1083 * phy_mse_capability to interpret the scale and sampling window. 1084 * 1085 * @average_mse: The average MSE value over the measurement window. 1086 * OPEN Alliance references MSE as a DCQ metric; recommends 2^16 symbols and 1087 * 0..511 scaling. Exact scale and refresh are vendor-specific. 1088 * (100BASE-T1 TC1 v1.0 6.1.1; 1000BASE-T1 TC12 v2.2 6.1.1). 1089 * 1090 * @peak_mse: The peak MSE value observed within the measurement window. 1091 * For 100BASE-T1, "pMSE" is optional and may be implemented via a sliding 1092 * 128-symbol window with periodic capture; not standardized for 1000BASE-T1. 1093 * (100BASE-T1 TC1 v1.0 6.1.3, Table "DCQ.peakMSE"). 1094 * 1095 * @worst_peak_mse: A latched high-water mark of the peak MSE since last read 1096 * (read-to-clear if implemented). OPEN Alliance shows a latched "worst case 1097 * peak MSE" for 100BASE-T1 pMSE; availability/semantics outside that are 1098 * vendor-specific. (100BASE-T1 TC1 v1.0 6.1.3, DCQ.peakMSE high byte; 1099 * 1000BASE-T1 TC12 v2.2 treats DCQ details as vendor-specific.) 1100 */ 1101 struct phy_mse_snapshot { 1102 u64 average_mse; 1103 u64 peak_mse; 1104 u64 worst_peak_mse; 1105 }; 1106 1107 /** 1108 * struct phy_driver - Driver structure for a particular PHY type 1109 * 1110 * @mdiodrv: Data common to all MDIO devices 1111 * @phy_id: The result of reading the UID registers of this PHY 1112 * type, and ANDing them with the phy_id_mask. This driver 1113 * only works for PHYs with IDs which match this field 1114 * @name: The friendly name of this PHY type 1115 * @phy_id_mask: Defines the important bits of the phy_id 1116 * @features: A mandatory list of features (speed, duplex, etc) 1117 * supported by this PHY 1118 * @flags: A bitfield defining certain other features this PHY 1119 * supports (like interrupts) 1120 * @driver_data: Static driver data 1121 * 1122 * All functions are optional. If config_aneg or read_status 1123 * are not implemented, the phy core uses the genphy versions. 1124 * Note that none of these functions should be called from 1125 * interrupt time. The goal is for the bus read/write functions 1126 * to be able to block when the bus transaction is happening, 1127 * and be freed up by an interrupt (The MPC85xx has this ability, 1128 * though it is not currently supported in the driver). 1129 */ 1130 struct phy_driver { 1131 struct mdio_driver_common mdiodrv; 1132 u32 phy_id; 1133 char *name; 1134 u32 phy_id_mask; 1135 const unsigned long * const features; 1136 u32 flags; 1137 const void *driver_data; 1138 1139 /** 1140 * @soft_reset: Called to issue a PHY software reset 1141 */ 1142 int (*soft_reset)(struct phy_device *phydev); 1143 1144 /** 1145 * @config_init: Called to initialize the PHY, 1146 * including after a reset 1147 */ 1148 int (*config_init)(struct phy_device *phydev); 1149 1150 /** 1151 * @probe: Called during discovery. Used to set 1152 * up device-specific structures, if any 1153 */ 1154 int (*probe)(struct phy_device *phydev); 1155 1156 /** 1157 * @get_features: Probe the hardware to determine what 1158 * abilities it has. Should only set phydev->supported. 1159 */ 1160 int (*get_features)(struct phy_device *phydev); 1161 1162 /** 1163 * @inband_caps: query whether in-band is supported for the given PHY 1164 * interface mode. Returns a bitmask of bits defined by enum 1165 * link_inband_signalling. 1166 */ 1167 unsigned int (*inband_caps)(struct phy_device *phydev, 1168 phy_interface_t interface); 1169 1170 /** 1171 * @config_inband: configure in-band mode for the PHY 1172 */ 1173 int (*config_inband)(struct phy_device *phydev, unsigned int modes); 1174 1175 /** 1176 * @get_rate_matching: Get the supported type of rate matching for a 1177 * particular phy interface. This is used by phy consumers to determine 1178 * whether to advertise lower-speed modes for that interface. It is 1179 * assumed that if a rate matching mode is supported on an interface, 1180 * then that interface's rate can be adapted to all slower link speeds 1181 * supported by the phy. If the interface is not supported, this should 1182 * return %RATE_MATCH_NONE. 1183 */ 1184 int (*get_rate_matching)(struct phy_device *phydev, 1185 phy_interface_t iface); 1186 1187 /* PHY Power Management */ 1188 /** @suspend: Suspend the hardware, saving state if needed */ 1189 int (*suspend)(struct phy_device *phydev); 1190 /** @resume: Resume the hardware, restoring state if needed */ 1191 int (*resume)(struct phy_device *phydev); 1192 1193 /** 1194 * @config_aneg: Configures the advertisement and resets 1195 * autonegotiation if phydev->autoneg is on, 1196 * forces the speed to the current settings in phydev 1197 * if phydev->autoneg is off 1198 */ 1199 int (*config_aneg)(struct phy_device *phydev); 1200 1201 /** @aneg_done: Determines the auto negotiation result */ 1202 int (*aneg_done)(struct phy_device *phydev); 1203 1204 /** @read_status: Determines the negotiated speed and duplex */ 1205 int (*read_status)(struct phy_device *phydev); 1206 1207 /** 1208 * @config_intr: Enables or disables interrupts. 1209 * It should also clear any pending interrupts prior to enabling the 1210 * IRQs and after disabling them. 1211 */ 1212 int (*config_intr)(struct phy_device *phydev); 1213 1214 /** @handle_interrupt: Override default interrupt handling */ 1215 irqreturn_t (*handle_interrupt)(struct phy_device *phydev); 1216 1217 /** @remove: Clears up any memory if needed */ 1218 void (*remove)(struct phy_device *phydev); 1219 1220 /** 1221 * @match_phy_device: Returns true if this is a suitable 1222 * driver for the given phydev. If NULL, matching is based on 1223 * phy_id and phy_id_mask. 1224 */ 1225 int (*match_phy_device)(struct phy_device *phydev, 1226 const struct phy_driver *phydrv); 1227 1228 /** 1229 * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY 1230 * register changes to enable Wake on LAN, so set_wol is 1231 * provided to be called in the ethernet driver's set_wol 1232 * function. 1233 */ 1234 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol); 1235 1236 /** 1237 * @get_wol: See set_wol, but for checking whether Wake on LAN 1238 * is enabled. 1239 */ 1240 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol); 1241 1242 /** 1243 * @link_change_notify: Called to inform a PHY device driver 1244 * when the core is about to change the link state. This 1245 * callback is supposed to be used as fixup hook for drivers 1246 * that need to take action when the link state 1247 * changes. Drivers are by no means allowed to mess with the 1248 * PHY device structure in their implementations. 1249 */ 1250 void (*link_change_notify)(struct phy_device *dev); 1251 1252 /** 1253 * @read_mmd: PHY specific driver override for reading a MMD 1254 * register. This function is optional for PHY specific 1255 * drivers. When not provided, the default MMD read function 1256 * will be used by phy_read_mmd(), which will use either a 1257 * direct read for Clause 45 PHYs or an indirect read for 1258 * Clause 22 PHYs. devnum is the MMD device number within the 1259 * PHY device, regnum is the register within the selected MMD 1260 * device. 1261 */ 1262 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum); 1263 1264 /** 1265 * @write_mmd: PHY specific driver override for writing a MMD 1266 * register. This function is optional for PHY specific 1267 * drivers. When not provided, the default MMD write function 1268 * will be used by phy_write_mmd(), which will use either a 1269 * direct write for Clause 45 PHYs, or an indirect write for 1270 * Clause 22 PHYs. devnum is the MMD device number within the 1271 * PHY device, regnum is the register within the selected MMD 1272 * device. val is the value to be written. 1273 */ 1274 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum, 1275 u16 val); 1276 1277 /** @read_page: Return the current PHY register page number */ 1278 int (*read_page)(struct phy_device *dev); 1279 /** @write_page: Set the current PHY register page number */ 1280 int (*write_page)(struct phy_device *dev, int page); 1281 1282 /** 1283 * @module_info: Get the size and type of the eeprom contained 1284 * within a plug-in module 1285 */ 1286 int (*module_info)(struct phy_device *dev, 1287 struct ethtool_modinfo *modinfo); 1288 1289 /** 1290 * @module_eeprom: Get the eeprom information from the plug-in 1291 * module 1292 */ 1293 int (*module_eeprom)(struct phy_device *dev, 1294 struct ethtool_eeprom *ee, u8 *data); 1295 1296 /** @cable_test_start: Start a cable test */ 1297 int (*cable_test_start)(struct phy_device *dev); 1298 1299 /** @cable_test_tdr_start: Start a raw TDR cable test */ 1300 int (*cable_test_tdr_start)(struct phy_device *dev, 1301 const struct phy_tdr_config *config); 1302 1303 /** 1304 * @cable_test_get_status: Once per second, or on interrupt, 1305 * request the status of the test. 1306 */ 1307 int (*cable_test_get_status)(struct phy_device *dev, bool *finished); 1308 1309 /* Get statistics from the PHY using ethtool */ 1310 /** 1311 * @get_phy_stats: Retrieve PHY statistics. 1312 * @dev: The PHY device for which the statistics are retrieved. 1313 * @eth_stats: structure where Ethernet PHY stats will be stored. 1314 * @stats: structure where additional PHY-specific stats will be stored. 1315 * 1316 * Retrieves the supported PHY statistics and populates the provided 1317 * structures. The input structures are pre-initialized with 1318 * `ETHTOOL_STAT_NOT_SET`, and the driver must only modify members 1319 * corresponding to supported statistics. Unmodified members will remain 1320 * set to `ETHTOOL_STAT_NOT_SET` and will not be returned to userspace. 1321 */ 1322 void (*get_phy_stats)(struct phy_device *dev, 1323 struct ethtool_eth_phy_stats *eth_stats, 1324 struct ethtool_phy_stats *stats); 1325 1326 /** 1327 * @get_link_stats: Retrieve link statistics. 1328 * @dev: The PHY device for which the statistics are retrieved. 1329 * @link_stats: structure where link-specific stats will be stored. 1330 * 1331 * Retrieves link-related statistics for the given PHY device. The input 1332 * structure is pre-initialized with `ETHTOOL_STAT_NOT_SET`, and the 1333 * driver must only modify members corresponding to supported 1334 * statistics. Unmodified members will remain set to 1335 * `ETHTOOL_STAT_NOT_SET` and will not be returned to userspace. 1336 */ 1337 void (*get_link_stats)(struct phy_device *dev, 1338 struct ethtool_link_ext_stats *link_stats); 1339 1340 /** 1341 * @update_stats: Trigger periodic statistics updates. 1342 * @dev: The PHY device for which statistics updates are triggered. 1343 * 1344 * Periodically gathers statistics from the PHY device to update locally 1345 * maintained 64-bit counters. This is necessary for PHYs that implement 1346 * reduced-width counters (e.g., 16-bit or 32-bit) which can overflow 1347 * more frequently compared to 64-bit counters. By invoking this 1348 * callback, drivers can fetch the current counter values, handle 1349 * overflow detection, and accumulate the results into local 64-bit 1350 * counters for accurate reporting through the `get_phy_stats` and 1351 * `get_link_stats` interfaces. 1352 * 1353 * Return: 0 on success or a negative error code on failure. 1354 */ 1355 int (*update_stats)(struct phy_device *dev); 1356 1357 /** @get_sset_count: Number of statistic counters */ 1358 int (*get_sset_count)(struct phy_device *dev); 1359 /** @get_strings: Names of the statistic counters */ 1360 void (*get_strings)(struct phy_device *dev, u8 *data); 1361 /** @get_stats: Return the statistic counter values */ 1362 void (*get_stats)(struct phy_device *dev, 1363 struct ethtool_stats *stats, u64 *data); 1364 1365 /** 1366 * @disable_autonomous_eee: Disable PHY-autonomous EEE 1367 * 1368 * Some PHYs manage EEE autonomously, preventing the MAC from 1369 * controlling LPI signaling. This callback disables autonomous 1370 * EEE at the PHY. 1371 * 1372 * Return: 0 on success, negative errno on failure. 1373 */ 1374 int (*disable_autonomous_eee)(struct phy_device *dev); 1375 1376 /* Get and Set PHY tunables */ 1377 /** @get_tunable: Return the value of a tunable */ 1378 int (*get_tunable)(struct phy_device *dev, 1379 struct ethtool_tunable *tuna, void *data); 1380 /** @set_tunable: Set the value of a tunable */ 1381 int (*set_tunable)(struct phy_device *dev, 1382 struct ethtool_tunable *tuna, 1383 const void *data); 1384 /** 1385 * @set_loopback: Set the loopback mode of the PHY 1386 * enable selects if the loopback mode is enabled or disabled. If the 1387 * loopback mode is enabled, then the speed of the loopback mode can be 1388 * requested with the speed argument. If the speed argument is zero, 1389 * then any speed can be selected. If the speed argument is > 0, then 1390 * this speed shall be selected for the loopback mode or EOPNOTSUPP 1391 * shall be returned if speed selection is not supported. 1392 */ 1393 int (*set_loopback)(struct phy_device *dev, bool enable, int speed); 1394 /** @get_sqi: Get the signal quality indication */ 1395 int (*get_sqi)(struct phy_device *dev); 1396 /** @get_sqi_max: Get the maximum signal quality indication */ 1397 int (*get_sqi_max)(struct phy_device *dev); 1398 1399 /** 1400 * @get_mse_capability: Get capabilities and scale of MSE measurement 1401 * @dev: PHY device 1402 * @cap: Output (filled on success) 1403 * 1404 * Fill @cap with the PHY's MSE capability for the current 1405 * link mode: scale limits (max_average_mse, max_peak_mse), update 1406 * interval (refresh_rate_ps), sample length (num_symbols) and the 1407 * capability bitmask (supported_caps). 1408 * 1409 * Implementations may defer capability report until hardware has 1410 * converged; in that case they should return -EAGAIN and allow the 1411 * caller to retry later. 1412 * 1413 * Return: 0 on success. On failure, returns a negative errno code, such 1414 * as -EOPNOTSUPP if MSE measurement is not supported by the PHY or in 1415 * the current link mode, or -EAGAIN if the capability information is 1416 * not yet available. 1417 */ 1418 int (*get_mse_capability)(struct phy_device *dev, 1419 struct phy_mse_capability *cap); 1420 1421 /** 1422 * @get_mse_snapshot: Retrieve a snapshot of MSE diagnostic values 1423 * @dev: PHY device 1424 * @channel: Channel identifier (PHY_MSE_CHANNEL_*) 1425 * @snapshot: Output (filled on success) 1426 * 1427 * Fill @snapshot with a correlated set of MSE values from the most 1428 * recent measurement window. 1429 * 1430 * Callers must validate @channel against supported_caps returned by 1431 * get_mse_capability(). Drivers must not coerce @channel; if the 1432 * requested selector is not implemented by the device or current link 1433 * mode, the operation must fail. 1434 * 1435 * worst_peak_mse is latched and must be treated as read-to-clear. 1436 * 1437 * Return: 0 on success. On failure, returns a negative errno code, such 1438 * as -EOPNOTSUPP if MSE measurement is not supported by the PHY or in 1439 * the current link mode, or -EAGAIN if measurements are not yet 1440 * available. 1441 */ 1442 int (*get_mse_snapshot)(struct phy_device *dev, 1443 enum phy_mse_channel channel, 1444 struct phy_mse_snapshot *snapshot); 1445 1446 /* PLCA RS interface */ 1447 /** @get_plca_cfg: Return the current PLCA configuration */ 1448 int (*get_plca_cfg)(struct phy_device *dev, 1449 struct phy_plca_cfg *plca_cfg); 1450 /** @set_plca_cfg: Set the PLCA configuration */ 1451 int (*set_plca_cfg)(struct phy_device *dev, 1452 const struct phy_plca_cfg *plca_cfg); 1453 /** @get_plca_status: Return the current PLCA status info */ 1454 int (*get_plca_status)(struct phy_device *dev, 1455 struct phy_plca_status *plca_st); 1456 1457 /** 1458 * @led_brightness_set: Set a PHY LED brightness. Index 1459 * indicates which of the PHYs led should be set. Value 1460 * follows the standard LED class meaning, e.g. LED_OFF, 1461 * LED_HALF, LED_FULL. 1462 */ 1463 int (*led_brightness_set)(struct phy_device *dev, 1464 u8 index, enum led_brightness value); 1465 1466 /** 1467 * @led_blink_set: Set a PHY LED blinking. Index indicates 1468 * which of the PHYs led should be configured to blink. Delays 1469 * are in milliseconds and if both are zero then a sensible 1470 * default should be chosen. The call should adjust the 1471 * timings in that case and if it can't match the values 1472 * specified exactly. 1473 */ 1474 int (*led_blink_set)(struct phy_device *dev, u8 index, 1475 unsigned long *delay_on, 1476 unsigned long *delay_off); 1477 /** 1478 * @led_hw_is_supported: Can the HW support the given rules. 1479 * @dev: PHY device which has the LED 1480 * @index: Which LED of the PHY device 1481 * @rules The core is interested in these rules 1482 * 1483 * Return 0 if yes, -EOPNOTSUPP if not, or an error code. 1484 */ 1485 int (*led_hw_is_supported)(struct phy_device *dev, u8 index, 1486 unsigned long rules); 1487 /** 1488 * @led_hw_control_set: Set the HW to control the LED 1489 * @dev: PHY device which has the LED 1490 * @index: Which LED of the PHY device 1491 * @rules The rules used to control the LED 1492 * 1493 * Returns 0, or a an error code. 1494 */ 1495 int (*led_hw_control_set)(struct phy_device *dev, u8 index, 1496 unsigned long rules); 1497 /** 1498 * @led_hw_control_get: Get how the HW is controlling the LED 1499 * @dev: PHY device which has the LED 1500 * @index: Which LED of the PHY device 1501 * @rules Pointer to the rules used to control the LED 1502 * 1503 * Set *@rules to how the HW is currently blinking. Returns 0 1504 * on success, or a error code if the current blinking cannot 1505 * be represented in rules, or some other error happens. 1506 */ 1507 int (*led_hw_control_get)(struct phy_device *dev, u8 index, 1508 unsigned long *rules); 1509 1510 /** 1511 * @led_polarity_set: Set the LED polarity modes 1512 * @dev: PHY device which has the LED 1513 * @index: Which LED of the PHY device 1514 * @modes: bitmap of LED polarity modes 1515 * 1516 * Configure LED with all the required polarity modes in @modes 1517 * to make it correctly turn ON or OFF. 1518 * 1519 * Returns 0, or an error code. 1520 */ 1521 int (*led_polarity_set)(struct phy_device *dev, int index, 1522 unsigned long modes); 1523 1524 /** 1525 * @get_next_update_time: Get the time until the next update event 1526 * @dev: PHY device 1527 * 1528 * Callback to determine the time (in jiffies) until the next 1529 * update event for the PHY state machine. Allows PHY drivers to 1530 * dynamically adjust polling intervals based on link state or other 1531 * conditions. 1532 * 1533 * Returns the time in jiffies until the next update event. 1534 */ 1535 unsigned int (*get_next_update_time)(struct phy_device *dev); 1536 1537 /** 1538 * @attach_mii_port: Attach the given MII port to the PHY device 1539 * @dev: PHY device to notify 1540 * @port: The port being added 1541 * 1542 * Called when an MII port that needs to be driven by the PHY is found. 1543 * 1544 * The port that is being passed may or may not be initialized. If it is 1545 * already initialized, it is by the generic port representation from 1546 * devicetree, which superseeds any strapping or vendor-specific 1547 * properties. 1548 * 1549 * If the port isn't initialized, the port->mediums and port->lanes 1550 * fields must be set, possibly according to strapping information. 1551 * 1552 * The PHY driver must set the port->interfaces field to indicate the 1553 * possible MII modes that this PHY can output on the port. 1554 * 1555 * Returns 0, or an error code. 1556 */ 1557 int (*attach_mii_port)(struct phy_device *dev, struct phy_port *port); 1558 1559 /** 1560 * @attach_mdi_port: Attach the given MII port to the PHY device 1561 * @dev: PHY device to notify 1562 * @port: The port being added 1563 * 1564 * Called when a port that needs to be driven by the PHY is found. The 1565 * number of time this will be called depends on phydev->max_n_ports, 1566 * which the driver can change in .probe(). 1567 * 1568 * The port that is being passed may or may not be initialized. If it is 1569 * already initialized, it is by the generic port representation from 1570 * devicetree, which superseeds any strapping or vendor-specific 1571 * properties. 1572 * 1573 * If the port isn't initialized, the port->mediums and port->lanes 1574 * fields must be set, possibly according to strapping information. 1575 * 1576 * Returns 0, or an error code. 1577 */ 1578 int (*attach_mdi_port)(struct phy_device *dev, struct phy_port *port); 1579 }; 1580 #define to_phy_driver(d) container_of_const(to_mdio_common_driver(d), \ 1581 struct phy_driver, mdiodrv) 1582 1583 #define PHY_ID_MATCH_EXTACT_MASK GENMASK(31, 0) 1584 #define PHY_ID_MATCH_MODEL_MASK GENMASK(31, 4) 1585 #define PHY_ID_MATCH_VENDOR_MASK GENMASK(31, 10) 1586 1587 #define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = PHY_ID_MATCH_EXTACT_MASK 1588 #define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = PHY_ID_MATCH_MODEL_MASK 1589 #define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = PHY_ID_MATCH_VENDOR_MASK 1590 1591 /** 1592 * phy_id_compare - compare @id1 with @id2 taking account of @mask 1593 * @id1: first PHY ID 1594 * @id2: second PHY ID 1595 * @mask: the PHY ID mask, set bits are significant in matching 1596 * 1597 * Return true if the bits from @id1 and @id2 specified by @mask match. 1598 * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask). 1599 */ 1600 static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask) 1601 { 1602 return !((id1 ^ id2) & mask); 1603 } 1604 1605 /** 1606 * phy_id_compare_vendor - compare @id with @vendor mask 1607 * @id: PHY ID 1608 * @vendor_mask: PHY Vendor mask 1609 * 1610 * Return: true if the bits from @id match @vendor using the 1611 * generic PHY Vendor mask. 1612 */ 1613 static inline bool phy_id_compare_vendor(u32 id, u32 vendor_mask) 1614 { 1615 return phy_id_compare(id, vendor_mask, PHY_ID_MATCH_VENDOR_MASK); 1616 } 1617 1618 /** 1619 * phy_id_compare_model - compare @id with @model mask 1620 * @id: PHY ID 1621 * @model_mask: PHY Model mask 1622 * 1623 * Return: true if the bits from @id match @model using the 1624 * generic PHY Model mask. 1625 */ 1626 static inline bool phy_id_compare_model(u32 id, u32 model_mask) 1627 { 1628 return phy_id_compare(id, model_mask, PHY_ID_MATCH_MODEL_MASK); 1629 } 1630 1631 /** 1632 * phydev_id_compare - compare @id with the PHY's Clause 22 ID 1633 * @phydev: the PHY device 1634 * @id: the PHY ID to be matched 1635 * 1636 * Compare the @phydev clause 22 ID with the provided @id and return true or 1637 * false depending whether it matches, using the bound driver mask. The 1638 * @phydev must be bound to a driver. 1639 */ 1640 static inline bool phydev_id_compare(struct phy_device *phydev, u32 id) 1641 { 1642 return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask); 1643 } 1644 1645 const char *phy_speed_to_str(int speed); 1646 const char *phy_duplex_to_str(unsigned int duplex); 1647 const char *phy_rate_matching_to_str(int rate_matching); 1648 1649 int phy_interface_num_ports(phy_interface_t interface); 1650 1651 /** 1652 * phy_is_started - Convenience function to check whether PHY is started 1653 * @phydev: The phy_device struct 1654 */ 1655 static inline bool phy_is_started(struct phy_device *phydev) 1656 { 1657 return phydev->state >= PHY_UP; 1658 } 1659 1660 /** 1661 * phy_driver_is_genphy - Convenience function to check whether PHY is driven 1662 * by one of the generic PHY drivers 1663 * @phydev: The phy_device struct 1664 * Return: true if PHY is driven by one of the genphy drivers 1665 */ 1666 static inline bool phy_driver_is_genphy(struct phy_device *phydev) 1667 { 1668 return phydev->is_genphy_driven; 1669 } 1670 1671 /** 1672 * phy_disable_eee_mode - Don't advertise an EEE mode. 1673 * @phydev: The phy_device struct 1674 * @link_mode: The EEE mode to be disabled 1675 */ 1676 static inline void phy_disable_eee_mode(struct phy_device *phydev, u32 link_mode) 1677 { 1678 WARN_ON(phy_is_started(phydev)); 1679 1680 linkmode_set_bit(link_mode, phydev->eee_disabled_modes); 1681 linkmode_clear_bit(link_mode, phydev->advertising_eee); 1682 } 1683 1684 /** 1685 * phy_can_wakeup() - indicate whether PHY has driver model wakeup capabilities 1686 * @phydev: The phy_device struct 1687 * 1688 * Returns: true/false depending on the PHY driver's device_set_wakeup_capable() 1689 * setting. 1690 */ 1691 static inline bool phy_can_wakeup(struct phy_device *phydev) 1692 { 1693 return device_can_wakeup(&phydev->mdio.dev); 1694 } 1695 1696 /** 1697 * phy_may_wakeup() - indicate whether PHY has wakeup enabled 1698 * @phydev: The phy_device struct 1699 * 1700 * Returns: true/false depending on the PHY driver's device_set_wakeup_enabled() 1701 * setting if using the driver model, otherwise the legacy determination. 1702 */ 1703 bool phy_may_wakeup(struct phy_device *phydev); 1704 1705 void phy_resolve_aneg_pause(struct phy_device *phydev); 1706 void phy_resolve_aneg_linkmode(struct phy_device *phydev); 1707 1708 /** 1709 * phy_read - Convenience function for reading a given PHY register 1710 * @phydev: the phy_device struct 1711 * @regnum: register number to read 1712 * 1713 * NOTE: MUST NOT be called from interrupt context, 1714 * because the bus read/write functions may wait for an interrupt 1715 * to conclude the operation. 1716 */ 1717 static inline int phy_read(struct phy_device *phydev, u32 regnum) 1718 { 1719 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum); 1720 } 1721 1722 #define phy_read_poll_timeout(phydev, regnum, val, cond, sleep_us, \ 1723 timeout_us, sleep_before_read) \ 1724 ({ \ 1725 int __ret, __val; \ 1726 __ret = read_poll_timeout(__val = phy_read, val, \ 1727 __val < 0 || (cond), \ 1728 sleep_us, timeout_us, sleep_before_read, phydev, regnum); \ 1729 if (__val < 0) \ 1730 __ret = __val; \ 1731 if (__ret) \ 1732 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1733 __ret; \ 1734 }) 1735 1736 /** 1737 * __phy_read - convenience function for reading a given PHY register 1738 * @phydev: the phy_device struct 1739 * @regnum: register number to read 1740 * 1741 * The caller must have taken the MDIO bus lock. 1742 */ 1743 static inline int __phy_read(struct phy_device *phydev, u32 regnum) 1744 { 1745 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum); 1746 } 1747 1748 /** 1749 * phy_write - Convenience function for writing a given PHY register 1750 * @phydev: the phy_device struct 1751 * @regnum: register number to write 1752 * @val: value to write to @regnum 1753 * 1754 * NOTE: MUST NOT be called from interrupt context, 1755 * because the bus read/write functions may wait for an interrupt 1756 * to conclude the operation. 1757 */ 1758 static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val) 1759 { 1760 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val); 1761 } 1762 1763 /** 1764 * __phy_write - Convenience function for writing a given PHY register 1765 * @phydev: the phy_device struct 1766 * @regnum: register number to write 1767 * @val: value to write to @regnum 1768 * 1769 * The caller must have taken the MDIO bus lock. 1770 */ 1771 static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val) 1772 { 1773 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, 1774 val); 1775 } 1776 1777 /** 1778 * __phy_modify_changed() - Convenience function for modifying a PHY register 1779 * @phydev: a pointer to a &struct phy_device 1780 * @regnum: register number 1781 * @mask: bit mask of bits to clear 1782 * @set: bit mask of bits to set 1783 * 1784 * Unlocked helper function which allows a PHY register to be modified as 1785 * new register value = (old register value & ~mask) | set 1786 * 1787 * Returns negative errno, 0 if there was no change, and 1 in case of change 1788 */ 1789 static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum, 1790 u16 mask, u16 set) 1791 { 1792 return __mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, 1793 regnum, mask, set); 1794 } 1795 1796 /* 1797 * phy_read_mmd - Convenience function for reading a register 1798 * from an MMD on a given PHY. 1799 */ 1800 int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum); 1801 1802 /** 1803 * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a 1804 * condition is met or a timeout occurs 1805 * 1806 * @phydev: The phy_device struct 1807 * @devaddr: The MMD to read from 1808 * @regnum: The register on the MMD to read 1809 * @val: Variable to read the register into 1810 * @cond: Break condition (usually involving @val) 1811 * @sleep_us: Maximum time to sleep between reads in us (0 tight-loops). Please 1812 * read usleep_range() function description for details and 1813 * limitations. 1814 * @timeout_us: Timeout in us, 0 means never timeout 1815 * @sleep_before_read: if it is true, sleep @sleep_us before read. 1816 * 1817 * Returns: 0 on success and -ETIMEDOUT upon a timeout. In either 1818 * case, the last read value at @args is stored in @val. Must not 1819 * be called from atomic context if sleep_us or timeout_us are used. 1820 */ 1821 #define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \ 1822 sleep_us, timeout_us, sleep_before_read) \ 1823 ({ \ 1824 int __ret, __val; \ 1825 __ret = read_poll_timeout(__val = phy_read_mmd, val, \ 1826 __val < 0 || (cond), \ 1827 sleep_us, timeout_us, sleep_before_read, \ 1828 phydev, devaddr, regnum); \ 1829 if (__val < 0) \ 1830 __ret = __val; \ 1831 if (__ret) \ 1832 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \ 1833 __ret; \ 1834 }) 1835 1836 /* 1837 * __phy_read_mmd - Convenience function for reading a register 1838 * from an MMD on a given PHY. 1839 */ 1840 int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum); 1841 1842 /* 1843 * phy_write_mmd - Convenience function for writing a register 1844 * on an MMD on a given PHY. 1845 */ 1846 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); 1847 1848 /* 1849 * __phy_write_mmd - Convenience function for writing a register 1850 * on an MMD on a given PHY. 1851 */ 1852 int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); 1853 1854 int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, 1855 u16 set); 1856 int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, 1857 u16 set); 1858 int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); 1859 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); 1860 1861 int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 1862 u16 mask, u16 set); 1863 int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum, 1864 u16 mask, u16 set); 1865 int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1866 u16 mask, u16 set); 1867 int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum, 1868 u16 mask, u16 set); 1869 1870 /** 1871 * __phy_set_bits - Convenience function for setting bits in a PHY register 1872 * @phydev: the phy_device struct 1873 * @regnum: register number to write 1874 * @val: bits to set 1875 * 1876 * The caller must have taken the MDIO bus lock. 1877 */ 1878 static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) 1879 { 1880 return __phy_modify(phydev, regnum, 0, val); 1881 } 1882 1883 /** 1884 * __phy_clear_bits - Convenience function for clearing bits in a PHY register 1885 * @phydev: the phy_device struct 1886 * @regnum: register number to write 1887 * @val: bits to clear 1888 * 1889 * The caller must have taken the MDIO bus lock. 1890 */ 1891 static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum, 1892 u16 val) 1893 { 1894 return __phy_modify(phydev, regnum, val, 0); 1895 } 1896 1897 /** 1898 * phy_set_bits - Convenience function for setting bits in a PHY register 1899 * @phydev: the phy_device struct 1900 * @regnum: register number to write 1901 * @val: bits to set 1902 */ 1903 static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) 1904 { 1905 return phy_modify(phydev, regnum, 0, val); 1906 } 1907 1908 /** 1909 * phy_clear_bits - Convenience function for clearing bits in a PHY register 1910 * @phydev: the phy_device struct 1911 * @regnum: register number to write 1912 * @val: bits to clear 1913 */ 1914 static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val) 1915 { 1916 return phy_modify(phydev, regnum, val, 0); 1917 } 1918 1919 /** 1920 * __phy_set_bits_mmd - Convenience function for setting bits in a register 1921 * on MMD 1922 * @phydev: the phy_device struct 1923 * @devad: the MMD containing register to modify 1924 * @regnum: register number to modify 1925 * @val: bits to set 1926 * 1927 * The caller must have taken the MDIO bus lock. 1928 */ 1929 static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad, 1930 u32 regnum, u16 val) 1931 { 1932 return __phy_modify_mmd(phydev, devad, regnum, 0, val); 1933 } 1934 1935 /** 1936 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register 1937 * on MMD 1938 * @phydev: the phy_device struct 1939 * @devad: the MMD containing register to modify 1940 * @regnum: register number to modify 1941 * @val: bits to clear 1942 * 1943 * The caller must have taken the MDIO bus lock. 1944 */ 1945 static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad, 1946 u32 regnum, u16 val) 1947 { 1948 return __phy_modify_mmd(phydev, devad, regnum, val, 0); 1949 } 1950 1951 /** 1952 * phy_set_bits_mmd - Convenience function for setting bits in a register 1953 * on MMD 1954 * @phydev: the phy_device struct 1955 * @devad: the MMD containing register to modify 1956 * @regnum: register number to modify 1957 * @val: bits to set 1958 */ 1959 static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, 1960 u32 regnum, u16 val) 1961 { 1962 return phy_modify_mmd(phydev, devad, regnum, 0, val); 1963 } 1964 1965 /** 1966 * phy_clear_bits_mmd - Convenience function for clearing bits in a register 1967 * on MMD 1968 * @phydev: the phy_device struct 1969 * @devad: the MMD containing register to modify 1970 * @regnum: register number to modify 1971 * @val: bits to clear 1972 */ 1973 static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, 1974 u32 regnum, u16 val) 1975 { 1976 return phy_modify_mmd(phydev, devad, regnum, val, 0); 1977 } 1978 1979 /** 1980 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq 1981 * @phydev: the phy_device struct 1982 * 1983 * NOTE: must be kept in sync with addition/removal of PHY_POLL and 1984 * PHY_MAC_INTERRUPT 1985 */ 1986 static inline bool phy_interrupt_is_valid(struct phy_device *phydev) 1987 { 1988 return phydev->irq != PHY_POLL && phydev->irq != PHY_MAC_INTERRUPT; 1989 } 1990 1991 /** 1992 * phy_polling_mode - Convenience function for testing whether polling is 1993 * used to detect PHY status changes 1994 * @phydev: the phy_device struct 1995 */ 1996 static inline bool phy_polling_mode(struct phy_device *phydev) 1997 { 1998 if (phydev->state == PHY_CABLETEST) 1999 if (phydev->drv->flags & PHY_POLL_CABLE_TEST) 2000 return true; 2001 2002 if (phydev->drv->update_stats) 2003 return true; 2004 2005 return phydev->irq == PHY_POLL; 2006 } 2007 2008 /** 2009 * phy_has_hwtstamp - Tests whether a PHY time stamp configuration. 2010 * @phydev: the phy_device struct 2011 */ 2012 static inline bool phy_has_hwtstamp(struct phy_device *phydev) 2013 { 2014 return phydev && phydev->mii_ts && phydev->mii_ts->hwtstamp_set; 2015 } 2016 2017 /** 2018 * phy_has_rxtstamp - Tests whether a PHY supports receive time stamping. 2019 * @phydev: the phy_device struct 2020 */ 2021 static inline bool phy_has_rxtstamp(struct phy_device *phydev) 2022 { 2023 return phydev && phydev->mii_ts && phydev->mii_ts->rxtstamp; 2024 } 2025 2026 /** 2027 * phy_has_tsinfo - Tests whether a PHY reports time stamping and/or 2028 * PTP hardware clock capabilities. 2029 * @phydev: the phy_device struct 2030 */ 2031 static inline bool phy_has_tsinfo(struct phy_device *phydev) 2032 { 2033 return phydev && phydev->mii_ts && phydev->mii_ts->ts_info; 2034 } 2035 2036 /** 2037 * phy_has_txtstamp - Tests whether a PHY supports transmit time stamping. 2038 * @phydev: the phy_device struct 2039 */ 2040 static inline bool phy_has_txtstamp(struct phy_device *phydev) 2041 { 2042 return phydev && phydev->mii_ts && phydev->mii_ts->txtstamp; 2043 } 2044 2045 static inline int phy_hwtstamp(struct phy_device *phydev, 2046 struct kernel_hwtstamp_config *cfg, 2047 struct netlink_ext_ack *extack) 2048 { 2049 return phydev->mii_ts->hwtstamp_set(phydev->mii_ts, cfg, extack); 2050 } 2051 2052 static inline bool phy_rxtstamp(struct phy_device *phydev, struct sk_buff *skb, 2053 int type) 2054 { 2055 return phydev->mii_ts->rxtstamp(phydev->mii_ts, skb, type); 2056 } 2057 2058 static inline int phy_ts_info(struct phy_device *phydev, 2059 struct kernel_ethtool_ts_info *tsinfo) 2060 { 2061 return phydev->mii_ts->ts_info(phydev->mii_ts, tsinfo); 2062 } 2063 2064 static inline void phy_txtstamp(struct phy_device *phydev, struct sk_buff *skb, 2065 int type) 2066 { 2067 phydev->mii_ts->txtstamp(phydev->mii_ts, skb, type); 2068 } 2069 2070 /** 2071 * phy_is_default_hwtstamp - Is the PHY hwtstamp the default timestamp 2072 * @phydev: Pointer to phy_device 2073 * 2074 * This is used to get default timestamping device taking into account 2075 * the new API choice, which is selecting the timestamping from MAC by 2076 * default if the phydev does not have default_timestamp flag enabled. 2077 * 2078 * Return: True if phy is the default hw timestamp, false otherwise. 2079 */ 2080 static inline bool phy_is_default_hwtstamp(struct phy_device *phydev) 2081 { 2082 return phy_has_hwtstamp(phydev) && phydev->default_timestamp; 2083 } 2084 2085 /** 2086 * phy_on_sfp - Convenience function for testing if a PHY is on an SFP module 2087 * @phydev: the phy_device struct 2088 */ 2089 static inline bool phy_on_sfp(struct phy_device *phydev) 2090 { 2091 return phydev->is_on_sfp_module; 2092 } 2093 2094 /** 2095 * phy_interface_mode_is_rgmii - Convenience function for testing if a 2096 * PHY interface mode is RGMII (all variants) 2097 * @mode: the &phy_interface_t enum 2098 */ 2099 static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode) 2100 { 2101 return mode >= PHY_INTERFACE_MODE_RGMII && 2102 mode <= PHY_INTERFACE_MODE_RGMII_TXID; 2103 }; 2104 2105 /** 2106 * phy_interface_mode_is_8023z() - does the PHY interface mode use 802.3z 2107 * negotiation 2108 * @mode: one of &enum phy_interface_t 2109 * 2110 * Returns true if the PHY interface mode uses the 16-bit negotiation 2111 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding) 2112 */ 2113 static inline bool phy_interface_mode_is_8023z(phy_interface_t mode) 2114 { 2115 return mode == PHY_INTERFACE_MODE_1000BASEX || 2116 mode == PHY_INTERFACE_MODE_2500BASEX; 2117 } 2118 2119 /** 2120 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 2121 * is RGMII (all variants) 2122 * @phydev: the phy_device struct 2123 */ 2124 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 2125 { 2126 return phy_interface_mode_is_rgmii(phydev->interface); 2127 }; 2128 2129 /** 2130 * phy_is_pseudo_fixed_link - Convenience function for testing if this 2131 * PHY is the CPU port facing side of an Ethernet switch, or similar. 2132 * @phydev: the phy_device struct 2133 */ 2134 static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev) 2135 { 2136 return phydev->is_pseudo_fixed_link; 2137 } 2138 2139 phy_interface_t phy_fix_phy_mode_for_mac_delays(phy_interface_t interface, 2140 bool mac_txid, bool mac_rxid); 2141 2142 int phy_save_page(struct phy_device *phydev); 2143 int phy_select_page(struct phy_device *phydev, int page); 2144 int phy_restore_page(struct phy_device *phydev, int oldpage, int ret); 2145 int phy_read_paged(struct phy_device *phydev, int page, u32 regnum); 2146 int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val); 2147 int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum, 2148 u16 mask, u16 set); 2149 int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum, 2150 u16 mask, u16 set); 2151 2152 struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id, 2153 bool is_c45, 2154 struct phy_c45_device_ids *c45_ids); 2155 int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id); 2156 struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode); 2157 struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode); 2158 struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode); 2159 struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45); 2160 int phy_device_register(struct phy_device *phy); 2161 void phy_device_free(struct phy_device *phydev); 2162 void phy_device_remove(struct phy_device *phydev); 2163 int phy_get_c45_ids(struct phy_device *phydev); 2164 int phy_init_hw(struct phy_device *phydev); 2165 int phy_suspend(struct phy_device *phydev); 2166 int phy_resume(struct phy_device *phydev); 2167 int __phy_resume(struct phy_device *phydev); 2168 int phy_loopback(struct phy_device *phydev, bool enable, int speed); 2169 struct phy_device *phy_find_next(struct mii_bus *bus, struct phy_device *pos); 2170 int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, 2171 u32 flags, phy_interface_t interface); 2172 int phy_connect_direct(struct net_device *dev, struct phy_device *phydev, 2173 void (*handler)(struct net_device *), 2174 phy_interface_t interface); 2175 struct phy_device *phy_connect(struct net_device *dev, const char *bus_id, 2176 void (*handler)(struct net_device *), 2177 phy_interface_t interface); 2178 void phy_disconnect(struct phy_device *phydev); 2179 void phy_detach(struct phy_device *phydev); 2180 void phy_start(struct phy_device *phydev); 2181 void phy_stop(struct phy_device *phydev); 2182 int phy_config_aneg(struct phy_device *phydev); 2183 int _phy_start_aneg(struct phy_device *phydev); 2184 int phy_start_aneg(struct phy_device *phydev); 2185 int phy_aneg_done(struct phy_device *phydev); 2186 unsigned int phy_inband_caps(struct phy_device *phydev, 2187 phy_interface_t interface); 2188 int phy_config_inband(struct phy_device *phydev, unsigned int modes); 2189 int phy_speed_down(struct phy_device *phydev, bool sync); 2190 int phy_speed_up(struct phy_device *phydev); 2191 bool phy_check_valid(int speed, int duplex, unsigned long *features); 2192 2193 int phy_restart_aneg(struct phy_device *phydev); 2194 int phy_reset_after_clk_enable(struct phy_device *phydev); 2195 2196 static inline struct phy_device *phy_find_first(struct mii_bus *bus) 2197 { 2198 return phy_find_next(bus, NULL); 2199 } 2200 2201 #define mdiobus_for_each_phy(_bus, _phydev) \ 2202 for (_phydev = phy_find_first(_bus); _phydev; \ 2203 _phydev = phy_find_next(_bus, _phydev)) 2204 2205 #if IS_ENABLED(CONFIG_PHYLIB) 2206 int phy_start_cable_test(struct phy_device *phydev, 2207 struct netlink_ext_ack *extack); 2208 int phy_start_cable_test_tdr(struct phy_device *phydev, 2209 struct netlink_ext_ack *extack, 2210 const struct phy_tdr_config *config); 2211 #else 2212 static inline 2213 int phy_start_cable_test(struct phy_device *phydev, 2214 struct netlink_ext_ack *extack) 2215 { 2216 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support"); 2217 return -EOPNOTSUPP; 2218 } 2219 static inline 2220 int phy_start_cable_test_tdr(struct phy_device *phydev, 2221 struct netlink_ext_ack *extack, 2222 const struct phy_tdr_config *config) 2223 { 2224 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support"); 2225 return -EOPNOTSUPP; 2226 } 2227 #endif 2228 2229 static inline void phy_device_reset(struct phy_device *phydev, int value) 2230 { 2231 mdio_device_reset(&phydev->mdio, value); 2232 } 2233 2234 #define phydev_err(_phydev, format, args...) \ 2235 dev_err(&_phydev->mdio.dev, format, ##args) 2236 2237 #define phydev_err_probe(_phydev, err, format, args...) \ 2238 dev_err_probe(&_phydev->mdio.dev, err, format, ##args) 2239 2240 #define phydev_info(_phydev, format, args...) \ 2241 dev_info(&_phydev->mdio.dev, format, ##args) 2242 2243 #define phydev_warn(_phydev, format, args...) \ 2244 dev_warn(&_phydev->mdio.dev, format, ##args) 2245 2246 #define phydev_dbg(_phydev, format, args...) \ 2247 dev_dbg(&_phydev->mdio.dev, format, ##args) 2248 2249 static inline const char *phydev_name(const struct phy_device *phydev) 2250 { 2251 return dev_name(&phydev->mdio.dev); 2252 } 2253 2254 static inline void phy_lock_mdio_bus(struct phy_device *phydev) 2255 { 2256 mutex_lock(&phydev->mdio.bus->mdio_lock); 2257 } 2258 2259 static inline void phy_unlock_mdio_bus(struct phy_device *phydev) 2260 { 2261 mutex_unlock(&phydev->mdio.bus->mdio_lock); 2262 } 2263 2264 void phy_attached_print(struct phy_device *phydev, const char *fmt, ...) 2265 __printf(2, 3); 2266 char *phy_attached_info_irq(struct phy_device *phydev) 2267 __malloc; 2268 void phy_attached_info(struct phy_device *phydev); 2269 2270 int genphy_match_phy_device(struct phy_device *phydev, 2271 const struct phy_driver *phydrv); 2272 2273 /* Clause 22 PHY */ 2274 int genphy_read_abilities(struct phy_device *phydev); 2275 int genphy_setup_forced(struct phy_device *phydev); 2276 int genphy_restart_aneg(struct phy_device *phydev); 2277 int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart); 2278 int __genphy_config_aneg(struct phy_device *phydev, bool changed); 2279 int genphy_aneg_done(struct phy_device *phydev); 2280 int genphy_update_link(struct phy_device *phydev); 2281 int genphy_read_lpa(struct phy_device *phydev); 2282 int genphy_read_status_fixed(struct phy_device *phydev); 2283 int genphy_read_status(struct phy_device *phydev); 2284 int genphy_read_master_slave(struct phy_device *phydev); 2285 int genphy_suspend(struct phy_device *phydev); 2286 int genphy_resume(struct phy_device *phydev); 2287 int genphy_loopback(struct phy_device *phydev, bool enable, int speed); 2288 int genphy_soft_reset(struct phy_device *phydev); 2289 irqreturn_t genphy_handle_interrupt_no_ack(struct phy_device *phydev); 2290 2291 static inline int genphy_config_aneg(struct phy_device *phydev) 2292 { 2293 return __genphy_config_aneg(phydev, false); 2294 } 2295 2296 static inline int genphy_no_config_intr(struct phy_device *phydev) 2297 { 2298 return 0; 2299 } 2300 int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, 2301 u16 regnum); 2302 int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum, 2303 u16 regnum, u16 val); 2304 2305 /* Clause 37 */ 2306 int genphy_c37_config_aneg(struct phy_device *phydev); 2307 int genphy_c37_read_status(struct phy_device *phydev, bool *changed); 2308 2309 /* Clause 45 PHY */ 2310 int genphy_c45_restart_aneg(struct phy_device *phydev); 2311 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart); 2312 int genphy_c45_aneg_done(struct phy_device *phydev); 2313 int genphy_c45_read_link(struct phy_device *phydev); 2314 int genphy_c45_read_lpa(struct phy_device *phydev); 2315 int genphy_c45_read_pma(struct phy_device *phydev); 2316 int genphy_c45_pma_setup_forced(struct phy_device *phydev); 2317 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev); 2318 int genphy_c45_an_config_aneg(struct phy_device *phydev); 2319 int genphy_c45_an_disable_aneg(struct phy_device *phydev); 2320 int genphy_c45_read_mdix(struct phy_device *phydev); 2321 int genphy_c45_pma_read_abilities(struct phy_device *phydev); 2322 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev); 2323 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev); 2324 int genphy_c45_read_eee_abilities(struct phy_device *phydev); 2325 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev); 2326 int genphy_c45_read_status(struct phy_device *phydev); 2327 int genphy_c45_baset1_read_status(struct phy_device *phydev); 2328 int genphy_c45_config_aneg(struct phy_device *phydev); 2329 int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed); 2330 int genphy_c45_pma_resume(struct phy_device *phydev); 2331 int genphy_c45_pma_suspend(struct phy_device *phydev); 2332 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable); 2333 int genphy_c45_plca_get_cfg(struct phy_device *phydev, 2334 struct phy_plca_cfg *plca_cfg); 2335 int genphy_c45_plca_set_cfg(struct phy_device *phydev, 2336 const struct phy_plca_cfg *plca_cfg); 2337 int genphy_c45_plca_get_status(struct phy_device *phydev, 2338 struct phy_plca_status *plca_st); 2339 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp); 2340 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, 2341 struct ethtool_keee *data); 2342 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, 2343 struct ethtool_keee *data); 2344 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev); 2345 int genphy_c45_oatc14_cable_test_start(struct phy_device *phydev); 2346 int genphy_c45_oatc14_cable_test_get_status(struct phy_device *phydev, 2347 bool *finished); 2348 int genphy_c45_oatc14_get_sqi_max(struct phy_device *phydev); 2349 int genphy_c45_oatc14_get_sqi(struct phy_device *phydev); 2350 2351 /* The gen10g_* functions are the old Clause 45 stub */ 2352 int gen10g_config_aneg(struct phy_device *phydev); 2353 2354 static inline int phy_read_status(struct phy_device *phydev) 2355 { 2356 if (!phydev->drv) 2357 return -EIO; 2358 2359 if (phydev->drv->read_status) 2360 return phydev->drv->read_status(phydev); 2361 else 2362 return genphy_read_status(phydev); 2363 } 2364 2365 void phy_drivers_unregister(struct phy_driver *drv, int n); 2366 int phy_drivers_register(struct phy_driver *new_driver, int n, 2367 struct module *owner); 2368 void phy_error(struct phy_device *phydev); 2369 void phy_state_machine(struct work_struct *work); 2370 void phy_trigger_machine(struct phy_device *phydev); 2371 void phy_mac_interrupt(struct phy_device *phydev); 2372 void phy_start_machine(struct phy_device *phydev); 2373 void phy_stop_machine(struct phy_device *phydev); 2374 2375 void phy_ethtool_ksettings_get(struct phy_device *phydev, 2376 struct ethtool_link_ksettings *cmd); 2377 int phy_ethtool_ksettings_set(struct phy_device *phydev, 2378 const struct ethtool_link_ksettings *cmd); 2379 int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); 2380 int phy_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); 2381 int phy_do_ioctl_running(struct net_device *dev, struct ifreq *ifr, int cmd); 2382 int phy_disable_interrupts(struct phy_device *phydev); 2383 void phy_request_interrupt(struct phy_device *phydev); 2384 void phy_free_interrupt(struct phy_device *phydev); 2385 void phy_print_status(struct phy_device *phydev); 2386 int phy_get_rate_matching(struct phy_device *phydev, 2387 phy_interface_t iface); 2388 void phy_set_max_speed(struct phy_device *phydev, u32 max_speed); 2389 void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode); 2390 void phy_advertise_supported(struct phy_device *phydev); 2391 void phy_advertise_eee_all(struct phy_device *phydev); 2392 void phy_support_sym_pause(struct phy_device *phydev); 2393 void phy_support_asym_pause(struct phy_device *phydev); 2394 void phy_support_eee(struct phy_device *phydev); 2395 void phy_disable_eee(struct phy_device *phydev); 2396 void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx, 2397 bool autoneg); 2398 void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx); 2399 bool phy_validate_pause(struct phy_device *phydev, 2400 struct ethtool_pauseparam *pp); 2401 void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause); 2402 2403 s32 phy_get_internal_delay(struct phy_device *phydev, const int *delay_values, 2404 int size, bool is_rx); 2405 2406 int phy_get_tx_amplitude_gain(struct phy_device *phydev, struct device *dev, 2407 enum ethtool_link_mode_bit_indices linkmode, 2408 u32 *val); 2409 2410 int phy_get_mac_termination(struct phy_device *phydev, struct device *dev, 2411 u32 *val); 2412 2413 void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv, 2414 bool *tx_pause, bool *rx_pause); 2415 2416 int phy_register_fixup_for_id(const char *bus_id, 2417 int (*run)(struct phy_device *)); 2418 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask, 2419 int (*run)(struct phy_device *)); 2420 2421 int phy_eee_tx_clock_stop_capable(struct phy_device *phydev); 2422 int phy_eee_rx_clock_stop(struct phy_device *phydev, bool clk_stop_enable); 2423 int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable); 2424 int phy_get_eee_err(struct phy_device *phydev); 2425 int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_keee *data); 2426 int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_keee *data); 2427 int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol); 2428 void phy_ethtool_get_wol(struct phy_device *phydev, 2429 struct ethtool_wolinfo *wol); 2430 int phy_ethtool_get_link_ksettings(struct net_device *ndev, 2431 struct ethtool_link_ksettings *cmd); 2432 int phy_ethtool_set_link_ksettings(struct net_device *ndev, 2433 const struct ethtool_link_ksettings *cmd); 2434 int phy_ethtool_nway_reset(struct net_device *ndev); 2435 2436 int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data); 2437 int phy_ethtool_get_sset_count(struct phy_device *phydev); 2438 int phy_ethtool_get_stats(struct phy_device *phydev, 2439 struct ethtool_stats *stats, u64 *data); 2440 2441 void __phy_ethtool_get_phy_stats(struct phy_device *phydev, 2442 struct ethtool_eth_phy_stats *phy_stats, 2443 struct ethtool_phy_stats *phydev_stats); 2444 void __phy_ethtool_get_link_ext_stats(struct phy_device *phydev, 2445 struct ethtool_link_ext_stats *link_stats); 2446 2447 int phy_ethtool_get_plca_cfg(struct phy_device *phydev, 2448 struct phy_plca_cfg *plca_cfg); 2449 int phy_ethtool_set_plca_cfg(struct phy_device *phydev, 2450 const struct phy_plca_cfg *plca_cfg, 2451 struct netlink_ext_ack *extack); 2452 int phy_ethtool_get_plca_status(struct phy_device *phydev, 2453 struct phy_plca_status *plca_st); 2454 2455 int __phy_hwtstamp_get(struct phy_device *phydev, 2456 struct kernel_hwtstamp_config *config); 2457 int __phy_hwtstamp_set(struct phy_device *phydev, 2458 struct kernel_hwtstamp_config *config, 2459 struct netlink_ext_ack *extack); 2460 2461 struct phy_port *phy_get_sfp_port(struct phy_device *phydev); 2462 2463 /** 2464 * phy_module_driver() - Helper macro for registering PHY drivers 2465 * @__phy_drivers: array of PHY drivers to register 2466 * @__count: Numbers of members in array 2467 * 2468 * Helper macro for PHY drivers which do not do anything special in module 2469 * init/exit. Each module may only use this macro once, and calling it 2470 * replaces module_init() and module_exit(). 2471 */ 2472 #define phy_module_driver(__phy_drivers, __count) \ 2473 static int __init phy_module_init(void) \ 2474 { \ 2475 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \ 2476 } \ 2477 module_init(phy_module_init); \ 2478 static void __exit phy_module_exit(void) \ 2479 { \ 2480 phy_drivers_unregister(__phy_drivers, __count); \ 2481 } \ 2482 module_exit(phy_module_exit) 2483 2484 #define module_phy_driver(__phy_drivers) \ 2485 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers)) 2486 2487 #endif /* __PHY_H */ 2488