1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_MCHBAR_REGS_H_ 7 #define _XE_MCHBAR_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 /* 12 * MCHBAR mirror. 13 * 14 * This mirrors the MCHBAR MMIO space whose location is determined by 15 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 16 * every way. 17 */ 18 19 #define MCHBAR_MIRROR_BASE_SNB 0x140000 20 21 #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930) 22 #define PKG_TDP GENMASK_ULL(14, 0) 23 #define PKG_MIN_PWR GENMASK_ULL(30, 16) 24 #define PKG_MAX_PWR GENMASK_ULL(46, 32) 25 #define PKG_MAX_WIN GENMASK_ULL(54, 48) 26 #define PKG_MAX_WIN_X GENMASK_ULL(54, 53) 27 #define PKG_MAX_WIN_Y GENMASK_ULL(52, 48) 28 29 30 #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938) 31 #define PKG_PWR_UNIT REG_GENMASK(3, 0) 32 #define PKG_ENERGY_UNIT REG_GENMASK(12, 8) 33 #define PKG_TIME_UNIT REG_GENMASK(19, 16) 34 35 #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c) 36 37 #define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978) 38 #define TEMP_MASK REG_GENMASK(7, 0) 39 40 #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0) 41 #define PWR_LIM_VAL REG_GENMASK(14, 0) 42 #define PWR_LIM_EN REG_BIT(15) 43 #define PWR_LIM REG_GENMASK(15, 0) 44 #define PWR_LIM_TIME REG_GENMASK(23, 17) 45 #define PWR_LIM_TIME_X REG_GENMASK(23, 22) 46 #define PWR_LIM_TIME_Y REG_GENMASK(21, 17) 47 48 #endif /* _XE_MCHBAR_REGS_H_ */ 49