1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_PPS_REGS_H__ 7 #define __INTEL_PPS_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 /* Panel power sequencing */ 12 #define PPS_BASE 0x61200 13 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 14 #define PCH_PPS_BASE 0xC7200 15 16 #define _MMIO_PPS(display, pps_idx, reg) \ 17 _MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100) 18 19 #define _PP_STATUS 0x61200 20 #define PP_STATUS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_STATUS) 21 #define PP_ON REG_BIT(31) 22 /* 23 * Indicates that all dependencies of the panel are on: 24 * 25 * - PLL enabled 26 * - pipe enabled 27 * - LVDS/DVOB/DVOC on 28 */ 29 #define PP_READY REG_BIT(30) 30 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 31 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 32 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 33 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 34 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 35 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 36 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 37 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 38 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 39 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 40 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 41 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 42 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 43 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 44 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 45 46 #define _PP_CONTROL 0x61204 47 #define PP_CONTROL(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_CONTROL) 48 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 49 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 50 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 51 #define EDP_FORCE_VDD REG_BIT(3) 52 #define EDP_BLC_ENABLE REG_BIT(2) 53 #define PANEL_POWER_RESET REG_BIT(1) 54 #define PANEL_POWER_ON REG_BIT(0) 55 56 #define _PP_ON_DELAYS 0x61208 57 #define PP_ON_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_ON_DELAYS) 58 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 59 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 60 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 61 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 62 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 63 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 64 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 65 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 66 67 #define _PP_OFF_DELAYS 0x6120C 68 #define PP_OFF_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_OFF_DELAYS) 69 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 70 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 71 72 #define _PP_DIVISOR 0x61210 73 #define PP_DIVISOR(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_DIVISOR) 74 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 75 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 76 77 #endif /* __INTEL_PPS_REGS_H__ */ 78