1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2012 Linaro Ltd.
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/export.h>
9 #include <linux/io.h>
10 #include <linux/slab.h>
11 #include <linux/err.h>
12 #include "clk.h"
13
14 /**
15 * struct clk_pfd - IMX PFD clock
16 * @hw: clock source
17 * @reg: PFD register address
18 * @idx: the index of PFD encoded in the register
19 *
20 * PFD clock found on i.MX6 series. Each register for PFD has 4 clk_pfd
21 * data encoded, and member idx is used to specify the one. And each
22 * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
23 */
24 struct clk_pfd {
25 struct clk_hw hw;
26 void __iomem *reg;
27 u8 idx;
28 };
29
30 #define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw)
31
32 #define SET 0x4
33 #define CLR 0x8
34 #define OTG 0xc
35
clk_pfd_enable(struct clk_hw * hw)36 static int clk_pfd_enable(struct clk_hw *hw)
37 {
38 struct clk_pfd *pfd = to_clk_pfd(hw);
39
40 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
41
42 return 0;
43 }
44
clk_pfd_disable(struct clk_hw * hw)45 static void clk_pfd_disable(struct clk_hw *hw)
46 {
47 struct clk_pfd *pfd = to_clk_pfd(hw);
48
49 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
50 }
51
clk_pfd_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)52 static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
53 unsigned long parent_rate)
54 {
55 struct clk_pfd *pfd = to_clk_pfd(hw);
56 u64 tmp = parent_rate;
57 u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
58
59 tmp *= 18;
60 do_div(tmp, frac);
61
62 return tmp;
63 }
64
clk_pfd_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)65 static int clk_pfd_determine_rate(struct clk_hw *hw,
66 struct clk_rate_request *req)
67 {
68 u64 tmp = req->best_parent_rate;
69 u8 frac;
70
71 tmp = tmp * 18 + req->rate / 2;
72 do_div(tmp, req->rate);
73 frac = tmp;
74 if (frac < 12)
75 frac = 12;
76 else if (frac > 35)
77 frac = 35;
78 tmp = req->best_parent_rate;
79 tmp *= 18;
80 do_div(tmp, frac);
81
82 req->rate = tmp;
83
84 return 0;
85 }
86
clk_pfd_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)87 static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
88 unsigned long parent_rate)
89 {
90 struct clk_pfd *pfd = to_clk_pfd(hw);
91 u64 tmp = parent_rate;
92 u8 frac;
93
94 tmp = tmp * 18 + rate / 2;
95 do_div(tmp, rate);
96 frac = tmp;
97 if (frac < 12)
98 frac = 12;
99 else if (frac > 35)
100 frac = 35;
101
102 writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
103 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
104
105 return 0;
106 }
107
clk_pfd_is_enabled(struct clk_hw * hw)108 static int clk_pfd_is_enabled(struct clk_hw *hw)
109 {
110 struct clk_pfd *pfd = to_clk_pfd(hw);
111
112 if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
113 return 0;
114
115 return 1;
116 }
117
118 static const struct clk_ops clk_pfd_ops = {
119 .enable = clk_pfd_enable,
120 .disable = clk_pfd_disable,
121 .recalc_rate = clk_pfd_recalc_rate,
122 .determine_rate = clk_pfd_determine_rate,
123 .set_rate = clk_pfd_set_rate,
124 .is_enabled = clk_pfd_is_enabled,
125 };
126
imx_clk_hw_pfd(const char * name,const char * parent_name,void __iomem * reg,u8 idx)127 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
128 void __iomem *reg, u8 idx)
129 {
130 struct clk_pfd *pfd;
131 struct clk_hw *hw;
132 struct clk_init_data init;
133 int ret;
134
135 pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
136 if (!pfd)
137 return ERR_PTR(-ENOMEM);
138
139 pfd->reg = reg;
140 pfd->idx = idx;
141
142 init.name = name;
143 init.ops = &clk_pfd_ops;
144 init.flags = 0;
145 init.parent_names = &parent_name;
146 init.num_parents = 1;
147
148 pfd->hw.init = &init;
149 hw = &pfd->hw;
150
151 ret = clk_hw_register(NULL, hw);
152 if (ret) {
153 kfree(pfd);
154 return ERR_PTR(ret);
155 }
156
157 return hw;
158 }
159 EXPORT_SYMBOL_GPL(imx_clk_hw_pfd);
160