1 // SPDX-License-Identifier: GPL-2.0
2 /*****************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include <drv_types.h>
9 #include "odm_precomp.h"
10
11 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
12 #define PATH_S0 1 /* RF_PATH_B */
13 #define IDX_0xC94 0
14 #define IDX_0xC80 1
15 #define IDX_0xC14 0
16 #define IDX_0xCA0 1
17 #define KEY 0
18 #define VAL 1
19
20 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
21 #define PATH_S1 0 /* RF_PATH_A */
22 #define IDX_0xC4C 2
23
24 /*---------------------------Define Local Constant---------------------------*/
25
26 /* In the case that we fail to read TxPowerTrack.txt, we use the table for
27 * 88E as the default table.
28 */
29 static u8 DeltaSwingTableIdx_2GA_N_8188E[] = {
30 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
31 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
32 };
33 static u8 DeltaSwingTableIdx_2GA_P_8188E[] = {
34 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4,
35 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9
36 };
37
38 /* 3 ============================================================ */
39 /* 3 Tx Power Tracking */
40 /* 3 ============================================================ */
41
42
setIqkMatrix_8723B(struct dm_odm_t * pDM_Odm,u8 OFDM_index,u8 RFPath,s32 IqkResult_X,s32 IqkResult_Y)43 static void setIqkMatrix_8723B(
44 struct dm_odm_t *pDM_Odm,
45 u8 OFDM_index,
46 u8 RFPath,
47 s32 IqkResult_X,
48 s32 IqkResult_Y
49 )
50 {
51 s32 ele_A = 0, ele_D, ele_C = 0, value32;
52
53 if (OFDM_index >= OFDM_TABLE_SIZE)
54 OFDM_index = OFDM_TABLE_SIZE-1;
55
56 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;
57
58 /* new element A = element D x X */
59 if (IqkResult_X != 0) {
60 if ((IqkResult_X & 0x00000200) != 0) /* consider minus */
61 IqkResult_X = IqkResult_X | 0xFFFFFC00;
62 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;
63
64 /* new element C = element D x Y */
65 if ((IqkResult_Y & 0x00000200) != 0)
66 IqkResult_Y = IqkResult_Y | 0xFFFFFC00;
67 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
68
69 /* if (RFPath == RF_PATH_A) */
70 switch (RFPath) {
71 case RF_PATH_A:
72 /* write new elements A, C, D to regC80 and regC94,
73 * element B is always 0
74 */
75 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
76 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
77
78 value32 = (ele_C&0x000003C0)>>6;
79 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
80
81 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
82 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32);
83 break;
84 case RF_PATH_B:
85 /* write new elements A, C, D to regC88 and regC9C,
86 * element B is always 0
87 */
88 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
89 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
90
91 value32 = (ele_C&0x000003C0)>>6;
92 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
93
94 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
95 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32);
96
97 break;
98 default:
99 break;
100 }
101 } else {
102 switch (RFPath) {
103 case RF_PATH_A:
104 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
105 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
106 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00);
107 break;
108
109 case RF_PATH_B:
110 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
111 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
112 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00);
113 break;
114
115 default:
116 break;
117 }
118 }
119 }
120
121
setCCKFilterCoefficient(struct dm_odm_t * pDM_Odm,u8 CCKSwingIndex)122 static void setCCKFilterCoefficient(struct dm_odm_t *pDM_Odm, u8 CCKSwingIndex)
123 {
124 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
125 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]);
126 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]);
127 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]);
128 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]);
129 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]);
130 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]);
131 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]);
132 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]);
133 } else {
134 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]);
135 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]);
136 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]);
137 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]);
138 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]);
139 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]);
140 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]);
141 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]);
142 }
143 }
144
145 /*-----------------------------------------------------------------------------
146 * Function: odm_TxPwrTrackSetPwr88E()
147 *
148 * Overview: 88E change all channel tx power according to flag.
149 * OFDM & CCK are all different.
150 *
151 * Input: NONE
152 *
153 * Output: NONE
154 *
155 * Return: NONE
156 *
157 * Revised History:
158 *When Who Remark
159 *04/23/2012 MHC Create Version 0.
160 *
161 *---------------------------------------------------------------------------*/
ODM_TxPwrTrackSetPwr_8723B(struct dm_odm_t * pDM_Odm,enum pwrtrack_method Method,u8 RFPath,u8 ChannelMappedIndex)162 void ODM_TxPwrTrackSetPwr_8723B(
163 struct dm_odm_t *pDM_Odm,
164 enum pwrtrack_method Method,
165 u8 RFPath,
166 u8 ChannelMappedIndex
167 )
168 {
169 struct adapter *Adapter = pDM_Odm->Adapter;
170 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
171 u8 PwrTrackingLimit_OFDM = 34; /* 0dB */
172 u8 PwrTrackingLimit_CCK = 28; /* 2dB */
173 u8 TxRate = 0xFF;
174 u8 Final_OFDM_Swing_Index = 0;
175 u8 Final_CCK_Swing_Index = 0;
176
177 {
178 u16 rate = *(pDM_Odm->pForcedDataRate);
179
180 if (!rate) { /* auto rate */
181 if (pDM_Odm->TxRate != 0xFF)
182 TxRate = HwRateToMRate(pDM_Odm->TxRate);
183 } else /* force rate */
184 TxRate = (u8)rate;
185
186 }
187
188 if (TxRate != 0xFF) {
189 /* 2 CCK */
190 if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M))
191 PwrTrackingLimit_CCK = 28; /* 2dB */
192 /* 2 OFDM */
193 else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M))
194 PwrTrackingLimit_OFDM = 36; /* 3dB */
195 else if (TxRate == MGN_54M)
196 PwrTrackingLimit_OFDM = 34; /* 2dB */
197
198 /* 2 HT */
199 else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /* QPSK/BPSK */
200 PwrTrackingLimit_OFDM = 38; /* 4dB */
201 else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /* 16QAM */
202 PwrTrackingLimit_OFDM = 36; /* 3dB */
203 else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /* 64QAM */
204 PwrTrackingLimit_OFDM = 34; /* 2dB */
205
206 else
207 PwrTrackingLimit_OFDM = pDM_Odm->DefaultOfdmIndex; /* Default OFDM index = 30 */
208 }
209
210 if (Method == TXAGC) {
211 struct adapter *Adapter = pDM_Odm->Adapter;
212
213 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
214
215 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
216 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
217
218 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
219 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
220 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
221 } else if (Method == BBSWING) {
222 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
223 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
224
225 /* Adjust BB swing by OFDM IQ matrix */
226 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
227 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
228 else if (Final_OFDM_Swing_Index <= 0)
229 Final_OFDM_Swing_Index = 0;
230
231 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)
232 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;
233 else if (pDM_Odm->BbSwingIdxCck <= 0)
234 Final_CCK_Swing_Index = 0;
235
236 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
237 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
238 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
239
240 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
241
242 } else if (Method == MIX_MODE) {
243 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
244 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
245
246 if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /* BBSwing higher then Limit */
247 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;
248
249 setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath,
250 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
251 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
252
253 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
254 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
255 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
256 } else if (Final_OFDM_Swing_Index <= 0) {
257 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;
258
259 setIqkMatrix_8723B(pDM_Odm, 0, RFPath,
260 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
261 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
262
263 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
264 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
265 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
266 } else {
267 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
268 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
269 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
270
271 if (pDM_Odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset TxAGC again */
272 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0;
273 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
274 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
275 pDM_Odm->Modify_TxAGC_Flag_PathA = false;
276 }
277 }
278
279 if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) {
280 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;
281 setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);
282 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
283 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
284 } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */
285 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
286 setCCKFilterCoefficient(pDM_Odm, 0);
287 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
288 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
289 } else {
290 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
291
292 if (pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, reset TxAGC again */
293 pDM_Odm->Remnant_CCKSwingIdx = 0;
294 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
295 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = false;
296 }
297 }
298 } else
299 return; /* This method is not supported. */
300 }
301
GetDeltaSwingTable_8723B(struct dm_odm_t * pDM_Odm,u8 ** TemperatureUP_A,u8 ** TemperatureDOWN_A,u8 ** TemperatureUP_B,u8 ** TemperatureDOWN_B)302 static void GetDeltaSwingTable_8723B(
303 struct dm_odm_t *pDM_Odm,
304 u8 **TemperatureUP_A,
305 u8 **TemperatureDOWN_A,
306 u8 **TemperatureUP_B,
307 u8 **TemperatureDOWN_B
308 )
309 {
310 struct adapter *Adapter = pDM_Odm->Adapter;
311 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
312 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
313 u16 rate = *(pDM_Odm->pForcedDataRate);
314 u8 channel = pHalData->CurrentChannel;
315
316 if (1 <= channel && channel <= 14) {
317 if (IS_CCK_RATE(rate)) {
318 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
319 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
320 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
321 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
322 } else {
323 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
324 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
325 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
326 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
327 }
328 } else {
329 *TemperatureUP_A = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
330 *TemperatureDOWN_A = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
331 *TemperatureUP_B = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
332 *TemperatureDOWN_B = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
333 }
334 }
335
336
ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg * pConfig)337 void ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg *pConfig)
338 {
339 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
340 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
341 pConfig->Threshold_IQK = IQK_THRESHOLD;
342 pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B;
343 pConfig->RfPathCount = MAX_PATH_NUM_8723B;
344 pConfig->ThermalRegAddr = RF_T_METER_8723B;
345
346 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B;
347 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B;
348 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B;
349 }
350
351 /* 1 7. IQK */
352 #define MAX_TOLERANCE 5
353
354 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathA_IQK_8723B(struct adapter * padapter,bool configPathB,u8 RF_Path)355 static u8 phy_PathA_IQK_8723B(
356 struct adapter *padapter, bool configPathB, u8 RF_Path
357 )
358 {
359 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/;
360 u8 result = 0x00;
361
362 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
363 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
364
365 /* Save RF Path */
366 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
367
368 /* leave IQK mode */
369 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
370
371 /* enable path A PA in TXIQK mode */
372 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
373 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
374 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
375 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
376 /* disable path B PA in TXIQK mode */
377 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */
378 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */
379
380 /* 1 Tx IQK */
381 /* IQK setting */
382 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
383 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
384 /* path-A IQK setting */
385 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
386 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
387 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
388 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
389 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */
390 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
391 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
392 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
393 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
394
395 /* LO calibration setting */
396 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
397
398 /* enter IQK mode */
399 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
400
401 /* Ant switch */
402 if (configPathB || (RF_Path == 0))
403 /* wifi switch to S1 */
404 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
405 else
406 /* wifi switch to S0 */
407 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
408
409 /* GNT_BT = 0 */
410 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
411
412 /* One shot, path A LOK & IQK */
413 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
414 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
415
416 /* delay x ms */
417 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
418 mdelay(IQK_DELAY_TIME_8723B);
419
420 /* restore Ant Path */
421 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
422 /* GNT_BT = 1 */
423 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
424
425 /* leave IQK mode */
426 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
427
428
429 /* Check failed */
430 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
431 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
432 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
433
434
435 /* Allen 20131125 */
436 tmp = (regE9C & 0x03FF0000)>>16;
437 if ((tmp & 0x200) > 0)
438 tmp = 0x400 - tmp;
439
440 if (
441 !(regEAC & BIT28) &&
442 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
443 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
444 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
445 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
446 (tmp < 0xf)
447 )
448 result |= 0x01;
449 else /* if Tx not OK, ignore Rx */
450 return result;
451
452 return result;
453 }
454
455 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathA_RxIQK8723B(struct adapter * padapter,bool configPathB,u8 RF_Path)456 static u8 phy_PathA_RxIQK8723B(
457 struct adapter *padapter, bool configPathB, u8 RF_Path
458 )
459 {
460 u32 regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB;
461 u8 result = 0x00;
462 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
463 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
464
465 /* Save RF Path */
466 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
467
468 /* leave IQK mode */
469 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
470 /* 1 Get TXIMR setting */
471 /* modify RXIQK mode table */
472 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
473 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
474 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
475 /* LNA2 off, PA on for Dcut */
476 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
477 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
478 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
479
480 /* IQK setting */
481 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
482 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
483
484 /* path-A IQK setting */
485 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
486 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
487 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
488 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
489
490 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
491 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
492 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
493 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
494 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
495
496 /* LO calibration setting */
497 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
498
499 /* enter IQK mode */
500 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
501
502 /* Ant switch */
503 if (configPathB || (RF_Path == 0))
504 /* wifi switch to S1 */
505 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
506 else
507 /* wifi switch to S0 */
508 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
509
510 /* GNT_BT = 0 */
511 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
512
513 /* One shot, path A LOK & IQK */
514 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
515 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
516
517 /* delay x ms */
518 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
519 mdelay(IQK_DELAY_TIME_8723B);
520
521 /* restore Ant Path */
522 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
523 /* GNT_BT = 1 */
524 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
525
526 /* leave IQK mode */
527 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
528
529 /* Check failed */
530 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
531 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
532 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
533
534 /* Allen 20131125 */
535 tmp = (regE9C & 0x03FF0000)>>16;
536 if ((tmp & 0x200) > 0)
537 tmp = 0x400 - tmp;
538
539 if (
540 !(regEAC & BIT28) &&
541 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
542 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
543 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
544 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
545 (tmp < 0xf)
546 )
547 result |= 0x01;
548 else /* if Tx not OK, ignore Rx */
549 return result;
550
551 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
552 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
553
554 /* modify RXIQK mode table */
555 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
556 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
557 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
558 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
559 /* LAN2 on, PA off for Dcut */
560 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
561 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
562
563 /* PA, PAD setting */
564 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
565 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f);
566
567
568 /* IQK setting */
569 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
570
571 /* path-A IQK setting */
572 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
573 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
574 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
575 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
576
577 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
578 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
579 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
580 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
581 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
582
583 /* LO calibration setting */
584 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
585
586 /* enter IQK mode */
587 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
588
589 /* Ant switch */
590 if (configPathB || (RF_Path == 0))
591 /* wifi switch to S1 */
592 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
593 else
594 /* wifi switch to S0 */
595 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
596
597 /* GNT_BT = 0 */
598 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
599
600 /* One shot, path A LOK & IQK */
601 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
602 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
603
604 /* delay x ms */
605 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
606 mdelay(IQK_DELAY_TIME_8723B);
607
608 /* restore Ant Path */
609 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
610 /* GNT_BT = 1 */
611 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
612
613 /* leave IQK mode */
614 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
615
616 /* Check failed */
617 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
618 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
619
620 /* PA/PAD controlled by 0x0 */
621 /* leave IQK mode */
622 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
623 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780);
624
625 /* Allen 20131125 */
626 tmp = (regEAC & 0x03FF0000)>>16;
627 if ((tmp & 0x200) > 0)
628 tmp = 0x400 - tmp;
629
630 if (
631 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
632 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
633 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
634 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
635 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
636 (tmp < 0xf)
637 )
638 result |= 0x02;
639
640 return result;
641 }
642
643 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathB_IQK_8723B(struct adapter * padapter)644 static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
645 {
646 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/;
647 u8 result = 0x00;
648 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
649 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
650
651 /* Save RF Path */
652 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
653
654 /* leave IQK mode */
655 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
656
657 /* in TXIQK mode */
658 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */
659 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */
660 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */
661 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */
662 /* enable path B PA in TXIQK mode */
663 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
664 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1);
665
666
667
668 /* 1 Tx IQK */
669 /* IQK setting */
670 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
671 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
672 /* path-A IQK setting */
673 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
674 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
675 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
676 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
677
678 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */
679 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
680 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
681 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
682 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
683
684 /* LO calibration setting */
685 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
686
687 /* enter IQK mode */
688 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
689
690 /* switch to path B */
691 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
692 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
693
694 /* GNT_BT = 0 */
695 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
696
697 /* One shot, path B LOK & IQK */
698 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
699 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
700
701 /* delay x ms */
702 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
703 mdelay(IQK_DELAY_TIME_8723B);
704
705 /* restore Ant Path */
706 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
707 /* GNT_BT = 1 */
708 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
709
710 /* leave IQK mode */
711 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
712
713 /* Check failed */
714 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
715 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
716 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
717
718 /* Allen 20131125 */
719 tmp = (regE9C & 0x03FF0000)>>16;
720 if ((tmp & 0x200) > 0)
721 tmp = 0x400 - tmp;
722
723 if (
724 !(regEAC & BIT28) &&
725 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
726 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
727 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
728 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
729 (tmp < 0xf)
730 )
731 result |= 0x01;
732
733 return result;
734 }
735
736 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathB_RxIQK8723B(struct adapter * padapter,bool configPathB)737 static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
738 {
739 u32 regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB;
740 u8 result = 0x00;
741 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
742 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
743
744 /* Save RF Path */
745 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
746 /* leave IQK mode */
747 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
748
749 /* switch to path B */
750 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
751 /* modify RXIQK mode table */
752 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
753 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
754 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
755 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
756 /* open PA S1 & SMIXER */
757 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
758 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd);
759
760
761 /* IQK setting */
762 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
763 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
764
765
766 /* path-B IQK setting */
767 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
768 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
769 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
770 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
771
772 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
773 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
774 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
775 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
776 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
777
778 /* LO calibration setting */
779 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
780
781 /* enter IQK mode */
782 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
783
784 /* switch to path B */
785 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
786 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
787
788 /* GNT_BT = 0 */
789 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
790
791 /* One shot, path B TXIQK @ RXIQK */
792 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
793 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
794
795
796 /* delay x ms */
797 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
798 mdelay(IQK_DELAY_TIME_8723B);
799
800 /* restore Ant Path */
801 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
802 /* GNT_BT = 1 */
803 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
804
805 /* leave IQK mode */
806 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
807
808 /* Check failed */
809 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
810 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
811 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
812
813 /* Allen 20131125 */
814 tmp = (regE9C & 0x03FF0000)>>16;
815 if ((tmp & 0x200) > 0)
816 tmp = 0x400 - tmp;
817
818 if (
819 !(regEAC & BIT28) &&
820 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
821 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
822 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
823 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
824 (tmp < 0xf)
825 )
826 result |= 0x01;
827 else /* if Tx not OK, ignore Rx */
828 return result;
829
830 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
831 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
832
833 /* modify RXIQK mode table */
834 /* 20121009, Kordan> RF Mode = 3 */
835 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
836 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
837 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
838 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
839 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
840 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
841
842 /* open PA S1 & close SMIXER */
843 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
844 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd);
845
846 /* PA, PAD setting */
847 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */
848 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */
849
850 /* IQK setting */
851 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
852
853 /* path-B IQK setting */
854 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
855 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
856 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
857 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
858
859 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
860 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
861 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
862 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
863 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
864
865 /* LO calibration setting */
866 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
867
868 /* enter IQK mode */
869 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
870
871 /* switch to path B */
872 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
873 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
874
875 /* GNT_BT = 0 */
876 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
877
878 /* One shot, path B LOK & IQK */
879 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
880 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
881
882 /* delay x ms */
883 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
884 mdelay(IQK_DELAY_TIME_8723B);
885
886 /* restore Ant Path */
887 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
888 /* GNT_BT = 1 */
889 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
890
891 /* leave IQK mode */
892 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
893
894 /* Check failed */
895 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
896 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
897
898 /* PA/PAD controlled by 0x0 */
899 /* leave IQK mode */
900 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */
901 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */
902
903
904
905 /* Allen 20131125 */
906 tmp = (regEAC & 0x03FF0000)>>16;
907 if ((tmp & 0x200) > 0)
908 tmp = 0x400 - tmp;
909
910 if (
911 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
912 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
913 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
914 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
915 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
916 (tmp < 0xf)
917 )
918 result |= 0x02;
919
920 return result;
921 }
922
_PHY_PathAFillIQKMatrix8723B(struct adapter * padapter,bool bIQKOK,s32 result[][8],u8 final_candidate,bool bTxOnly)923 static void _PHY_PathAFillIQKMatrix8723B(
924 struct adapter *padapter,
925 bool bIQKOK,
926 s32 result[][8],
927 u8 final_candidate,
928 bool bTxOnly
929 )
930 {
931 u32 Oldval_0, X, TX0_A, reg;
932 s32 Y, TX0_C;
933 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
934 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
935
936 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
937
938 if (final_candidate == 0xFF)
939 return;
940
941 else if (bIQKOK) {
942 Oldval_0 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
943
944 X = result[final_candidate][0];
945 if ((X & 0x00000200) != 0)
946 X = X | 0xFFFFFC00;
947 TX0_A = (X * Oldval_0) >> 8;
948 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
949
950 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_0>>7) & 0x1));
951
952 Y = result[final_candidate][1];
953 if ((Y & 0x00000200) != 0)
954 Y = Y | 0xFFFFFC00;
955
956 /* 2 Tx IQC */
957 TX0_C = (Y * Oldval_0) >> 8;
958 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
959 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
960 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord);
961
962 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
963 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
964 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord);
965
966 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_0>>7) & 0x1));
967 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
968 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
969
970 if (bTxOnly) {
971 /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
972 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
973 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
974 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
975 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
976 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;
977 return;
978 }
979
980 reg = result[final_candidate][2];
981
982 /* 2 Rx IQC */
983 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
984 reg = result[final_candidate][3] & 0x3F;
985 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
986 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
987 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord);
988
989 reg = (result[final_candidate][3] >> 6) & 0xF;
990 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
991 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
992 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
993
994 }
995 }
996
_PHY_PathBFillIQKMatrix8723B(struct adapter * padapter,bool bIQKOK,s32 result[][8],u8 final_candidate,bool bTxOnly)997 static void _PHY_PathBFillIQKMatrix8723B(
998 struct adapter *padapter,
999 bool bIQKOK,
1000 s32 result[][8],
1001 u8 final_candidate,
1002 bool bTxOnly /* do Tx only */
1003 )
1004 {
1005 u32 Oldval_1, X, TX1_A, reg;
1006 s32 Y, TX1_C;
1007 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1008 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1009
1010 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
1011
1012 if (final_candidate == 0xFF)
1013 return;
1014
1015 else if (bIQKOK) {
1016 Oldval_1 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1017
1018 X = result[final_candidate][4];
1019 if ((X & 0x00000200) != 0)
1020 X = X | 0xFFFFFC00;
1021 TX1_A = (X * Oldval_1) >> 8;
1022
1023 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
1024
1025 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_1>>7) & 0x1));
1026
1027 Y = result[final_candidate][5];
1028 if ((Y & 0x00000200) != 0)
1029 Y = Y | 0xFFFFFC00;
1030
1031 TX1_C = (Y * Oldval_1) >> 8;
1032
1033 /* 2 Tx IQC */
1034 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
1035 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */
1036 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */
1037 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1038 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord);
1039
1040 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
1041 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1042 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord);
1043
1044 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_1>>7) & 0x1));
1045 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1046 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
1047
1048 if (bTxOnly) {
1049 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1050 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
1051 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;
1052 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1053 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1054 return;
1055 }
1056
1057 /* 2 Rx IQC */
1058 reg = result[final_candidate][6];
1059 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
1060 reg = result[final_candidate][7] & 0x3F;
1061 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
1062 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1063 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord);
1064
1065 reg = (result[final_candidate][7] >> 6) & 0xF;
1066 /* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */
1067 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1068 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff);
1069 }
1070 }
1071
1072 /* */
1073 /* 2011/07/26 MH Add an API for testing IQK fail case. */
1074 /* */
1075 /* MP Already declare in odm.c */
1076
ODM_SetIQCbyRFpath(struct dm_odm_t * pDM_Odm,u32 RFpath)1077 void ODM_SetIQCbyRFpath(struct dm_odm_t *pDM_Odm, u32 RFpath)
1078 {
1079
1080 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
1081
1082 if (
1083 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) &&
1084 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) &&
1085 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) &&
1086 (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)
1087 ) {
1088 if (RFpath) { /* S1: RFpath = 0, S0:RFpath = 1 */
1089 /* S0 TX IQC */
1090 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]);
1091 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]);
1092 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]);
1093 /* S0 RX IQC */
1094 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]);
1095 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]);
1096 } else {
1097 /* S1 TX IQC */
1098 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]);
1099 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]);
1100 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]);
1101 /* S1 RX IQC */
1102 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]);
1103 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]);
1104 }
1105 }
1106 }
1107
ODM_CheckPowerStatus(struct adapter * Adapter)1108 static bool ODM_CheckPowerStatus(struct adapter *Adapter)
1109 {
1110 return true;
1111 }
1112
_PHY_SaveADDARegisters8723B(struct adapter * padapter,u32 * ADDAReg,u32 * ADDABackup,u32 RegisterNum)1113 static void _PHY_SaveADDARegisters8723B(
1114 struct adapter *padapter,
1115 u32 *ADDAReg,
1116 u32 *ADDABackup,
1117 u32 RegisterNum
1118 )
1119 {
1120 u32 i;
1121 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1122 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1123
1124 if (!ODM_CheckPowerStatus(padapter))
1125 return;
1126
1127 for (i = 0 ; i < RegisterNum ; i++) {
1128 ADDABackup[i] = PHY_QueryBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord);
1129 }
1130 }
1131
1132
_PHY_SaveMACRegisters8723B(struct adapter * padapter,u32 * MACReg,u32 * MACBackup)1133 static void _PHY_SaveMACRegisters8723B(
1134 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1135 )
1136 {
1137 u32 i;
1138 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1139 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1140
1141 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1142 MACBackup[i] = rtw_read8(pDM_Odm->Adapter, MACReg[i]);
1143 }
1144 MACBackup[i] = rtw_read32(pDM_Odm->Adapter, MACReg[i]);
1145
1146 }
1147
1148
_PHY_ReloadADDARegisters8723B(struct adapter * padapter,u32 * ADDAReg,u32 * ADDABackup,u32 RegiesterNum)1149 static void _PHY_ReloadADDARegisters8723B(
1150 struct adapter *padapter,
1151 u32 *ADDAReg,
1152 u32 *ADDABackup,
1153 u32 RegiesterNum
1154 )
1155 {
1156 u32 i;
1157 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1158 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1159
1160 for (i = 0 ; i < RegiesterNum; i++) {
1161 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]);
1162 }
1163 }
1164
_PHY_ReloadMACRegisters8723B(struct adapter * padapter,u32 * MACReg,u32 * MACBackup)1165 static void _PHY_ReloadMACRegisters8723B(
1166 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1167 )
1168 {
1169 u32 i;
1170
1171 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1172 rtw_write8(padapter, MACReg[i], (u8)MACBackup[i]);
1173 }
1174 rtw_write32(padapter, MACReg[i], MACBackup[i]);
1175 }
1176
1177
_PHY_PathADDAOn8723B(struct adapter * padapter,u32 * ADDAReg,bool is2T)1178 static void _PHY_PathADDAOn8723B(
1179 struct adapter *padapter,
1180 u32 *ADDAReg,
1181 bool is2T
1182 )
1183 {
1184 u32 pathOn;
1185 u32 i;
1186 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1187 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1188
1189 pathOn = 0x01c00014;
1190 if (!is2T) {
1191 pathOn = 0x01c00014;
1192 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014);
1193 } else {
1194 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, pathOn);
1195 }
1196
1197 for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) {
1198 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, pathOn);
1199 }
1200
1201 }
1202
_PHY_MACSettingCalibration8723B(struct adapter * padapter,u32 * MACReg,u32 * MACBackup)1203 static void _PHY_MACSettingCalibration8723B(
1204 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1205 )
1206 {
1207 u32 i = 0;
1208 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1209 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1210
1211 rtw_write8(pDM_Odm->Adapter, MACReg[i], 0x3F);
1212
1213 for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1214 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
1215 }
1216 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
1217
1218 }
1219
phy_SimularityCompare_8723B(struct adapter * padapter,s32 result[][8],u8 c1,u8 c2)1220 static bool phy_SimularityCompare_8723B(
1221 struct adapter *padapter,
1222 s32 result[][8],
1223 u8 c1,
1224 u8 c2
1225 )
1226 {
1227 u32 i, j, diff, SimularityBitMap, bound = 0;
1228 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
1229 bool bResult = true;
1230 s32 tmp1 = 0, tmp2 = 0;
1231
1232 bound = 8;
1233 SimularityBitMap = 0;
1234
1235 for (i = 0; i < bound; i++) {
1236
1237 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
1238 if ((result[c1][i] & 0x00000200) != 0)
1239 tmp1 = result[c1][i] | 0xFFFFFC00;
1240 else
1241 tmp1 = result[c1][i];
1242
1243 if ((result[c2][i] & 0x00000200) != 0)
1244 tmp2 = result[c2][i] | 0xFFFFFC00;
1245 else
1246 tmp2 = result[c2][i];
1247 } else {
1248 tmp1 = result[c1][i];
1249 tmp2 = result[c2][i];
1250 }
1251
1252 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1253
1254 if (diff > MAX_TOLERANCE) {
1255 if ((i == 2 || i == 6) && !SimularityBitMap) {
1256 if (result[c1][i]+result[c1][i+1] == 0)
1257 final_candidate[(i/4)] = c2;
1258 else if (result[c2][i]+result[c2][i+1] == 0)
1259 final_candidate[(i/4)] = c1;
1260 else
1261 SimularityBitMap = SimularityBitMap|(1<<i);
1262 } else
1263 SimularityBitMap = SimularityBitMap|(1<<i);
1264 }
1265 }
1266
1267 if (SimularityBitMap == 0) {
1268 for (i = 0; i < (bound/4); i++) {
1269 if (final_candidate[i] != 0xFF) {
1270 for (j = i*4; j < (i+1)*4-2; j++)
1271 result[3][j] = result[final_candidate[i]][j];
1272 bResult = false;
1273 }
1274 }
1275 return bResult;
1276 } else {
1277
1278 if (!(SimularityBitMap & 0x03)) { /* path A TX OK */
1279 for (i = 0; i < 2; i++)
1280 result[3][i] = result[c1][i];
1281 }
1282
1283 if (!(SimularityBitMap & 0x0c)) { /* path A RX OK */
1284 for (i = 2; i < 4; i++)
1285 result[3][i] = result[c1][i];
1286 }
1287
1288 if (!(SimularityBitMap & 0x30)) { /* path B TX OK */
1289 for (i = 4; i < 6; i++)
1290 result[3][i] = result[c1][i];
1291 }
1292
1293 if (!(SimularityBitMap & 0xc0)) { /* path B RX OK */
1294 for (i = 6; i < 8; i++)
1295 result[3][i] = result[c1][i];
1296 }
1297 return false;
1298 }
1299 }
1300
1301
1302
phy_IQCalibrate_8723B(struct adapter * padapter,s32 result[][8],u8 t,bool is2T,u8 RF_Path)1303 static void phy_IQCalibrate_8723B(
1304 struct adapter *padapter,
1305 s32 result[][8],
1306 u8 t,
1307 bool is2T,
1308 u8 RF_Path
1309 )
1310 {
1311 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1312 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1313
1314 u32 i;
1315 u8 PathAOK, PathBOK;
1316 u8 tmp0xc50 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0);
1317 u8 tmp0xc58 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0);
1318 u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
1319 rFPGA0_XCD_SwitchControl,
1320 rBlue_Tooth,
1321 rRx_Wait_CCA,
1322 rTx_CCK_RFON,
1323 rTx_CCK_BBON,
1324 rTx_OFDM_RFON,
1325 rTx_OFDM_BBON,
1326 rTx_To_Rx,
1327 rTx_To_Tx,
1328 rRx_CCK,
1329 rRx_OFDM,
1330 rRx_Wait_RIFS,
1331 rRx_TO_Rx,
1332 rStandby,
1333 rSleep,
1334 rPMPD_ANAEN
1335 };
1336 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1337 REG_TXPAUSE,
1338 REG_BCN_CTRL,
1339 REG_BCN_CTRL_1,
1340 REG_GPIO_MUXCFG
1341 };
1342
1343 /* since 92C & 92D have the different define in IQK_BB_REG */
1344 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1345 rOFDM0_TRxPathEnable,
1346 rOFDM0_TRMuxPar,
1347 rFPGA0_XCD_RFInterfaceSW,
1348 rConfig_AntA,
1349 rConfig_AntB,
1350 rFPGA0_XAB_RFInterfaceSW,
1351 rFPGA0_XA_RFInterfaceOE,
1352 rFPGA0_XB_RFInterfaceOE,
1353 rCCK0_AFESetting
1354 };
1355 const u32 retryCount = 2;
1356
1357 /* Note: IQ calibration must be performed after loading */
1358 /* PHY_REG.txt , and radio_a, radio_b.txt */
1359
1360 /* u32 bbvalue; */
1361
1362 if (t == 0) {
1363
1364 /* Save ADDA parameters, turn Path A ADDA on */
1365 _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1366 _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1367 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1368 }
1369
1370 _PHY_PathADDAOn8723B(padapter, ADDA_REG, is2T);
1371
1372 /* no serial mode */
1373
1374 /* save RF path for 8723B */
1375 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1376 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
1377
1378 /* MAC settings */
1379 _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1380
1381 /* BB setting */
1382 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */
1383 PHY_SetBBReg(pDM_Odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf);
1384 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1385 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1386 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1387
1388
1389 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */
1390 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */
1391 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */
1392 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */
1393
1394
1395 /* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */
1396
1397 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1398 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1399 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
1400 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
1401 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
1402 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
1403 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd);
1404
1405 /* path A TX IQK */
1406 for (i = 0 ; i < retryCount ; i++) {
1407 PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
1408 /* if (PathAOK == 0x03) { */
1409 if (PathAOK == 0x01) {
1410 /* Path A Tx IQK Success */
1411 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1412 pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x8, bRFRegOffsetMask);
1413
1414 result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1415 result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1416 break;
1417 }
1418 }
1419
1420 /* path A RXIQK */
1421 for (i = 0 ; i < retryCount ; i++) {
1422 PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path);
1423 if (PathAOK == 0x03) {
1424 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1425 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1426 result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1427 result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1428 break;
1429 }
1430 }
1431
1432 if (0x00 == PathAOK) {
1433 }
1434
1435 /* path B IQK */
1436 if (is2T) {
1437
1438 /* path B TX IQK */
1439 for (i = 0 ; i < retryCount ; i++) {
1440 PathBOK = phy_PathB_IQK_8723B(padapter);
1441 if (PathBOK == 0x01) {
1442 /* Path B Tx IQK Success */
1443 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1444 pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_B, 0x8, bRFRegOffsetMask);
1445
1446 result[t][4] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1447 result[t][5] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1448 break;
1449 }
1450 }
1451
1452 /* path B RX IQK */
1453 for (i = 0 ; i < retryCount ; i++) {
1454 PathBOK = phy_PathB_RxIQK8723B(padapter, is2T);
1455 if (PathBOK == 0x03) {
1456 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1457 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1458 result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1459 result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1460 break;
1461 }
1462 }
1463
1464 /* Allen end */
1465 }
1466
1467 /* Back to BB mode, load original value */
1468 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0);
1469
1470 if (t != 0) {
1471 /* Reload ADDA power saving parameters */
1472 _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1473
1474 /* Reload MAC parameters */
1475 _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1476
1477 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1478
1479 /* Reload RF path */
1480 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
1481 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
1482
1483 /* Allen initial gain 0xc50 */
1484 /* Restore RX initial gain */
1485 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50);
1486 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50);
1487 if (is2T) {
1488 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50);
1489 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58);
1490 }
1491
1492 /* load 0xe30 IQC default value */
1493 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1494 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1495
1496 }
1497
1498 }
1499
1500
phy_LCCalibrate_8723B(struct dm_odm_t * pDM_Odm,bool is2T)1501 static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
1502 {
1503 u8 tmpReg;
1504 u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
1505 struct adapter *padapter = pDM_Odm->Adapter;
1506
1507 /* Check continuous TX and Packet TX */
1508 tmpReg = rtw_read8(pDM_Odm->Adapter, 0xd03);
1509
1510 if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
1511 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
1512 else /* Deal with Packet TX case */
1513 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */
1514
1515 if ((tmpReg&0x70) != 0) {
1516 /* 1. Read original RF mode */
1517 /* Path-A */
1518 RF_Amode = PHY_QueryRFReg(padapter, RF_PATH_A, RF_AC, bMask12Bits);
1519
1520 /* Path-B */
1521 if (is2T)
1522 RF_Bmode = PHY_QueryRFReg(padapter, RF_PATH_B, RF_AC, bMask12Bits);
1523
1524 /* 2. Set RF mode = standby mode */
1525 /* Path-A */
1526 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
1527
1528 /* Path-B */
1529 if (is2T)
1530 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
1531 }
1532
1533 /* 3. Read RF reg18 */
1534 LC_Cal = PHY_QueryRFReg(padapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
1535
1536 /* 4. Set LC calibration begin bit15 */
1537 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */
1538 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
1539
1540 mdelay(100);
1541
1542 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */
1543
1544 /* Channel 10 LC calibration issue for 8723bs with 26M xtal */
1545 if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) {
1546 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);
1547 }
1548
1549 /* Restore original situation */
1550 if ((tmpReg&0x70) != 0) { /* Deal with contisuous TX case */
1551 /* Path-A */
1552 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg);
1553 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
1554
1555 /* Path-B */
1556 if (is2T)
1557 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
1558 } else /* Deal with Packet TX case */
1559 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00);
1560 }
1561
1562 /* IQK version:V2.5 20140123 */
1563 /* IQK is controlled by Is2ant, RF path */
PHY_IQCalibrate_8723B(struct adapter * padapter,bool bReCovery,bool bRestore,bool Is2ant,u8 RF_Path)1564 void PHY_IQCalibrate_8723B(
1565 struct adapter *padapter,
1566 bool bReCovery,
1567 bool bRestore,
1568 bool Is2ant, /* false:1ant, true:2-ant */
1569 u8 RF_Path /* 0:S1, 1:S0 */
1570 )
1571 {
1572 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1573
1574 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1575
1576 s32 result[4][8]; /* last is final result */
1577 u8 i, final_candidate;
1578 bool bPathAOK, bPathBOK;
1579 s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC, RegEC4, RegTmp = 0;
1580 bool is12simular, is13simular, is23simular;
1581 bool bSingleTone = false, bCarrierSuppression = false;
1582 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1583 rOFDM0_XARxIQImbalance,
1584 rOFDM0_XBRxIQImbalance,
1585 rOFDM0_ECCAThreshold,
1586 rOFDM0_AGCRSSITable,
1587 rOFDM0_XATxIQImbalance,
1588 rOFDM0_XBTxIQImbalance,
1589 rOFDM0_XCTxAFE,
1590 rOFDM0_XDTxAFE,
1591 rOFDM0_RxIQExtAnta
1592 };
1593 /* u32 Path_SEL_BB = 0; */
1594 u32 GNT_BT_default;
1595
1596 if (!ODM_CheckPowerStatus(padapter))
1597 return;
1598
1599 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
1600 return;
1601
1602 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
1603 if (bSingleTone || bCarrierSuppression)
1604 return;
1605
1606 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
1607 return;
1608
1609
1610 pDM_Odm->RFCalibrateInfo.bIQKInProgress = true;
1611
1612 if (bRestore) {
1613 u32 offset, data;
1614 u8 path, bResult = SUCCESS;
1615 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
1616
1617 path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? RF_PATH_A : RF_PATH_B;
1618
1619 /* Restore TX IQK */
1620 for (i = 0; i < 3; ++i) {
1621 offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];
1622 data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];
1623 if ((offset == 0) || (data == 0)) {
1624 bResult = FAIL;
1625 break;
1626 }
1627 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1628 }
1629
1630 /* Restore RX IQK */
1631 for (i = 0; i < 2; ++i) {
1632 offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];
1633 data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];
1634 if ((offset == 0) || (data == 0)) {
1635 bResult = FAIL;
1636 break;
1637 }
1638 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1639 }
1640
1641 if (pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] == 0) {
1642 bResult = FAIL;
1643 } else {
1644 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A]);
1645 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B]);
1646 }
1647
1648 if (bResult == SUCCESS)
1649 return;
1650 }
1651
1652 if (bReCovery) {
1653 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1654 return;
1655 }
1656
1657 /* save default GNT_BT */
1658 GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord);
1659 /* Save RF Path */
1660 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1661 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
1662
1663 /* set GNT_BT = 0, pause BT traffic */
1664 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
1665 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */
1666
1667
1668 for (i = 0; i < 8; i++) {
1669 result[0][i] = 0;
1670 result[1][i] = 0;
1671 result[2][i] = 0;
1672 result[3][i] = 0;
1673 }
1674
1675 final_candidate = 0xff;
1676 bPathAOK = false;
1677 bPathBOK = false;
1678 is12simular = false;
1679 is23simular = false;
1680 is13simular = false;
1681
1682
1683 for (i = 0; i < 3; i++) {
1684 phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path);
1685
1686 if (i == 1) {
1687 is12simular = phy_SimularityCompare_8723B(padapter, result, 0, 1);
1688 if (is12simular) {
1689 final_candidate = 0;
1690 break;
1691 }
1692 }
1693
1694 if (i == 2) {
1695 is13simular = phy_SimularityCompare_8723B(padapter, result, 0, 2);
1696 if (is13simular) {
1697 final_candidate = 0;
1698
1699 break;
1700 }
1701
1702 is23simular = phy_SimularityCompare_8723B(padapter, result, 1, 2);
1703 if (is23simular) {
1704 final_candidate = 1;
1705 } else {
1706 for (i = 0; i < 8; i++)
1707 RegTmp += result[3][i];
1708
1709 if (RegTmp != 0)
1710 final_candidate = 3;
1711 else
1712 final_candidate = 0xFF;
1713 }
1714 }
1715 }
1716
1717 for (i = 0; i < 4; i++) {
1718 RegE94 = result[i][0];
1719 RegE9C = result[i][1];
1720 RegEA4 = result[i][2];
1721 RegEB4 = result[i][4];
1722 RegEBC = result[i][5];
1723 RegEC4 = result[i][6];
1724 }
1725
1726 if (final_candidate != 0xff) {
1727 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
1728 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
1729 RegEA4 = result[final_candidate][2];
1730 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
1731 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
1732 RegEC4 = result[final_candidate][6];
1733 bPathAOK = bPathBOK = true;
1734 } else {
1735 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */
1736 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */
1737 }
1738
1739 {
1740 if (RegE94 != 0)
1741 _PHY_PathAFillIQKMatrix8723B(padapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
1742 }
1743 {
1744 if (RegEB4 != 0)
1745 _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
1746 }
1747
1748 /* To Fix BSOD when final_candidate is 0xff */
1749 /* by sherry 20120321 */
1750 if (final_candidate < 4) {
1751 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
1752 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[0][i] = result[final_candidate][i];
1753 }
1754
1755 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1756
1757 /* restore GNT_BT */
1758 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default);
1759 /* Restore RF Path */
1760 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
1761 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
1762
1763 /* Resotr RX mode table parameter */
1764 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1765 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
1766 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
1767 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177);
1768 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
1769 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd);
1770
1771 /* set GNT_BT = HW control */
1772 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
1773 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */
1774
1775 if (Is2ant) {
1776 if (RF_Path == 0x0) /* S1 */
1777 ODM_SetIQCbyRFpath(pDM_Odm, 0);
1778 else /* S0 */
1779 ODM_SetIQCbyRFpath(pDM_Odm, 1);
1780 }
1781
1782 pDM_Odm->RFCalibrateInfo.bIQKInProgress = false;
1783 }
1784
1785
PHY_LCCalibrate_8723B(struct dm_odm_t * pDM_Odm)1786 void PHY_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm)
1787 {
1788 bool bSingleTone = false, bCarrierSuppression = false;
1789 u32 timeout = 2000, timecount = 0;
1790
1791 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
1792 return;
1793
1794 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
1795 if (bSingleTone || bCarrierSuppression)
1796 return;
1797
1798 while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) {
1799 mdelay(50);
1800 timecount += 50;
1801 }
1802
1803 pDM_Odm->RFCalibrateInfo.bLCKInProgress = true;
1804
1805
1806 phy_LCCalibrate_8723B(pDM_Odm, false);
1807
1808
1809 pDM_Odm->RFCalibrateInfo.bLCKInProgress = false;
1810 }
1811