xref: /qemu/hw/ppc/prep.c (revision a8b5c10c7147ebc992de12fdc3f25a219f5c742f)
1 /*
2  * QEMU PPC PREP hardware System Emulator
3  *
4  * Copyright (c) 2003-2007 Jocelyn Mayer
5  * Copyright (c) 2017 Hervé Poussineau
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 
26 #include "qemu/osdep.h"
27 #include "hw/rtc/m48t59.h"
28 #include "hw/block/fdc.h"
29 #include "net/net.h"
30 #include "hw/isa/isa.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/pci_host.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/boards.h"
35 #include "qapi/error.h"
36 #include "qemu/error-report.h"
37 #include "qemu/log.h"
38 #include "qemu/datadir.h"
39 #include "hw/loader.h"
40 #include "hw/rtc/mc146818rtc.h"
41 #include "hw/isa/pc87312.h"
42 #include "hw/qdev-properties.h"
43 #include "exec/target_page.h"
44 #include "system/kvm.h"
45 #include "system/reset.h"
46 #include "trace.h"
47 #include "elf.h"
48 #include "qemu/units.h"
49 #include "audio/audio.h"
50 
51 /* SMP is not enabled, for now */
52 #define MAX_CPUS 1
53 
54 #define CFG_ADDR 0xf0000510
55 
56 #define KERNEL_LOAD_ADDR 0x01000000
57 #define INITRD_LOAD_ADDR 0x01800000
58 
59 #define BIOS_ADDR         0xfff00000
60 #define BIOS_SIZE         (1 * MiB)
61 #define NVRAM_SIZE        0x2000
62 
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)63 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
64                             Error **errp)
65 {
66     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
67 }
68 
ppc_prep_reset(void * opaque)69 static void ppc_prep_reset(void *opaque)
70 {
71     PowerPCCPU *cpu = opaque;
72 
73     cpu_reset(CPU(cpu));
74     cpu_ppc_tb_reset(&cpu->env);
75 }
76 
77 
78 /*****************************************************************************/
79 /* NVRAM helpers */
nvram_read(Nvram * nvram,uint32_t addr)80 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
81 {
82     NvramClass *k = NVRAM_GET_CLASS(nvram);
83     return (k->read)(nvram, addr);
84 }
85 
nvram_write(Nvram * nvram,uint32_t addr,uint32_t val)86 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
87 {
88     NvramClass *k = NVRAM_GET_CLASS(nvram);
89     (k->write)(nvram, addr, val);
90 }
91 
NVRAM_set_byte(Nvram * nvram,uint32_t addr,uint8_t value)92 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
93 {
94     nvram_write(nvram, addr, value);
95 }
96 
NVRAM_get_byte(Nvram * nvram,uint32_t addr)97 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
98 {
99     return nvram_read(nvram, addr);
100 }
101 
NVRAM_set_word(Nvram * nvram,uint32_t addr,uint16_t value)102 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
103 {
104     nvram_write(nvram, addr, value >> 8);
105     nvram_write(nvram, addr + 1, value & 0xFF);
106 }
107 
NVRAM_get_word(Nvram * nvram,uint32_t addr)108 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
109 {
110     uint16_t tmp;
111 
112     tmp = nvram_read(nvram, addr) << 8;
113     tmp |= nvram_read(nvram, addr + 1);
114 
115     return tmp;
116 }
117 
NVRAM_set_lword(Nvram * nvram,uint32_t addr,uint32_t value)118 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
119 {
120     nvram_write(nvram, addr, value >> 24);
121     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
122     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
123     nvram_write(nvram, addr + 3, value & 0xFF);
124 }
125 
NVRAM_set_string(Nvram * nvram,uint32_t addr,const char * str,uint32_t max)126 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
127                              uint32_t max)
128 {
129     int i;
130 
131     for (i = 0; i < max && str[i] != '\0'; i++) {
132         nvram_write(nvram, addr + i, str[i]);
133     }
134     nvram_write(nvram, addr + i, str[i]);
135     nvram_write(nvram, addr + max - 1, '\0');
136 }
137 
NVRAM_crc_update(uint16_t prev,uint16_t value)138 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
139 {
140     uint16_t tmp;
141     uint16_t pd, pd1, pd2;
142 
143     tmp = prev >> 8;
144     pd = prev ^ value;
145     pd1 = pd & 0x000F;
146     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
147     tmp ^= (pd1 << 3) | (pd1 << 8);
148     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
149 
150     return tmp;
151 }
152 
NVRAM_compute_crc(Nvram * nvram,uint32_t start,uint32_t count)153 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
154 {
155     uint32_t i;
156     uint16_t crc = 0xFFFF;
157     int odd;
158 
159     odd = count & 1;
160     count &= ~1;
161     for (i = 0; i != count; i++) {
162         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
163     }
164     if (odd) {
165         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
166     }
167 
168     return crc;
169 }
170 
171 #define CMDLINE_ADDR 0x017ff000
172 
PPC_NVRAM_set_params(Nvram * nvram,uint16_t NVRAM_size,const char * arch,uint32_t RAM_size,int boot_device,uint32_t kernel_image,uint32_t kernel_size,const char * cmdline,uint32_t initrd_image,uint32_t initrd_size,uint32_t NVRAM_image,int width,int height,int depth)173 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
174                           const char *arch,
175                           uint32_t RAM_size, int boot_device,
176                           uint32_t kernel_image, uint32_t kernel_size,
177                           const char *cmdline,
178                           uint32_t initrd_image, uint32_t initrd_size,
179                           uint32_t NVRAM_image,
180                           int width, int height, int depth)
181 {
182     uint16_t crc;
183 
184     /* Set parameters for Open Hack'Ware BIOS */
185     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
186     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
187     NVRAM_set_word(nvram,   0x14, NVRAM_size);
188     NVRAM_set_string(nvram, 0x20, arch, 16);
189     NVRAM_set_lword(nvram,  0x30, RAM_size);
190     NVRAM_set_byte(nvram,   0x34, boot_device);
191     NVRAM_set_lword(nvram,  0x38, kernel_image);
192     NVRAM_set_lword(nvram,  0x3C, kernel_size);
193     if (cmdline) {
194         /* XXX: put the cmdline in NVRAM too ? */
195         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
196                          cmdline);
197         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
198         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
199     } else {
200         NVRAM_set_lword(nvram,  0x40, 0);
201         NVRAM_set_lword(nvram,  0x44, 0);
202     }
203     NVRAM_set_lword(nvram,  0x48, initrd_image);
204     NVRAM_set_lword(nvram,  0x4C, initrd_size);
205     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
206 
207     NVRAM_set_word(nvram,   0x54, width);
208     NVRAM_set_word(nvram,   0x56, height);
209     NVRAM_set_word(nvram,   0x58, depth);
210     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
211     NVRAM_set_word(nvram,   0xFC, crc);
212 
213     return 0;
214 }
215 
prep_set_cmos_checksum(DeviceState * dev,void * opaque)216 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
217 {
218     uint16_t checksum = *(uint16_t *)opaque;
219 
220     if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
221         MC146818RtcState *rtc = MC146818_RTC(dev);
222         mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff);
223         mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff);
224         mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8);
225         mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8);
226 
227         object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
228                                   "date");
229     }
230     return 0;
231 }
232 
ibm_40p_init(MachineState * machine)233 static void ibm_40p_init(MachineState *machine)
234 {
235     const char *bios_name = machine->firmware ?: "openbios-ppc";
236     MachineClass *mc = MACHINE_GET_CLASS(machine);
237     CPUPPCState *env = NULL;
238     uint16_t cmos_checksum;
239     PowerPCCPU *cpu;
240     DeviceState *dev, *i82378_dev;
241     SysBusDevice *pcihost, *s;
242     Nvram *m48t59 = NULL;
243     PCIBus *pci_bus;
244     ISADevice *isa_dev;
245     ISABus *isa_bus;
246     void *fw_cfg;
247     MemoryRegion *bios = g_new(MemoryRegion, 1);
248     char *filename;
249     ssize_t bios_size = -1;
250     uint32_t kernel_base = 0, initrd_base = 0;
251     long kernel_size = 0, initrd_size = 0;
252     char boot_device;
253 
254     if (kvm_enabled()) {
255         error_report("machine %s does not support the KVM accelerator",
256                      MACHINE_GET_CLASS(machine)->name);
257         exit(EXIT_FAILURE);
258     }
259 
260     /* init CPU */
261     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
262     env = &cpu->env;
263     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
264         error_report("only 6xx bus is supported on this machine");
265         exit(1);
266     }
267 
268     /* Set time-base frequency to 100 Mhz */
269     cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
270     qemu_register_reset(ppc_prep_reset, cpu);
271 
272     /* allocate and load firmware */
273     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
274     if (!filename) {
275         error_report("Could not find bios image '%s'", bios_name);
276         exit(1);
277     }
278     memory_region_init_rom(bios, NULL, "bios", BIOS_SIZE, &error_fatal);
279     memory_region_add_subregion(get_system_memory(), BIOS_ADDR, bios);
280     bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
281                          ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
282     if (bios_size < 0) {
283         bios_size = load_image_targphys(filename, BIOS_ADDR, BIOS_SIZE);
284     }
285     if (bios_size < 0 || bios_size > BIOS_SIZE) {
286         error_report("Could not load bios image '%s'", filename);
287         return;
288     }
289     g_free(filename);
290 
291     /* PCI host */
292     dev = qdev_new("raven-pcihost");
293     pcihost = SYS_BUS_DEVICE(dev);
294     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
295     sysbus_realize_and_unref(pcihost, &error_fatal);
296     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
297     if (!pci_bus) {
298         error_report("could not create PCI host controller");
299         exit(1);
300     }
301 
302     /* PCI -> ISA bridge */
303     i82378_dev = DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378"));
304     qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal);
305     qdev_connect_gpio_out(i82378_dev, 0,
306                           qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
307 
308     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
309     isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
310 
311     /* Memory controller */
312     isa_dev = isa_new("rs6000-mc");
313     dev = DEVICE(isa_dev);
314     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
315     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
316 
317     /* RTC */
318     isa_dev = isa_new(TYPE_MC146818_RTC);
319     dev = DEVICE(isa_dev);
320     qdev_prop_set_int32(dev, "base_year", 1900);
321     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
322 
323     /* initialize CMOS checksums */
324     cmos_checksum = 0x6aa9;
325     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
326                        &cmos_checksum);
327 
328     /* add some more devices */
329     if (defaults_enabled()) {
330         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
331 
332         isa_dev = isa_new("cs4231a");
333         dev = DEVICE(isa_dev);
334         qdev_prop_set_uint32(dev, "iobase", 0x830);
335         qdev_prop_set_uint32(dev, "irq", 10);
336 
337         if (machine->audiodev) {
338             qdev_prop_set_string(dev, "audiodev", machine->audiodev);
339         }
340         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
341 
342         isa_dev = isa_new("pc87312");
343         dev = DEVICE(isa_dev);
344         qdev_prop_set_uint32(dev, "config", 12);
345         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
346 
347         isa_dev = isa_new("prep-systemio");
348         dev = DEVICE(isa_dev);
349         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
350         qdev_prop_set_uint32(dev, "equipment", 0xc0);
351         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
352 
353         dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
354                                        "lsi53c810"));
355         lsi53c8xx_handle_legacy_cmdline(dev);
356         qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
357 
358         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
359         pci_vga_init(pci_bus);
360 
361         /* First PCNET device at PCI_DEVFN(3, 0) */
362         pci_init_nic_in_slot(pci_bus, mc->default_nic, NULL, "3");
363         pci_init_nic_devices(pci_bus, mc->default_nic);
364     }
365 
366     /* Prepare firmware configuration for OpenBIOS */
367     dev = qdev_new(TYPE_FW_CFG_MEM);
368     fw_cfg = FW_CFG(dev);
369     qdev_prop_set_uint32(dev, "data_width", 1);
370     qdev_prop_set_bit(dev, "dma_enabled", false);
371     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
372                               OBJECT(fw_cfg));
373     s = SYS_BUS_DEVICE(dev);
374     sysbus_realize_and_unref(s, &error_fatal);
375     sysbus_mmio_map(s, 0, CFG_ADDR);
376     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
377 
378     if (machine->kernel_filename) {
379         /* load kernel */
380         kernel_base = KERNEL_LOAD_ADDR;
381         kernel_size = load_image_targphys(machine->kernel_filename,
382                                           kernel_base,
383                                           machine->ram_size - kernel_base);
384         if (kernel_size < 0) {
385             error_report("could not load kernel '%s'",
386                          machine->kernel_filename);
387             exit(1);
388         }
389         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
390         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
391         /* load initrd */
392         if (machine->initrd_filename) {
393             initrd_base = INITRD_LOAD_ADDR;
394             initrd_size = load_image_targphys(machine->initrd_filename,
395                                               initrd_base,
396                                               machine->ram_size - initrd_base);
397             if (initrd_size < 0) {
398                 error_report("could not load initial ram disk '%s'",
399                              machine->initrd_filename);
400                 exit(1);
401             }
402             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
403             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
404         }
405         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
406             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
407             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
408                              machine->kernel_cmdline);
409             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
410                               machine->kernel_cmdline);
411             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
412                            strlen(machine->kernel_cmdline) + 1);
413         }
414         boot_device = 'm';
415     } else {
416         boot_device = machine->boot_config.order[0];
417     }
418 
419     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
420     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
421     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
422 
423     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
424     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
425     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
426 
427     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
428     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
429     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
430 
431     /* Prepare firmware configuration for Open Hack'Ware */
432     if (m48t59) {
433         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
434                              boot_device,
435                              kernel_base, kernel_size,
436                              machine->kernel_cmdline,
437                              initrd_base, initrd_size,
438                              /* XXX: need an option to load a NVRAM image */
439                              0,
440                              graphic_width, graphic_height, graphic_depth);
441     }
442 }
443 
ibm_40p_machine_init(MachineClass * mc)444 static void ibm_40p_machine_init(MachineClass *mc)
445 {
446     mc->desc = "IBM RS/6000 7020 (40p)",
447     mc->init = ibm_40p_init;
448     mc->max_cpus = 1;
449     mc->default_ram_size = 128 * MiB;
450     mc->block_default_type = IF_SCSI;
451     mc->default_boot_order = "c";
452     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
453     mc->default_display = "std";
454     mc->default_nic = "pcnet";
455 
456     machine_add_audiodev_property(mc);
457 }
458 
459 DEFINE_MACHINE("40p", ibm_40p_machine_init)
460