1 /* SPDX-License-Identifier: MIT */ 2 3 /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 4 5 #ifndef __NVRM_FIFO_H__ 6 #define __NVRM_FIFO_H__ 7 #include <nvrm/nvtypes.h> 8 9 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 10 11 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32 12 13 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16 14 15 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2 16 17 #define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16 18 19 typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY { 20 NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES]; 21 NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; 22 NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; 23 NvU32 numPbdmas; 24 char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN]; 25 } NV2080_CTRL_FIFO_DEVICE_ENTRY; 26 27 #define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ 28 typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS { 29 NvU32 baseIndex; 30 NvU32 numEntries; 31 NvBool bMore; 32 // C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; 33 NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; 34 } NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS; 35 36 typedef enum 37 { 38 /* ************************************************************************* 39 * Bug 3820969 40 * THINK BEFORE CHANGING ENUM ORDER HERE. 41 * VGPU-guest uses this same ordering. Because this enum is not versioned, 42 * changing the order here WILL BREAK old-guest-on-newer-host compatibility. 43 * ************************************************************************/ 44 45 // *ENG_XYZ, e.g.: ENG_GR, ENG_CE etc., 46 ENGINE_INFO_TYPE_ENG_DESC = 0, 47 48 // HW engine ID 49 ENGINE_INFO_TYPE_FIFO_TAG, 50 51 // RM_ENGINE_TYPE_* 52 ENGINE_INFO_TYPE_RM_ENGINE_TYPE, 53 54 // 55 // runlist id (meaning varies by GPU) 56 // Valid only for Esched-driven engines 57 // 58 ENGINE_INFO_TYPE_RUNLIST, 59 60 // NV_PFIFO_INTR_MMU_FAULT_ENG_ID_* 61 ENGINE_INFO_TYPE_MMU_FAULT_ID, 62 63 // ROBUST_CHANNEL_* 64 ENGINE_INFO_TYPE_RC_MASK, 65 66 // Reset Bit Position. On Ampere, only valid if not _INVALID 67 ENGINE_INFO_TYPE_RESET, 68 69 // Interrupt Bit Position 70 ENGINE_INFO_TYPE_INTR, 71 72 // log2(MC_ENGINE_*) 73 ENGINE_INFO_TYPE_MC, 74 75 // The DEV_TYPE_ENUM for this engine 76 ENGINE_INFO_TYPE_DEV_TYPE_ENUM, 77 78 // The particular instance of this engine type 79 ENGINE_INFO_TYPE_INSTANCE_ID, 80 81 // 82 // The base address for this engine's NV_RUNLIST. Valid only on Ampere+ 83 // Valid only for Esched-driven engines 84 // 85 ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, 86 87 // 88 // If this entry is a host-driven engine. 89 // Update _isEngineInfoTypeValidForOnlyHostDriven when adding any new entry. 90 // 91 ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE, 92 93 // 94 // The index into the per-engine NV_RUNLIST registers. Valid only on Ampere+ 95 // Valid only for Esched-driven engines 96 // 97 ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID, 98 99 // 100 // The base address for this engine's NV_CHRAM registers. Valid only on 101 // Ampere+ 102 // 103 // Valid only for Esched-driven engines 104 // 105 ENGINE_INFO_TYPE_CHRAM_PRI_BASE, 106 107 // This entry added to copy data at RMCTRL_EXPORT() call for Kernel RM 108 ENGINE_INFO_TYPE_KERNEL_RM_MAX, 109 // Used for iterating the engine info table by the index passed. 110 ENGINE_INFO_TYPE_INVALID = ENGINE_INFO_TYPE_KERNEL_RM_MAX, 111 112 // Size of FIFO_ENGINE_LIST.engineData 113 ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE = ENGINE_INFO_TYPE_INVALID, 114 115 // Input-only parameter for kfifoEngineInfoXlate. 116 ENGINE_INFO_TYPE_PBDMA_ID 117 118 /* ************************************************************************* 119 * Bug 3820969 120 * THINK BEFORE CHANGING ENUM ORDER HERE. 121 * VGPU-guest uses this same ordering. Because this enum is not versioned, 122 * changing the order here WILL BREAK old-guest-on-newer-host compatibility. 123 * ************************************************************************/ 124 } ENGINE_INFO_TYPE; 125 126 #define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */ 127 typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS { 128 NvU32 size; 129 } NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS; 130 131 #define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40 132 133 typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO { 134 NvU32 engDesc; 135 NvU32 ctxAttr; 136 NvU32 ctxBufferSize; 137 NvU32 addrSpaceList; 138 NvU32 registerBase; 139 } NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO; 140 141 #define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ 142 typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { 143 NvU32 numConstructedFalcons; 144 NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS]; 145 } NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS; 146 147 #define NV_MAX_SUBDEVICES 8 148 149 typedef struct NV_MEMORY_DESC_PARAMS { 150 NV_DECLARE_ALIGNED(NvU64 base, 8); 151 NV_DECLARE_ALIGNED(NvU64 size, 8); 152 NvU32 addressSpace; 153 NvU32 cacheAttrib; 154 } NV_MEMORY_DESC_PARAMS; 155 156 #define CC_CHAN_ALLOC_IV_SIZE_DWORD 3U 157 158 #define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U 159 160 typedef struct NV_CHANNEL_ALLOC_PARAMS { 161 162 NvHandle hObjectError; // error context DMA 163 NvHandle hObjectBuffer; // no longer used 164 NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO 165 NvU32 gpFifoEntries; // number of GP FIFO entries 166 167 NvU32 flags; 168 169 170 NvHandle hContextShare; // context share handle 171 NvHandle hVASpace; // VASpace for the channel 172 173 // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 174 NvHandle hUserdMemory[NV_MAX_SUBDEVICES]; 175 176 // offset to beginning of UserD within hUserdMemory[x] 177 NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8); 178 179 // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated 180 NvU32 engineType; 181 // Channel identifier that is unique for the duration of a RM session 182 NvU32 cid; 183 // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods 184 NvU32 subDeviceId; 185 NvHandle hObjectEccError; // ECC error context DMA 186 187 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); 188 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); 189 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); 190 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8); 191 192 NvHandle hPhysChannelGroup; // reserved 193 NvU32 internalFlags; // reserved 194 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved 195 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved 196 NvU32 ProcessID; // reserved 197 NvU32 SubProcessID; // reserved 198 199 // IV used for CPU-side encryption / GPU-side decryption. 200 NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved 201 // IV used for CPU-side decryption / GPU-side encryption. 202 NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved 203 // Nonce used CPU-side signing / GPU-side signature verification. 204 NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved 205 } NV_CHANNEL_ALLOC_PARAMS; 206 207 typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; 208 209 #define NVOS04_FLAGS_CHANNEL_TYPE 1:0 210 #define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 211 #define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE 212 #define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE 213 #define NVOS04_FLAGS_VPR 2:2 214 #define NVOS04_FLAGS_VPR_FALSE 0x00000000 215 #define NVOS04_FLAGS_VPR_TRUE 0x00000001 216 #define NVOS04_FLAGS_CC_SECURE 2:2 217 #define NVOS04_FLAGS_CC_SECURE_FALSE 0x00000000 218 #define NVOS04_FLAGS_CC_SECURE_TRUE 0x00000001 219 #define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 220 #define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 221 #define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 222 #define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 223 #define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 224 #define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 225 #define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 226 #define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 227 #define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 228 #define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 229 #define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 230 #define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 231 #define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 232 #define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 233 #define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 234 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 235 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 236 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 237 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 238 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 239 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 240 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 241 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 242 #define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 243 #define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 244 #define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 245 #define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 246 #define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 247 #define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 248 #define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 249 #define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 250 #define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 251 #define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 252 #define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 253 #define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 254 #define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 255 #define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 256 #define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 257 #define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 258 #define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 259 #define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 260 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 261 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 262 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 263 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 264 #define NVOS04_FLAGS_MAP_CHANNEL 30:30 265 #define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 266 #define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 267 #define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 268 #define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 269 #define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 270 271 typedef enum { 272 /*! 273 * Initial state as passed in NV_CHANNEL_ALLOC_PARAMS by 274 * kernel CPU-RM clients. 275 */ 276 ERROR_NOTIFIER_TYPE_UNKNOWN = 0, 277 /*! @brief Error notifier is explicitly not set. 278 * 279 * The corresponding hErrorContext or hEccErrorContext must be 280 * NV01_NULL_OBJECT. 281 */ 282 ERROR_NOTIFIER_TYPE_NONE, 283 /*! @brief Error notifier is a ContextDma */ 284 ERROR_NOTIFIER_TYPE_CTXDMA, 285 /*! @brief Error notifier is a NvNotification array in sysmem/vidmem */ 286 ERROR_NOTIFIER_TYPE_MEMORY 287 } ErrorNotifierType; 288 289 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE 1:0 290 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_USER 0x0 291 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_ADMIN 0x1 292 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_KERNEL 0x2 293 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE 3:2 294 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_UNKNOWN ERROR_NOTIFIER_TYPE_UNKNOWN 295 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_NONE ERROR_NOTIFIER_TYPE_NONE 296 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_CTXDMA ERROR_NOTIFIER_TYPE_CTXDMA 297 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ERROR_NOTIFIER_TYPE_MEMORY ERROR_NOTIFIER_TYPE_MEMORY 298 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE 5:4 299 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_UNKNOWN ERROR_NOTIFIER_TYPE_UNKNOWN 300 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_NONE ERROR_NOTIFIER_TYPE_NONE 301 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_CTXDMA ERROR_NOTIFIER_TYPE_CTXDMA 302 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_ECC_ERROR_NOTIFIER_TYPE_MEMORY ERROR_NOTIFIER_TYPE_MEMORY 303 304 #define NVA06F_CTRL_CMD_BIND (0xa06f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID" */ 305 typedef struct NVA06F_CTRL_BIND_PARAMS { 306 NvU32 engineType; 307 } NVA06F_CTRL_BIND_PARAMS; 308 309 #define NVA06F_CTRL_CMD_GPFIFO_SCHEDULE (0xa06f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */ 310 typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS { 311 NvBool bEnable; 312 NvBool bSkipSubmit; 313 } NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS; 314 315 #define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U 316 317 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { 318 NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8); 319 NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8); 320 NV_DECLARE_ALIGNED(NvU64 size, 8); 321 NvU32 physAttr; 322 NvU16 bufferId; 323 NvU8 bInitialize; 324 NvU8 bNonmapped; 325 } NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY; 326 327 #define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ 328 typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS { 329 NvU32 engineType; 330 NvHandle hClient; 331 NvU32 ChID; 332 NvHandle hChanClient; 333 NvHandle hObject; 334 NvHandle hVirtMemory; 335 NV_DECLARE_ALIGNED(NvU64 virtAddress, 8); 336 NV_DECLARE_ALIGNED(NvU64 size, 8); 337 NvU32 entryCount; 338 // C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES]; 339 NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8); 340 } NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS; 341 342 typedef struct rpc_rc_triggered_v17_02 343 { 344 NvU32 nv2080EngineType; 345 NvU32 chid; 346 NvU32 exceptType; 347 NvU32 scope; 348 NvU16 partitionAttributionId; 349 } rpc_rc_triggered_v17_02; 350 #endif 351