1 /* SPDX-License-Identifier: MIT */ 2 3 /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 4 5 #ifndef __NVRM_VMM_H__ 6 #define __NVRM_VMM_H__ 7 #include <nvrm/nvtypes.h> 8 9 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 10 11 #define FERMI_VASPACE_A (0x000090f1) 12 13 typedef struct 14 { 15 NvU32 index; 16 NvV32 flags; 17 NvU64 vaSize NV_ALIGN_BYTES(8); 18 NvU64 vaStartInternal NV_ALIGN_BYTES(8); 19 NvU64 vaLimitInternal NV_ALIGN_BYTES(8); 20 NvU32 bigPageSize; 21 NvU64 vaBase NV_ALIGN_BYTES(8); 22 } NV_VASPACE_ALLOCATION_PARAMETERS; 23 24 #define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default 25 26 #define NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED BIT(3) 27 28 #define SPLIT_VAS_SERVER_RM_MANAGED_VA_START 0x100000000ULL // 4GB 29 #define SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE 0x20000000ULL // 512MB 30 31 #define GMMU_FMT_MAX_LEVELS 6U 32 33 #define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */ 34 typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS { 35 /*! 36 * [in] GPU sub-device handle - this API only supports unicast. 37 * Pass 0 to use subDeviceId instead. 38 */ 39 NvHandle hSubDevice; 40 41 /*! 42 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. 43 */ 44 NvU32 subDeviceId; 45 46 /*! 47 * [in] Page size (VA coverage) of the level to reserve. 48 * This need not be a leaf (page table) page size - it can be 49 * the coverage of an arbitrary level (including root page directory). 50 */ 51 NV_DECLARE_ALIGNED(NvU64 pageSize, 8); 52 53 /*! 54 * [in] First GPU virtual address of the range to reserve. 55 * This must be aligned to pageSize. 56 */ 57 NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8); 58 59 /*! 60 * [in] Last GPU virtual address of the range to reserve. 61 * This (+1) must be aligned to pageSize. 62 */ 63 NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8); 64 65 /*! 66 * [in] Number of PDE levels to copy. 67 */ 68 NvU32 numLevelsToCopy; 69 70 /*! 71 * [in] Per-level information. 72 */ 73 struct { 74 /*! 75 * Physical address of this page level instance. 76 */ 77 NV_DECLARE_ALIGNED(NvU64 physAddress, 8); 78 79 /*! 80 * Size in bytes allocated for this level instance. 81 */ 82 NV_DECLARE_ALIGNED(NvU64 size, 8); 83 84 /*! 85 * Aperture in which this page level instance resides. 86 */ 87 NvU32 aperture; 88 89 /*! 90 * Page shift corresponding to the level 91 */ 92 NvU8 pageShift; 93 } levels[GMMU_FMT_MAX_LEVELS]; 94 } NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS; 95 96 #define NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY (0x801813U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ 97 ID << 8) | NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ 98 99 typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS { 100 NV_DECLARE_ALIGNED(NvU64 physAddress, 8); 101 NvU32 numEntries; 102 NvU32 flags; 103 NvHandle hVASpace; 104 NvU32 chId; 105 NvU32 subDeviceId; // ID+1, 0 for BC 106 NvU32 pasid; 107 } NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS; 108 109 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE 1:0 110 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM (0x00000000U) 111 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH (0x00000001U) 112 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH (0x00000002U) 113 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES 2:2 114 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE (0x00000000U) 115 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE (0x00000001U) 116 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS 3:3 117 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE (0x00000000U) 118 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE (0x00000001U) 119 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY 4:4 120 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE (0x00000000U) 121 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE (0x00000001U) 122 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE 5:5 123 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE (0x00000000U) 124 #define NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE (0x00000001U) 125 126 #define NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY (0x801814U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID" */ 127 128 typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS { 129 NvHandle hVASpace; 130 NvU32 subDeviceId; // ID+1, 0 for BC 131 } NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS; 132 #endif 133