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Searched defs:NAME (Results 1 – 25 of 55) sorted by relevance

123

/qemu/tests/tcg/hexagon/
H A Dusr.c51 #define FUNC_x_OP_x(RESTYPE, SRCTYPE, NAME, INSN) \ argument
66 #define FUNC_R_OP_R(NAME, INSN) \ argument
69 #define FUNC_R_OP_P(NAME, INSN) \ argument
72 #define FUNC_P_OP_P(NAME, INSN) \ argument
75 #define FUNC_P_OP_R(NAME, INSN) \ argument
82 #define FUNC_xp_OP_x(RESTYPE, SRCTYPE, NAME, INSN) \ argument
100 #define FUNC_Rp_OP_R(NAME, INSN) \ argument
104 #define FUNC_x_OP_xx(RESTYPE, SRC1TYPE, SRC2TYPE, NAME, INSN) \ argument
119 #define FUNC_P_OP_PP(NAME, INSN) \ argument
122 #define FUNC_R_OP_PP(NAME, INSN) \ argument
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H A Dload_align.c62 #define TEST_io(NAME, SZ, SIZE, EXP1, EXP2, EXP3, EXP4) \ argument
97 #define TEST_ur(NAME, SZ, SHIFT, RES1, RES2, RES3, RES4) \ argument
131 #define TEST_ap(NAME, SZ, SIZE, RES1, RES2, RES3, RES4) \ argument
173 #define TEST_pr(NAME, SZ, SIZE, RES1, RES2, RES3, RES4) \ argument
216 #define TEST_pbr(NAME, SZ, RES1, RES2, RES3, RES4) \ argument
251 #define TEST_pi(NAME, SZ, INC, RES1, RES2, RES3, RES4) \ argument
295 #define TEST_pci(NAME, SZ, LEN, INC, RES1, RES2, RES3, RES4) \ argument
340 #define TEST_pcr(NAME, SZ, SIZE, LEN, INC, RES1, RES2, RES3, RES4) \ argument
H A Dload_unpack.c65 #define TEST_io(NAME, TYPE, SIGN, SIZE, EXT, EXP1, EXP2, EXP3, EXP4) \ argument
106 #define TEST_ur(NAME, TYPE, SIGN, SHIFT, EXT, RES1, RES2, RES3, RES4) \ argument
145 #define TEST_ap(NAME, TYPE, SIGN, SIZE, EXT, RES1, RES2, RES3, RES4) \ argument
192 #define TEST_pr(NAME, TYPE, SIGN, SIZE, EXT, RES1, RES2, RES3, RES4) \ argument
240 #define TEST_pbr(NAME, TYPE, SIGN, EXT, RES1, RES2, RES3, RES4) \ argument
280 #define TEST_pi(NAME, TYPE, SIGN, INC, EXT, RES1, RES2, RES3, RES4) \ argument
329 #define TEST_pci(NAME, TYPE, SIGN, LEN, INC, EXT, RES1, RES2, RES3, RES4) \ argument
379 #define TEST_pcr(NAME, TYPE, SIGN, SIZE, LEN, INC, \ argument
H A Dhvx_misc.h97 #define TEST_VEC_OP1(NAME, ASM, EL, FIELD, FIELDSZ, OP) \ argument
115 #define TEST_VEC_OP2(NAME, ASM, EL, FIELD, FIELDSZ, OP) \ argument
151 #define TEST_PRED_OP2(NAME, ASM, OP, INV) \ argument
H A Dmem_noshuf.c33 #define MEM_NOSHUF32(NAME, ST_TYPE, LD_TYPE, ST_OP, LD_OP) \ argument
47 #define MEM_NOSHUF64(NAME, ST_TYPE, LD_TYPE, ST_OP, LD_OP) \ argument
/qemu/hw/display/
H A Dpl110_template.h17 #define NAME glue(lblp_, BORDER) macro
22 #define NAME glue(bbbp_, BORDER) macro
28 #define NAME glue(lbbp_, BORDER) macro
38 static void glue(pl110_draw_line1_,NAME)(void *opaque, uint8_t *d, const uint8_t *src, int width, i… in glue() argument
66 static void glue(pl110_draw_line2_,NAME)(void *opaque, uint8_t *d, const uint8_t *src, int width, i… in glue() argument
94 static void glue(pl110_draw_line4_,NAME)(void *opaque, uint8_t *d, const uint8_t *src, int width, i… in glue() argument
122 static void glue(pl110_draw_line8_,NAME)(void *opaque, uint8_t *d, const uint8_t *src, int width, i… in glue() argument
146 static void glue(pl110_draw_line16_,NAME)(void *opaque, uint8_t *d, const uint8_t *src, int width, … in glue() argument
192 static void glue(pl110_draw_line32_,NAME)(void *opaque, uint8_t *d, const uint8_t *src, int width, … in glue() argument
222 static void glue(pl110_draw_line16_555_,NAME)(void *opaque, uint8_t *d, const uint8_t *src, int wid… in glue() argument
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/qemu/target/loongarch/
H A Dcsr.c10 #define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ argument
17 #define CSR_OFF_ARRAY(NAME, N) \ argument
24 #define CSR_OFF_FLAGS(NAME, FL) CSR_OFF_FUNCS(NAME, FL, NULL, NULL) argument
25 #define CSR_OFF(NAME) CSR_OFF_FLAGS(NAME, 0) argument
/qemu/target/loongarch/tcg/
H A Dvec_helper.c17 #define DO_ODD_EVEN(NAME, BIT, E1, E2, DO_OP) \ argument
104 #define DO_EVEN(NAME, BIT, E1, E2, DO_OP) \ argument
119 #define DO_ODD(NAME, BIT, E1, E2, DO_OP) \ argument
278 #define DO_EVEN_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \ argument
294 #define DO_ODD_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \ argument
346 #define DO_3OP(NAME, BIT, E, DO_OP) \ argument
386 #define DO_VADDA(NAME, BIT, E) \ argument
405 #define VMINMAXI(NAME, BIT, E, DO_OP) \ argument
436 #define DO_VMUH(NAME, BIT, E1, E2, DO_OP) \ argument
513 #define VMADDSUB(NAME, BIT, E, DO_OP) \ argument
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/qemu/include/accel/tcg/
H A Dcpu-ldst-common.h58 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ argument
64 #define GEN_ATOMIC_HELPER_ALL(NAME) \ argument
73 #define GEN_ATOMIC_HELPER_ALL(NAME) \ argument
/qemu/target/arm/tcg/
H A Dsve_ldst_internal.h42 #define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \ argument
46 #define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \ argument
50 #define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \ argument
58 #define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ argument
66 #define DO_LD_PRIM_1(NAME, H, TE, TM) \ argument
78 #define DO_ST_PRIM_1(NAME, H, TE, TM) \ argument
87 #define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ argument
93 #define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ argument
H A Dsve_helper.c126 #define LOGICAL_PPPP(NAME, FUNC) \ argument
173 #define DO_ZPZZ(NAME, TYPE, H, OP) \ in LOGICAL_PPPP() argument
191 #define DO_ZPZZ_D(NAME, TYPE, OP) \ argument
668 #define DO_ZPZZ_PAIR(NAME, TYPE, H, OP) \ in DO_ZPZZ() argument
692 #define DO_ZPZZ_PAIR_D(NAME, TYPE, OP) \ argument
738 #define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP) \ argument
788 #define DO_ZPZW(NAME, TYPE, TYPEW, H, OP) \ argument
821 #define DO_ZPZ(NAME, TYPE, H, OP) \ argument
838 #define DO_ZPZ_D(NAME, TYPE, OP) \ argument
1003 #define DO_ZZW(NAME, TYPE, TYPEW, H, OP) \ argument
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H A Dvec_helper.c811 #define DO_DOT(NAME, TYPED, TYPEN, TYPEM) \ argument
834 #define DO_DOT_IDX(NAME, TYPED, TYPEN, TYPEM, HD) \ in DO_DOT() argument
1226 #define DO_2OP(NAME, FUNC, TYPE) \ argument
1407 #define DO_3OP(NAME, FUNC, TYPE) \ argument
1601 #define DO_MULADD(NAME, FUNC, TYPE) \ argument
1635 #define DO_MUL_IDX(NAME, TYPE, H) \ in DO_MULADD() argument
1657 #define DO_MLA_IDX(NAME, TYPE, OP, H) \ argument
1683 #define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \ argument
1727 #define DO_FMLA_IDX(NAME, TYPE, H, NEGX, NEGF) \ argument
1759 #define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \ argument
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/qemu/ui/
H A Dvnc-enc-hextile-template.h5 #define NAME CONCAT(generic_, BPP) macro
7 #define NAME BPP macro
12 static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, in CONCAT() argument
/qemu/target/riscv/
H A Dvector_internals.h143 #define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ argument
150 #define GEN_VEXT_V(NAME, ESZ) \ argument
182 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ argument
195 #define GEN_VEXT_VV(NAME, ESZ) \ argument
210 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ argument
222 #define GEN_VEXT_VX(NAME, ESZ) \ argument
H A Dvector_helper.c170 #define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ argument
191 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ in GEN_VEXT_LD_ELEM() argument
305 #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \ argument
320 #define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \ in GEN_VEXT_LD_STRIDE() argument
469 #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \ argument
490 #define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN_TLB, STORE_FN_HOST) \ in GEN_VEXT_LD_US() argument
538 #define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \ argument
587 #define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \ argument
612 #define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \ in GEN_VEXT_LD_INDEX() argument
779 #define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \ argument
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/qemu/target/tricore/
H A Dhelper.c153 #define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ argument
162 #define FIELD_GETTER(NAME, REG, FIELD) \ argument
168 #define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ argument
177 #define FIELD_SETTER(NAME, REG, FIELD) \ argument
H A Dcpu.h49 #define R(ADDR, NAME, FEATURE) uint32_t NAME; argument
50 #define A(ADDR, NAME, FEATURE) uint32_t NAME; argument
51 #define E(ADDR, NAME, FEATURE) uint32_t NAME; argument
/qemu/linux-headers/linux/
H A Dstddef.h33 #define __struct_group(TAG, NAME, ATTRS, MEMBERS...) \ argument
54 #define __DECLARE_FLEX_ARRAY(TYPE, NAME) \ argument
/qemu/accel/tcg/
H A Dtcg-runtime.h72 #define GEN_ATOMIC_HELPERS(NAME) \ argument
/qemu/target/s390x/tcg/
H A Dvec_fpu_helper.c225 #define DEF_GVEC_VOP2_FN(NAME, FN, BITS) \ argument
236 #define DEF_GVEC_VOP2_32(NAME) \ argument
239 #define DEF_GVEC_VOP2_64(NAME) \ argument
242 #define DEF_GVEC_VOP2(NAME, OP) \ argument
320 #define DEF_GVEC_VOP3_B(NAME, OP, BITS) \ argument
329 #define DEF_GVEC_VOP3(NAME, OP) \ argument
399 #define DEF_GVEC_WFC_B(NAME, SIGNAL, BITS) \ argument
406 #define DEF_GVEC_WFC(NAME, SIGNAL) \ argument
500 #define DEF_GVEC_VFC_B(NAME, OP, BITS) \ argument
521 #define DEF_GVEC_VFC(NAME, OP) \ argument
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/qemu/target/hexagon/
H A Dattribs.h25 #define DEF_ATTRIB(NAME, ...) A_##NAME, argument
/qemu/audio/
H A Ddsound_template.h25 #define NAME "capture buffer" macro
35 #define NAME "playback buffer" macro
H A Drate_template.h30 void NAME (void *opaque, struct st_sample *ibuf, struct st_sample *obuf, in NAME() function
/qemu/target/mips/tcg/
H A Dmsa_translate.c172 #define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ argument
178 #define TRANS_DF_iv(NAME, trans_func, gen_func) \ argument
181 #define TRANS_DF_ii(NAME, trans_func, gen_func) \ argument
184 #define TRANS_DF_iii(NAME, trans_func, gen_func) \ argument
187 #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ argument
/qemu/target/microblaze/
H A Dtranslate.c253 #define DO_TYPEA(NAME, SE, FN) \ argument
257 #define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ argument
261 #define DO_TYPEA0(NAME, SE, FN) \ argument
265 #define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \ argument
269 #define DO_TYPEBI(NAME, SE, FNI) \ argument
273 #define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \ argument
277 #define DO_TYPEBV(NAME, SE, FN) \ argument
281 #define ENV_WRAPPER2(NAME, HELPER) \ argument
285 #define ENV_WRAPPER3(NAME, HELPER) \ argument
1096 #define DO_BR(NAME, NAMEI, DELAY, ABS, LINK) \ argument
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