1 // Copyright 2024, Linaro Limited 2 // Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> 3 // SPDX-License-Identifier: GPL-2.0-or-later 4 5 //! Device registers exposed as typed structs which are backed by arbitrary 6 //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. 7 8 use bilge::prelude::*; 9 use qemu_api::impl_vmstate_bitsized; 10 11 /// Offset of each register from the base memory address of the device. 12 /// 13 /// # Source 14 /// ARM DDI 0183G, Table 3-1 p.3-3 15 #[doc(alias = "offset")] 16 #[allow(non_camel_case_types)] 17 #[repr(u64)] 18 #[derive(Debug, Eq, PartialEq, qemu_api_macros::TryInto)] 19 pub enum RegisterOffset { 20 /// Data Register 21 /// 22 /// A write to this register initiates the actual data transmission 23 #[doc(alias = "UARTDR")] 24 DR = 0x000, 25 /// Receive Status Register or Error Clear Register 26 #[doc(alias = "UARTRSR")] 27 #[doc(alias = "UARTECR")] 28 RSR = 0x004, 29 /// Flag Register 30 /// 31 /// A read of this register shows if transmission is complete 32 #[doc(alias = "UARTFR")] 33 FR = 0x018, 34 /// Fractional Baud Rate Register 35 /// 36 /// responsible for baud rate speed 37 #[doc(alias = "UARTFBRD")] 38 FBRD = 0x028, 39 /// `IrDA` Low-Power Counter Register 40 #[doc(alias = "UARTILPR")] 41 ILPR = 0x020, 42 /// Integer Baud Rate Register 43 /// 44 /// Responsible for baud rate speed 45 #[doc(alias = "UARTIBRD")] 46 IBRD = 0x024, 47 /// line control register (data frame format) 48 #[doc(alias = "UARTLCR_H")] 49 LCR_H = 0x02C, 50 /// Toggle UART, transmission or reception 51 #[doc(alias = "UARTCR")] 52 CR = 0x030, 53 /// Interrupt FIFO Level Select Register 54 #[doc(alias = "UARTIFLS")] 55 FLS = 0x034, 56 /// Interrupt Mask Set/Clear Register 57 #[doc(alias = "UARTIMSC")] 58 IMSC = 0x038, 59 /// Raw Interrupt Status Register 60 #[doc(alias = "UARTRIS")] 61 RIS = 0x03C, 62 /// Masked Interrupt Status Register 63 #[doc(alias = "UARTMIS")] 64 MIS = 0x040, 65 /// Interrupt Clear Register 66 #[doc(alias = "UARTICR")] 67 ICR = 0x044, 68 /// DMA control Register 69 #[doc(alias = "UARTDMACR")] 70 DMACR = 0x048, 71 ///// Reserved, offsets `0x04C` to `0x07C`. 72 //Reserved = 0x04C, 73 } 74 75 /// Receive Status Register / Data Register common error bits 76 /// 77 /// The `UARTRSR` register is updated only when a read occurs 78 /// from the `UARTDR` register with the same status information 79 /// that can also be obtained by reading the `UARTDR` register 80 #[bitsize(8)] 81 #[derive(Clone, Copy, Default, DebugBits, FromBits)] 82 pub struct Errors { 83 pub framing_error: bool, 84 pub parity_error: bool, 85 pub break_error: bool, 86 pub overrun_error: bool, 87 _reserved_unpredictable: u4, 88 } 89 90 // TODO: FIFO Mode has different semantics 91 /// Data Register, `UARTDR` 92 /// 93 /// The `UARTDR` register is the data register. 94 /// 95 /// For words to be transmitted: 96 /// 97 /// - if the FIFOs are enabled, data written to this location is pushed onto the 98 /// transmit 99 /// FIFO 100 /// - if the FIFOs are not enabled, data is stored in the transmitter holding 101 /// register (the 102 /// bottom word of the transmit FIFO). 103 /// 104 /// The write operation initiates transmission from the UART. The data is 105 /// prefixed with a start bit, appended with the appropriate parity bit 106 /// (if parity is enabled), and a stop bit. The resultant word is then 107 /// transmitted. 108 /// 109 /// For received words: 110 /// 111 /// - if the FIFOs are enabled, the data byte and the 4-bit status (break, 112 /// frame, parity, 113 /// and overrun) is pushed onto the 12-bit wide receive FIFO 114 /// - if the FIFOs are not enabled, the data byte and status are stored in the 115 /// receiving 116 /// holding register (the bottom word of the receive FIFO). 117 /// 118 /// The received data byte is read by performing reads from the `UARTDR` 119 /// register along with the corresponding status information. The status 120 /// information can also be read by a read of the `UARTRSR/UARTECR` 121 /// register. 122 /// 123 /// # Note 124 /// 125 /// You must disable the UART before any of the control registers are 126 /// reprogrammed. When the UART is disabled in the middle of 127 /// transmission or reception, it completes the current character before 128 /// stopping. 129 /// 130 /// # Source 131 /// ARM DDI 0183G 3.3.1 Data Register, UARTDR 132 #[bitsize(32)] 133 #[derive(Clone, Copy, Default, DebugBits, FromBits)] 134 #[doc(alias = "UARTDR")] 135 pub struct Data { 136 pub data: u8, 137 pub errors: Errors, 138 _reserved: u16, 139 } 140 impl_vmstate_bitsized!(Data); 141 142 impl Data { 143 // bilge is not very const-friendly, unfortunately 144 pub const BREAK: Self = Self { value: 1 << 10 }; 145 } 146 147 // TODO: FIFO Mode has different semantics 148 /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` 149 /// 150 /// The UARTRSR/UARTECR register is the receive status register/error clear 151 /// register. Receive status can also be read from the `UARTRSR` 152 /// register. If the status is read from this register, then the status 153 /// information for break, framing and parity corresponds to the 154 /// data character read from the [Data register](Data), `UARTDR` prior to 155 /// reading the UARTRSR register. The status information for overrun is 156 /// set immediately when an overrun condition occurs. 157 /// 158 /// 159 /// # Note 160 /// The received data character must be read first from the [Data 161 /// Register](Data), `UARTDR` before reading the error status associated 162 /// with that data character from the `UARTRSR` register. This read 163 /// sequence cannot be reversed, because the `UARTRSR` register is 164 /// updated only when a read occurs from the `UARTDR` register. However, 165 /// the status information can also be obtained by reading the `UARTDR` 166 /// register 167 /// 168 /// # Source 169 /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, 170 /// UARTRSR/UARTECR 171 #[bitsize(32)] 172 #[derive(Clone, Copy, DebugBits, FromBits)] 173 pub struct ReceiveStatusErrorClear { 174 pub errors: Errors, 175 _reserved_unpredictable: u24, 176 } 177 impl_vmstate_bitsized!(ReceiveStatusErrorClear); 178 179 impl ReceiveStatusErrorClear { set_from_data(&mut self, data: Data)180 pub fn set_from_data(&mut self, data: Data) { 181 self.set_errors(data.errors()); 182 } 183 reset(&mut self)184 pub fn reset(&mut self) { 185 // All the bits are cleared to 0 on reset. 186 *self = Self::default(); 187 } 188 } 189 190 impl Default for ReceiveStatusErrorClear { default() -> Self191 fn default() -> Self { 192 0.into() 193 } 194 } 195 196 #[bitsize(32)] 197 #[derive(Clone, Copy, DebugBits, FromBits)] 198 /// Flag Register, `UARTFR` 199 #[doc(alias = "UARTFR")] 200 pub struct Flags { 201 /// CTS Clear to send. This bit is the complement of the UART clear to 202 /// send, `nUARTCTS`, modem status input. That is, the bit is 1 203 /// when `nUARTCTS` is LOW. 204 pub clear_to_send: bool, 205 /// DSR Data set ready. This bit is the complement of the UART data set 206 /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 when 207 /// `nUARTDSR` is LOW. 208 pub data_set_ready: bool, 209 /// DCD Data carrier detect. This bit is the complement of the UART data 210 /// carrier detect, `nUARTDCD`, modem status input. That is, the bit is 211 /// 1 when `nUARTDCD` is LOW. 212 pub data_carrier_detect: bool, 213 /// BUSY UART busy. If this bit is set to 1, the UART is busy 214 /// transmitting data. This bit remains set until the complete 215 /// byte, including all the stop bits, has been sent from the 216 /// shift register. This bit is set as soon as the transmit FIFO 217 /// becomes non-empty, regardless of whether the UART is enabled 218 /// or not. 219 pub busy: bool, 220 /// RXFE Receive FIFO empty. The meaning of this bit depends on the 221 /// state of the FEN bit in the UARTLCR_H register. If the FIFO 222 /// is disabled, this bit is set when the receive holding 223 /// register is empty. If the FIFO is enabled, the RXFE bit is 224 /// set when the receive FIFO is empty. 225 pub receive_fifo_empty: bool, 226 /// TXFF Transmit FIFO full. The meaning of this bit depends on the 227 /// state of the FEN bit in the UARTLCR_H register. If the FIFO 228 /// is disabled, this bit is set when the transmit holding 229 /// register is full. If the FIFO is enabled, the TXFF bit is 230 /// set when the transmit FIFO is full. 231 pub transmit_fifo_full: bool, 232 /// RXFF Receive FIFO full. The meaning of this bit depends on the state 233 /// of the FEN bit in the UARTLCR_H register. If the FIFO is 234 /// disabled, this bit is set when the receive holding register 235 /// is full. If the FIFO is enabled, the RXFF bit is set when 236 /// the receive FIFO is full. 237 pub receive_fifo_full: bool, 238 /// Transmit FIFO empty. The meaning of this bit depends on the state of 239 /// the FEN bit in the [Line Control register](LineControl), 240 /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the 241 /// transmit holding register is empty. If the FIFO is enabled, 242 /// the TXFE bit is set when the transmit FIFO is empty. This 243 /// bit does not indicate if there is data in the transmit shift 244 /// register. 245 pub transmit_fifo_empty: bool, 246 /// `RI`, is `true` when `nUARTRI` is `LOW`. 247 pub ring_indicator: bool, 248 _reserved_zero_no_modify: u23, 249 } 250 impl_vmstate_bitsized!(Flags); 251 252 impl Flags { reset(&mut self)253 pub fn reset(&mut self) { 254 *self = Self::default(); 255 } 256 } 257 258 impl Default for Flags { default() -> Self259 fn default() -> Self { 260 let mut ret: Self = 0.into(); 261 // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1 262 ret.set_receive_fifo_empty(true); 263 ret.set_transmit_fifo_empty(true); 264 ret 265 } 266 } 267 268 #[bitsize(32)] 269 #[derive(Clone, Copy, DebugBits, FromBits)] 270 /// Line Control Register, `UARTLCR_H` 271 #[doc(alias = "UARTLCR_H")] 272 pub struct LineControl { 273 /// BRK Send break. 274 /// 275 /// If this bit is set to `1`, a low-level is continually output on the 276 /// `UARTTXD` output, after completing transmission of the 277 /// current character. For the proper execution of the break command, 278 /// the software must set this bit for at least two complete 279 /// frames. For normal use, this bit must be cleared to `0`. 280 pub send_break: bool, 281 /// 1 PEN Parity enable: 282 /// 283 /// - 0 = parity is disabled and no parity bit added to the data frame 284 /// - 1 = parity checking and generation is enabled. 285 /// 286 /// See Table 3-11 on page 3-14 for the parity truth table. 287 pub parity_enabled: bool, 288 /// EPS Even parity select. Controls the type of parity the UART uses 289 /// during transmission and reception: 290 /// - 0 = odd parity. The UART generates or checks for an odd number of 1s 291 /// in the data and parity bits. 292 /// - 1 = even parity. The UART generates or checks for an even number of 1s 293 /// in the data and parity bits. 294 /// This bit has no effect when the `PEN` bit disables parity checking 295 /// and generation. See Table 3-11 on page 3-14 for the parity 296 /// truth table. 297 pub parity: Parity, 298 /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits 299 /// are transmitted at the end of the frame. The receive 300 /// logic does not check for two stop bits being received. 301 pub two_stops_bits: bool, 302 /// FEN Enable FIFOs: 303 /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 304 /// 1-byte-deep holding registers 1 = transmit and receive FIFO 305 /// buffers are enabled (FIFO mode). 306 pub fifos_enabled: Mode, 307 /// WLEN Word length. These bits indicate the number of data bits 308 /// transmitted or received in a frame as follows: b11 = 8 bits 309 /// b10 = 7 bits 310 /// b01 = 6 bits 311 /// b00 = 5 bits. 312 pub word_length: WordLength, 313 /// 7 SPS Stick parity select. 314 /// 0 = stick parity is disabled 315 /// 1 = either: 316 /// • if the EPS bit is 0 then the parity bit is transmitted and checked 317 /// as a 1 • if the EPS bit is 1 then the parity bit is 318 /// transmitted and checked as a 0. This bit has no effect when 319 /// the PEN bit disables parity checking and generation. See Table 3-11 320 /// on page 3-14 for the parity truth table. 321 pub sticky_parity: bool, 322 /// 31:8 - Reserved, do not modify, read as zero. 323 _reserved_zero_no_modify: u24, 324 } 325 impl_vmstate_bitsized!(LineControl); 326 327 impl LineControl { reset(&mut self)328 pub fn reset(&mut self) { 329 // All the bits are cleared to 0 when reset. 330 *self = 0.into(); 331 } 332 } 333 334 impl Default for LineControl { default() -> Self335 fn default() -> Self { 336 0.into() 337 } 338 } 339 340 #[bitsize(1)] 341 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] 342 /// `EPS` "Even parity select", field of [Line Control 343 /// register](LineControl). 344 pub enum Parity { 345 /// - 0 = odd parity. The UART generates or checks for an odd number of 1s 346 /// in the data and parity bits. 347 Odd = 0, 348 /// - 1 = even parity. The UART generates or checks for an even number of 1s 349 /// in the data and parity bits. 350 Even = 1, 351 } 352 353 #[bitsize(1)] 354 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] 355 /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control 356 /// register](LineControl). 357 pub enum Mode { 358 /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 359 /// 1-byte-deep holding registers 360 Character = 0, 361 /// 1 = transmit and receive FIFO buffers are enabled (FIFO mode). 362 FIFO = 1, 363 } 364 365 #[bitsize(2)] 366 #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] 367 /// `WLEN` Word length, field of [Line Control register](LineControl). 368 /// 369 /// These bits indicate the number of data bits transmitted or received in a 370 /// frame as follows: 371 pub enum WordLength { 372 /// b11 = 8 bits 373 _8Bits = 0b11, 374 /// b10 = 7 bits 375 _7Bits = 0b10, 376 /// b01 = 6 bits 377 _6Bits = 0b01, 378 /// b00 = 5 bits. 379 _5Bits = 0b00, 380 } 381 382 /// Control Register, `UARTCR` 383 /// 384 /// The `UARTCR` register is the control register. All the bits are cleared 385 /// to `0` on reset except for bits `9` and `8` that are set to `1`. 386 /// 387 /// # Source 388 /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 389 #[bitsize(32)] 390 #[doc(alias = "UARTCR")] 391 #[derive(Clone, Copy, DebugBits, FromBits)] 392 pub struct Control { 393 /// `UARTEN` UART enable: 0 = UART is disabled. If the UART is disabled 394 /// in the middle of transmission or reception, it completes the current 395 /// character before stopping. 1 = the UART is enabled. Data 396 /// transmission and reception occurs for either UART signals or SIR 397 /// signals depending on the setting of the SIREN bit. 398 pub enable_uart: bool, 399 /// `SIREN` `SIR` enable: 0 = IrDA SIR ENDEC is disabled. `nSIROUT` 400 /// remains LOW (no light pulse generated), and signal transitions on 401 /// SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is 402 /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, 403 /// in the marking state. Signal transitions on UARTRXD or modem status 404 /// inputs have no effect. This bit has no effect if the UARTEN bit 405 /// disables the UART. 406 pub enable_sir: bool, 407 /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding 408 /// mode. If this bit is cleared to 0, low-level bits are transmitted as 409 /// an active high pulse with a width of 3/ 16th of the bit period. If 410 /// this bit is set to 1, low-level bits are transmitted with a pulse 411 /// width that is 3 times the period of the IrLPBaud16 input signal, 412 /// regardless of the selected bit rate. Setting this bit uses less 413 /// power, but might reduce transmission distances. 414 pub sir_lowpower_irda_mode: u1, 415 /// Reserved, do not modify, read as zero. 416 _reserved_zero_no_modify: u4, 417 /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN bit is 418 /// set to 1 and the SIRTEST bit in the Test Control register, UARTTCR 419 /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed 420 /// through to the SIRIN path. The SIRTEST bit in the test register must 421 /// be set to 1 to override the normal half-duplex SIR operation. This 422 /// must be the requirement for accessing the test registers during 423 /// normal operation, and SIRTEST must be cleared to 0 when loopback 424 /// testing is finished. This feature reduces the amount of external 425 /// coupling required during system test. If this bit is set to 1, and 426 /// the SIRTEST bit is set to 0, the UARTTXD path is fed through to the 427 /// UARTRXD path. In either SIR mode or UART mode, when this bit is set, 428 /// the modem outputs are also fed through to the modem inputs. This bit 429 /// is cleared to 0 on reset, to disable loopback. 430 pub enable_loopback: bool, 431 /// `TXE` Transmit enable. If this bit is set to 1, the transmit section 432 /// of the UART is enabled. Data transmission occurs for either UART 433 /// signals, or SIR signals depending on the setting of the SIREN bit. 434 /// When the UART is disabled in the middle of transmission, it 435 /// completes the current character before stopping. 436 pub enable_transmit: bool, 437 /// `RXE` Receive enable. If this bit is set to 1, the receive section 438 /// of the UART is enabled. Data reception occurs for either UART 439 /// signals or SIR signals depending on the setting of the SIREN bit. 440 /// When the UART is disabled in the middle of reception, it completes 441 /// the current character before stopping. 442 pub enable_receive: bool, 443 /// `DTR` Data transmit ready. This bit is the complement of the UART 444 /// data transmit ready, `nUARTDTR`, modem status output. That is, when 445 /// the bit is programmed to a 1 then `nUARTDTR` is LOW. 446 pub data_transmit_ready: bool, 447 /// `RTS` Request to send. This bit is the complement of the UART 448 /// request to send, `nUARTRTS`, modem status output. That is, when the 449 /// bit is programmed to a 1 then `nUARTRTS` is LOW. 450 pub request_to_send: bool, 451 /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1`) 452 /// modem status output. That is, when the bit is programmed to a 1 the 453 /// output is 0. For DTE this can be used as Data Carrier Detect (DCD). 454 pub out_1: bool, 455 /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2`) 456 /// modem status output. That is, when the bit is programmed to a 1, the 457 /// output is 0. For DTE this can be used as Ring Indicator (RI). 458 pub out_2: bool, 459 /// `RTSEn` RTS hardware flow control enable. If this bit is set to 1, 460 /// RTS hardware flow control is enabled. Data is only requested when 461 /// there is space in the receive FIFO for it to be received. 462 pub rts_hardware_flow_control_enable: bool, 463 /// `CTSEn` CTS hardware flow control enable. If this bit is set to 1, 464 /// CTS hardware flow control is enabled. Data is only transmitted when 465 /// the `nUARTCTS` signal is asserted. 466 pub cts_hardware_flow_control_enable: bool, 467 /// 31:16 - Reserved, do not modify, read as zero. 468 _reserved_zero_no_modify2: u16, 469 } 470 impl_vmstate_bitsized!(Control); 471 472 impl Control { reset(&mut self)473 pub fn reset(&mut self) { 474 *self = 0.into(); 475 self.set_enable_receive(true); 476 self.set_enable_transmit(true); 477 } 478 } 479 480 impl Default for Control { default() -> Self481 fn default() -> Self { 482 let mut ret: Self = 0.into(); 483 ret.reset(); 484 ret 485 } 486 } 487 488 /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC 489 pub struct Interrupt(pub u32); 490 491 impl Interrupt { 492 pub const OE: Self = Self(1 << 10); 493 pub const BE: Self = Self(1 << 9); 494 pub const PE: Self = Self(1 << 8); 495 pub const FE: Self = Self(1 << 7); 496 pub const RT: Self = Self(1 << 6); 497 pub const TX: Self = Self(1 << 5); 498 pub const RX: Self = Self(1 << 4); 499 pub const DSR: Self = Self(1 << 3); 500 pub const DCD: Self = Self(1 << 2); 501 pub const CTS: Self = Self(1 << 1); 502 pub const RI: Self = Self(1 << 0); 503 504 pub const E: Self = Self(Self::OE.0 | Self::BE.0 | Self::PE.0 | Self::FE.0); 505 pub const MS: Self = Self(Self::RI.0 | Self::DSR.0 | Self::DCD.0 | Self::CTS.0); 506 } 507