1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU_13_0_12_PMFW_H 24 #define SMU_13_0_12_PMFW_H 25 26 #define NUM_VCLK_DPM_LEVELS 4 27 #define NUM_DCLK_DPM_LEVELS 4 28 #define NUM_SOCCLK_DPM_LEVELS 4 29 #define NUM_LCLK_DPM_LEVELS 4 30 #define NUM_UCLK_DPM_LEVELS 4 31 #define NUM_FCLK_DPM_LEVELS 4 32 #define NUM_XGMI_DPM_LEVELS 2 33 #define NUM_CXL_BITRATES 4 34 #define NUM_PCIE_BITRATES 4 35 #define NUM_XGMI_BITRATES 4 36 #define NUM_XGMI_WIDTHS 3 37 #define NUM_TDP_GROUPS 4 38 #define NUM_SOC_P2S_TABLES 6 39 #define NUM_GFX_P2S_TABLES 8 40 #define NUM_PSM_DIDT_THRESHOLDS 3 41 #define NUM_XVMIN_VMIN_THRESHOLDS 3 42 43 #define PRODUCT_MODEL_NUMBER_LEN 20 44 #define PRODUCT_NAME_LEN 64 45 #define PRODUCT_SERIAL_LEN 20 46 #define PRODUCT_MANUFACTURER_NAME_LEN 32 47 #define PRODUCT_FRU_ID_LEN 32 48 49 typedef enum { 50 /*0*/ FEATURE_DATA_CALCULATION = 0, 51 /*1*/ FEATURE_DPM_FCLK = 1, 52 /*2*/ FEATURE_DPM_GFXCLK = 2, 53 /*3*/ FEATURE_DPM_LCLK = 3, 54 /*4*/ FEATURE_DPM_SOCCLK = 4, 55 /*5*/ FEATURE_DPM_UCLK = 5, 56 /*6*/ FEATURE_DPM_VCN = 6, 57 /*7*/ FEATURE_DPM_XGMI = 7, 58 /*8*/ FEATURE_DS_FCLK = 8, 59 /*9*/ FEATURE_DS_GFXCLK = 9, 60 /*10*/ FEATURE_DS_LCLK = 10, 61 /*11*/ FEATURE_DS_MP0CLK = 11, 62 /*12*/ FEATURE_DS_MP1CLK = 12, 63 /*13*/ FEATURE_DS_MPIOCLK = 13, 64 /*14*/ FEATURE_DS_SOCCLK = 14, 65 /*15*/ FEATURE_DS_VCN = 15, 66 /*16*/ FEATURE_APCC_DFLL = 16, 67 /*17*/ FEATURE_APCC_PLUS = 17, 68 /*18*/ FEATURE_PPT = 18, 69 /*19*/ FEATURE_TDC = 19, 70 /*20*/ FEATURE_THERMAL = 20, 71 /*21*/ FEATURE_SOC_PCC = 21, 72 /*22*/ FEATURE_PROCHOT = 22, 73 /*23*/ FEATURE_FDD_AID_HBM = 23, 74 /*24*/ FEATURE_FDD_AID_SOC = 24, 75 /*25*/ FEATURE_FDD_XCD_EDC = 25, 76 /*26*/ FEATURE_FDD_XCD_XVMIN = 26, 77 /*27*/ FEATURE_FW_CTF = 27, 78 /*28*/ FEATURE_SMU_CG = 28, 79 /*29*/ FEATURE_PSI7 = 29, 80 /*30*/ FEATURE_XGMI_PER_LINK_PWR_DOWN = 30, 81 /*31*/ FEATURE_SOC_DC_RTC = 31, 82 /*32*/ FEATURE_GFX_DC_RTC = 32, 83 /*33*/ FEATURE_DVM_MIN_PSM = 33, 84 /*34*/ FEATURE_PRC = 34, 85 /*35*/ FEATURE_PSM_SQ_THROTTLER = 35, 86 /*36*/ FEATURE_PIT = 36, 87 /*37*/ FEATURE_DVO = 37, 88 /*38*/ FEATURE_XVMINORPSM_CLKSTOP_DS = 38, 89 90 /*39*/ NUM_FEATURES = 39 91 } FEATURE_LIST_e; 92 93 //enum for MPIO PCIe gen speed msgs 94 typedef enum { 95 PCIE_LINK_SPEED_INDEX_TABLE_RESERVED, 96 PCIE_LINK_SPEED_INDEX_TABLE_GEN1, 97 PCIE_LINK_SPEED_INDEX_TABLE_GEN2, 98 PCIE_LINK_SPEED_INDEX_TABLE_GEN3, 99 PCIE_LINK_SPEED_INDEX_TABLE_GEN4, 100 PCIE_LINK_SPEED_INDEX_TABLE_GEN5, 101 PCIE_LINK_SPEED_INDEX_TABLE_COUNT 102 } PCIE_LINK_SPEED_INDEX_TABLE_e; 103 104 typedef enum { 105 GFX_GUARDBAND_OFFSET_0, 106 GFX_GUARDBAND_OFFSET_1, 107 GFX_GUARDBAND_OFFSET_2, 108 GFX_GUARDBAND_OFFSET_3, 109 GFX_GUARDBAND_OFFSET_4, 110 GFX_GUARDBAND_OFFSET_5, 111 GFX_GUARDBAND_OFFSET_6, 112 GFX_GUARDBAND_OFFSET_7, 113 GFX_GUARDBAND_OFFSET_COUNT 114 } GFX_GUARDBAND_OFFSET_e; 115 116 typedef enum { 117 GFX_DVM_MARGINHI_0, 118 GFX_DVM_MARGINHI_1, 119 GFX_DVM_MARGINHI_2, 120 GFX_DVM_MARGINHI_3, 121 GFX_DVM_MARGINHI_4, 122 GFX_DVM_MARGINHI_5, 123 GFX_DVM_MARGINHI_6, 124 GFX_DVM_MARGINHI_7, 125 GFX_DVM_MARGINLO_0, 126 GFX_DVM_MARGINLO_1, 127 GFX_DVM_MARGINLO_2, 128 GFX_DVM_MARGINLO_3, 129 GFX_DVM_MARGINLO_4, 130 GFX_DVM_MARGINLO_5, 131 GFX_DVM_MARGINLO_6, 132 GFX_DVM_MARGINLO_7, 133 GFX_DVM_MARGIN_COUNT 134 } GFX_DVM_MARGIN_e; 135 136 #define SMU_METRICS_TABLE_VERSION 0x12 137 138 typedef struct __attribute__((packed, aligned(4))) { 139 uint64_t AccumulationCounter; 140 141 //TEMPERATURE 142 uint32_t MaxSocketTemperature; 143 uint32_t MaxVrTemperature; 144 uint32_t MaxHbmTemperature; 145 uint64_t MaxSocketTemperatureAcc; 146 uint64_t MaxVrTemperatureAcc; 147 uint64_t MaxHbmTemperatureAcc; 148 149 //POWER 150 uint32_t SocketPowerLimit; 151 uint32_t SocketPower; 152 153 //ENERGY 154 uint64_t Timestamp; 155 uint64_t SocketEnergyAcc; 156 uint64_t XcdEnergyAcc; 157 uint64_t AidEnergyAcc; 158 uint64_t HbmEnergyAcc; 159 160 //FREQUENCY 161 uint32_t GfxclkFrequencyLimit; 162 uint32_t FclkFrequency; 163 uint32_t UclkFrequency; 164 uint32_t SocclkFrequency[4]; 165 uint32_t VclkFrequency[4]; 166 uint32_t DclkFrequency[4]; 167 uint32_t LclkFrequency[4]; 168 uint64_t GfxclkFrequencyAcc[8]; 169 170 //FREQUENCY RANGE 171 uint32_t MaxLclkDpmRange; 172 uint32_t MinLclkDpmRange; 173 174 //XGMI 175 uint32_t XgmiWidth; 176 uint32_t XgmiBitrate; 177 uint64_t XgmiReadBandwidthAcc[8]; 178 uint64_t XgmiWriteBandwidthAcc[8]; 179 180 //ACTIVITY 181 uint32_t SocketGfxBusy; 182 uint32_t DramBandwidthUtilization; 183 uint64_t SocketGfxBusyAcc; 184 uint64_t DramBandwidthAcc; 185 uint32_t MaxDramBandwidth; 186 uint64_t DramBandwidthUtilizationAcc; 187 uint64_t PcieBandwidthAcc[4]; 188 189 //THROTTLERS 190 uint32_t ProchotResidencyAcc; 191 uint32_t PptResidencyAcc; 192 uint32_t SocketThmResidencyAcc; 193 uint32_t VrThmResidencyAcc; 194 uint32_t HbmThmResidencyAcc; 195 uint32_t GfxLockXCDMak; 196 197 // New Items at end to maintain driver compatibility 198 uint32_t GfxclkFrequency[8]; 199 200 //XGMI Data tranfser size 201 uint64_t XgmiReadDataSizeAcc[8];//in KByte 202 uint64_t XgmiWriteDataSizeAcc[8];//in KByte 203 204 //PCIE BW Data and error count 205 uint32_t PcieBandwidth[4]; 206 uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated 207 uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated 208 uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated 209 uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated 210 uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated 211 212 // VCN/JPEG ACTIVITY 213 uint32_t VcnBusy[4]; 214 uint32_t JpegBusy[40]; 215 216 // PCIE LINK Speed and width 217 uint32_t PCIeLinkSpeed; 218 uint32_t PCIeLinkWidth; 219 220 // PER XCD ACTIVITY 221 uint32_t GfxBusy[8]; 222 uint64_t GfxBusyAcc[8]; 223 224 //PCIE BW Data and error count 225 uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated 226 227 //Total App Clock Counter 228 uint64_t GfxclkBelowHostLimitPptAcc[8]; 229 uint64_t GfxclkBelowHostLimitThmAcc[8]; 230 uint64_t GfxclkBelowHostLimitTotalAcc[8]; 231 uint64_t GfxclkLowUtilizationAcc[8]; 232 } MetricsTable_t; 233 234 #define SMU_VF_METRICS_TABLE_MASK (1 << 31) 235 #define SMU_VF_METRICS_TABLE_VERSION (0x6 | SMU_VF_METRICS_TABLE_MASK) 236 237 typedef struct __attribute__((packed, aligned(4))) { 238 uint32_t AccumulationCounter; 239 uint32_t InstGfxclk_TargFreq; 240 uint64_t AccGfxclk_TargFreq; 241 uint64_t AccGfxRsmuDpm_Busy; 242 uint64_t AccGfxclkBelowHostLimitPpt; 243 uint64_t AccGfxclkBelowHostLimitThm; 244 uint64_t AccGfxclkBelowHostLimitTotal; 245 uint64_t AccGfxclkLowUtilization; 246 } VfMetricsTable_t; 247 248 /* FRU product information */ 249 typedef struct __attribute__((packed, aligned(4))) { 250 uint8_t ModelNumber[PRODUCT_MODEL_NUMBER_LEN]; 251 uint8_t Name[PRODUCT_NAME_LEN]; 252 uint8_t Serial[PRODUCT_SERIAL_LEN]; 253 uint8_t ManufacturerName[PRODUCT_MANUFACTURER_NAME_LEN]; 254 uint8_t FruId[PRODUCT_FRU_ID_LEN]; 255 } FRUProductInfo_t; 256 257 #pragma pack(push, 4) 258 typedef struct { 259 //FRU PRODUCT INFO 260 FRUProductInfo_t ProductInfo; 261 262 //POWER 263 uint32_t MaxSocketPowerLimit; 264 265 //FREQUENCY RANGE 266 uint32_t MaxGfxclkFrequency; 267 uint32_t MinGfxclkFrequency; 268 uint32_t FclkFrequencyTable[4]; 269 uint32_t UclkFrequencyTable[4]; 270 uint32_t SocclkFrequencyTable[4]; 271 uint32_t VclkFrequencyTable[4]; 272 uint32_t DclkFrequencyTable[4]; 273 uint32_t LclkFrequencyTable[4]; 274 275 //PSNs 276 uint64_t PublicSerialNumber_AID[4]; 277 uint64_t PublicSerialNumber_XCD[8]; 278 } StaticMetricsTable_t; 279 #pragma pack(pop) 280 281 #endif 282