1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_REGS_H 7 #define __MT7996_REGS_H 8 9 struct __map { 10 u32 phys; 11 u32 mapped; 12 u32 size; 13 }; 14 15 struct __base { 16 u32 band_base[__MT_MAX_BAND]; 17 }; 18 19 /* used to differentiate between generations */ 20 struct mt7996_reg_desc { 21 const struct __base *base; 22 const u32 *offs_rev; 23 const struct __map *map; 24 u32 map_size; 25 }; 26 27 enum base_rev { 28 WF_AGG_BASE, 29 WF_ARB_BASE, 30 WF_TMAC_BASE, 31 WF_RMAC_BASE, 32 WF_DMA_BASE, 33 WF_WTBLOFF_BASE, 34 WF_ETBF_BASE, 35 WF_LPON_BASE, 36 WF_MIB_BASE, 37 WF_RATE_BASE, 38 __MT_REG_BASE_MAX, 39 }; 40 41 #define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)]) 42 43 enum offs_rev { 44 MIB_RVSR0, 45 MIB_RVSR1, 46 MIB_BTSCR5, 47 MIB_BTSCR6, 48 MIB_RSCR1, 49 MIB_RSCR27, 50 MIB_RSCR28, 51 MIB_RSCR29, 52 MIB_RSCR30, 53 MIB_RSCR31, 54 MIB_RSCR33, 55 MIB_RSCR35, 56 MIB_RSCR36, 57 MIB_BSCR0, 58 MIB_BSCR1, 59 MIB_BSCR2, 60 MIB_BSCR3, 61 MIB_BSCR4, 62 MIB_BSCR5, 63 MIB_BSCR6, 64 MIB_BSCR7, 65 MIB_BSCR17, 66 MIB_TRDR1, 67 HIF_REMAP_L1, 68 HIF_REMAP_BASE_L1, 69 HIF_REMAP_L2, 70 HIF_REMAP_BASE_L2, 71 CBTOP1_PHY_END, 72 INFRA_MCU_END, 73 WTBLON_WDUCR, 74 WTBL_UPDATE, 75 WTBL_ITCR, 76 WTBL_ITCR0, 77 WTBL_ITCR1, 78 __MT_OFFS_MAX, 79 }; 80 81 #define __OFFS(id) (dev->reg.offs_rev[(id)]) 82 83 /* RRO TOP */ 84 #define MT_RRO_TOP_BASE 0xA000 85 #define MT_RRO_TOP(ofs) (MT_RRO_TOP_BASE + (ofs)) 86 87 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8) 88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC) 89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8) 90 #define WF_RRO_AXI_MST_CFG_DIDX_OK BIT(12) 91 92 #define MT_RRO_ADDR_ARRAY_BASE0 MT_RRO_TOP(0x30) 93 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34) 94 #define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE BIT(31) 95 96 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38) 97 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C) 98 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40) 99 #define MT_RRO_IND_CMD_SIGNATURE_BASE1_EN BIT(31) 100 101 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C) 102 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60) 103 #define MT_RRO_PARTICULAR_CONFG_EN BIT(31) 104 #define MT_RRO_PARTICULAR_SID GENMASK(30, 16) 105 106 #define MT_RRO_BA_BITMAP_BASE_EXT0 MT_RRO_TOP(0x70) 107 #define MT_RRO_BA_BITMAP_BASE_EXT1 MT_RRO_TOP(0x74) 108 #define MT_RRO_HOST_INT_ENA MT_RRO_TOP(0x204) 109 #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0) 110 111 #define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400) 112 113 #define MT_RRO_3_0_EMU_CONF MT_RRO_TOP(0x600) 114 #define MT_RRO_3_0_EMU_CONF_EN_MASK BIT(11) 115 116 #define MT_RRO_3_1_GLOBAL_CONFIG MT_RRO_TOP(0x604) 117 #define MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL BIT(6) 118 #define MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN BIT(3) 119 #define MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN BIT(2) 120 #define MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN BIT(0) 121 122 #define MT_RRO_MSDU_PG_SEG_ADDR0 MT_RRO_TOP(0x620) 123 #define MT_RRO_RX_RING_AP_CIDX_ADDR MT_RRO_TOP(0x6f0) 124 #define MT_RRO_RX_RING_AP_DIDX_ADDR MT_RRO_TOP(0x6f4) 125 126 #define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50) 127 #define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16) 128 #define MT_RRO_ACK_SN_CTRL_SESSION_MASK GENMASK(11, 0) 129 130 #define MT_RRO_DBG_RD_CTRL MT_RRO_TOP(0xe0) 131 #define MT_RRO_DBG_RD_ADDR GENMASK(15, 0) 132 #define MT_RRO_DBG_RD_EXEC BIT(31) 133 134 #define MT_RRO_DBG_RDAT_DW(_n) MT_RRO_TOP(0xf0 + (_n) * 0x4) 135 136 #define MT_MCU_INT_EVENT 0x2108 137 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 138 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 139 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 140 141 /* PLE */ 142 #define MT_PLE_BASE 0x820c0000 143 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 144 145 #define MT_FL_Q_EMPTY MT_PLE(0x360) 146 #define MT_FL_Q0_CTRL MT_PLE(0x3e0) 147 #define MT_FL_Q2_CTRL MT_PLE(0x3e8) 148 #define MT_FL_Q3_CTRL MT_PLE(0x3ec) 149 150 #define MT_PLE_FREEPG_CNT MT_PLE(0x380) 151 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384) 152 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c) 153 #define MT_PLE_HIF_PG_INFO MT_PLE(0x388) 154 155 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2)) 156 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 157 158 /* WF MDP TOP */ 159 #define MT_MDP_BASE 0x820cc000 160 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 161 162 #define MT_MDP_DCR0 MT_MDP(0x800) 163 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19) 164 165 #define MT_MDP_DCR2 MT_MDP(0x8e8) 166 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2) 167 168 /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */ 169 #define MT_WF_TMAC_BASE(_band) __BASE(WF_TMAC_BASE, (_band)) 170 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 171 172 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 173 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 174 175 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8) 176 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc) 177 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 178 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 179 180 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014) 181 #define MT_IFS_EIFS_OFDM GENMASK(8, 0) 182 #define MT_IFS_RIFS GENMASK(14, 10) 183 #define MT_IFS_SIFS GENMASK(22, 16) 184 #define MT_IFS_SLOT GENMASK(30, 24) 185 186 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018) 187 #define MT_IFS_EIFS_CCK GENMASK(8, 0) 188 189 /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */ 190 #define MT_WF_DMA_BASE(_band) __BASE(WF_DMA_BASE, (_band)) 191 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 192 193 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 194 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 195 196 #define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054) 197 #define MT_DMA_TCRF1_QIDX GENMASK(15, 13) 198 199 /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */ 200 #define MT_WTBLOFF_BASE(_band) __BASE(WF_WTBLOFF_BASE, (_band)) 201 #define MT_WTBLOFF(_band, ofs) (MT_WTBLOFF_BASE(_band) + (ofs)) 202 203 #define MT_WTBLOFF_RSCR(_band) MT_WTBLOFF(_band, 0x008) 204 #define MT_WTBLOFF_RSCR_RCPI_MODE GENMASK(31, 30) 205 #define MT_WTBLOFF_RSCR_RCPI_PARAM GENMASK(25, 24) 206 207 #define MT_WTBLOFF_ACR(_band) MT_WTBLOFF(_band, 0x010) 208 #define MT_WTBLOFF_ADM_BACKOFFTIME BIT(29) 209 210 /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */ 211 #define MT_WF_ETBF_BASE(_band) __BASE(WF_ETBF_BASE, (_band)) 212 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 213 214 #define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100) 215 #define MT_ETBF_RX_FB_BW GENMASK(10, 8) 216 #define MT_ETBF_RX_FB_NC GENMASK(7, 4) 217 #define MT_ETBF_RX_FB_NR GENMASK(3, 0) 218 219 /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */ 220 #define MT_WF_LPON_BASE(_band) __BASE(WF_LPON_BASE, (_band)) 221 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 222 223 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360) 224 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364) 225 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c) 226 227 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4)) 228 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 229 #define MT_LPON_TCR_SW_WRITE BIT(0) 230 #define MT_LPON_TCR_SW_ADJUST BIT(1) 231 #define MT_LPON_TCR_SW_READ GENMASK(1, 0) 232 233 /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/ 234 /* These counters are (mostly?) clear-on-read. So, some should not 235 * be read at all in case firmware is already reading them. These 236 * are commented with 'DNR' below. The DNR stats will be read by querying 237 * the firmware API for the appropriate message. For counters the driver 238 * does read, the driver should accumulate the counters. 239 */ 240 #define MT_WF_MIB_BASE(_band) __BASE(WF_MIB_BASE, (_band)) 241 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 242 243 #define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR0)) 244 #define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR1)) 245 #define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR2)) 246 #define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR3)) 247 #define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR4)) 248 #define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR5)) 249 #define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR6)) 250 #define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR7)) 251 #define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR17)) 252 253 #define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4) 254 #define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8) 255 #define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0) 256 257 #define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR1)) 258 /* rx mpdu counter, full 32 bits */ 259 #define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR31)) 260 #define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR33)) 261 262 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 263 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 264 265 #define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR0)) 266 267 #define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR35)) 268 #define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR36)) 269 270 /* tx ampdu cnt, full 32 bits */ 271 #define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0) 272 #define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8) 273 274 /* counts all mpdus in ampdu, regardless of success */ 275 #define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc) 276 277 /* counts all successfully tx'd mpdus in ampdu */ 278 #define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0) 279 280 /* rx ampdu count, 32-bit */ 281 #define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR27)) 282 283 /* rx ampdu bytes count, 32-bit */ 284 #define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR28)) 285 286 /* rx ampdu valid subframe count */ 287 #define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR29)) 288 289 /* rx ampdu valid subframe bytes count, 32bits */ 290 #define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR30)) 291 292 /* remaining windows protected stats */ 293 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080) 294 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0) 295 296 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084) 297 #define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0) 298 299 #define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR1)) 300 301 /* rx blockack count, 32 bits */ 302 #define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4) 303 304 #define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0) 305 #define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR5)) 306 #define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR6)) 307 308 #define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0) 309 310 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(MIB_TRDR1) + ((n) << 2)) 311 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2)) 312 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0)) 313 314 /* UMIB */ 315 #define MT_WF_UMIB_BASE 0x820cd000 316 #define MT_WF_UMIB(ofs) (MT_WF_UMIB_BASE + (ofs)) 317 318 #define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + (_band) * 0x164) 319 320 /* WTBLON TOP */ 321 #define MT_WTBLON_TOP_BASE 0x820d4000 322 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 323 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_WDUCR)) 324 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) 325 326 #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) 327 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0) 328 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14) 329 #define MT_WTBL_UPDATE_BUSY BIT(31) 330 331 #define MT_WTBL_ITCR MT_WTBLON_TOP(__OFFS(WTBL_ITCR)) 332 #define MT_WTBL_ITCR_WR BIT(16) 333 #define MT_WTBL_ITCR_EXEC BIT(31) 334 #define MT_WTBL_ITDR0 MT_WTBLON_TOP(__OFFS(WTBL_ITCR0)) 335 #define MT_WTBL_ITDR1 MT_WTBLON_TOP(__OFFS(WTBL_ITCR1)) 336 #define MT_WTBL_SPE_IDX_SEL BIT(6) 337 338 /* WTBL */ 339 #define MT_WTBL_BASE 0x820d8000 340 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 341 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 342 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 343 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 344 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 345 346 /* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */ 347 #define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band)) 348 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 349 350 #define MT_AGG_ACR4(_band) MT_WF_AGG(_band, 0x3c) 351 #define MT_AGG_ACR_PPDU_TXS2H BIT(1) 352 353 /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */ 354 #define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band)) 355 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 356 357 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000) 358 #define MT_ARB_SCR_TX_DISABLE BIT(8) 359 #define MT_ARB_SCR_RX_DISABLE BIT(9) 360 361 /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */ 362 #define MT_WF_RMAC_BASE(_band) __BASE(WF_RMAC_BASE, (_band)) 363 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 364 365 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 366 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 367 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 368 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 369 #define MT_WF_RFCR_DROP_MCAST BIT(5) 370 #define MT_WF_RFCR_DROP_BCAST BIT(6) 371 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 372 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 373 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 374 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 375 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 376 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 377 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 378 #define MT_WF_RFCR_DROP_CTS BIT(14) 379 #define MT_WF_RFCR_DROP_RTS BIT(15) 380 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 381 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 382 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 383 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 384 #define MT_WF_RFCR_DROP_NDPA BIT(20) 385 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 386 387 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 388 #define MT_WF_RFCR1_DROP_ACK BIT(4) 389 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 390 #define MT_WF_RFCR1_DROP_BA BIT(6) 391 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 392 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 393 394 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 395 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 396 #define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16) 397 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0) 398 399 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384) 400 #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16) 401 402 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c) 403 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0) 404 405 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390) 406 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0) 407 408 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0) 409 #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) 410 411 /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */ 412 #define MT_WF_RATE_BASE(_band) __BASE(WF_RATE_BASE, (_band)) 413 #define MT_WF_RATE(_band, ofs) (MT_WF_RATE_BASE(_band) + (ofs)) 414 415 #define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050) 416 #define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0) 417 418 /* WFDMA0 */ 419 #define MT_WFDMA0_BASE 0xd4000 420 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 421 422 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 423 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 424 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 425 426 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 427 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 428 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 429 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 430 431 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154) 432 #define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3) 433 #define MT_WFDMA0_RX_INT_SEL_RING5 BIT(5) 434 #define MT_WFDMA0_RX_INT_SEL_RING6 BIT(6) 435 #define MT_WFDMA0_RX_INT_SEL_RING9 BIT(9) 436 437 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 438 439 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 440 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 441 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 442 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 443 #define MT_WFDMA0_GLO_CFG_EXT_EN BIT(26) 444 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 445 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 446 447 #define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268) 448 #define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c) 449 #define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270) 450 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c) 451 452 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 453 #define WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK GENMASK(27, 24) 454 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) 455 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) 456 457 #define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4) 458 #define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE BIT(31) 459 #define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE BIT(28) 460 461 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 462 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 463 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 464 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 465 466 /* WFDMA1 */ 467 #define MT_WFDMA1_BASE 0xd5000 468 469 /* WFDMA CSR */ 470 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 471 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 472 473 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 474 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 475 #define MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 BIT(20) 476 #define MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 BIT(21) 477 #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) 478 479 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 480 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 481 482 #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) 483 #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) 484 485 #define MT_WFDMA_AXI_R2A_CTRL2 MT_WFDMA_EXT_CSR(0x508) 486 #define MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK GENMASK(31, 28) 487 488 #define MT_PCIE_RECOG_ID 0xd7090 489 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 490 #define MT_PCIE_RECOG_ID_SEM BIT(31) 491 492 /* WFDMA0 PCIE1 */ 493 #define MT_WFDMA0_PCIE1_BASE 0xd8000 494 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 495 496 #define MT_INT_PCIE1_SOURCE_CSR_EXT MT_WFDMA0_PCIE1(0x118) 497 #define MT_INT_PCIE1_MASK_CSR MT_WFDMA0_PCIE1(0x11c) 498 499 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 500 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 501 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 502 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 503 504 /* WFDMA COMMON */ 505 #define __RXQ(q) ((q) + __MT_MCUQ_MAX) 506 #define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX) 507 508 #define MT_Q_ID(q) (dev->q_id[(q)]) 509 #define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \ 510 MT_WFDMA1_BASE : MT_WFDMA0_BASE) 511 512 #define MT_MCUQ_ID(q) MT_Q_ID(q) 513 #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 514 #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 515 516 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 517 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 518 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 519 #define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40) 520 521 #define MT_RXQ_RRO_AP_RING_BASE MT_RRO_TOP(0x650) 522 523 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 524 MT_MCUQ_ID(q) * 0x4) 525 #define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 526 MT_RXQ_ID(q) * 0x4) 527 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 528 MT_TXQ_ID(q) * 0x4) 529 530 #define MT_INT_SOURCE_CSR MT_WFDMA0(0x200) 531 #define MT_INT_MASK_CSR MT_WFDMA0(0x204) 532 533 #define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200) 534 #define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204) 535 536 #define MT_INT_RX_DONE_BAND0 BIT(12) 537 #define MT_INT_RX_DONE_BAND1 BIT(13) /* for mt7992 */ 538 #define MT_INT_RX_DONE_BAND2 BIT(13) 539 #define MT_INT_RX_DONE_WM BIT(0) 540 #define MT_INT_RX_DONE_WA BIT(1) 541 #define MT_INT_RX_DONE_WA_MAIN BIT(2) 542 #define MT_INT_RX_DONE_WA_EXT BIT(3) /* for mt7992 */ 543 #define MT_INT_RX_DONE_WA_TRI BIT(3) 544 #define MT_INT_RX_TXFREE_MAIN BIT(17) 545 #define MT_INT_RX_TXFREE_BAND1 BIT(15) 546 #define MT_INT_RX_TXFREE_TRI BIT(15) 547 #define MT_INT_RX_TXFREE_BAND1_EXT BIT(19) /* for mt7992 two PCIE*/ 548 #define MT_INT_RX_TXFREE_BAND0_MT7990 BIT(14) 549 #define MT_INT_RX_TXFREE_BAND1_MT7990 BIT(15) 550 #define MT_INT_RX_DONE_BAND2_EXT BIT(23) 551 #define MT_INT_RX_TXFREE_EXT BIT(26) 552 #define MT_INT_MCU_CMD BIT(29) 553 554 #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) 555 #define MT_INT_RX_DONE_RRO_BAND1 BIT(17) 556 #define MT_INT_RX_DONE_RRO_BAND2 BIT(14) 557 #define MT_INT_RX_DONE_RRO_IND BIT(11) 558 #define MT_INT_RX_DONE_RRO_RXDMAD_C BIT(11) 559 #define MT_INT_RX_DONE_MSDU_PG_BAND0 BIT(18) 560 #define MT_INT_RX_DONE_MSDU_PG_BAND1 BIT(19) 561 #define MT_INT_RX_DONE_MSDU_PG_BAND2 BIT(23) 562 563 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 564 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 565 566 #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 567 MT_INT_RX(MT_RXQ_MCU_WA)) 568 569 #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 570 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 571 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 572 573 #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \ 574 MT_INT_RX(MT_RXQ_BAND1_WA) | \ 575 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 576 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 577 578 #define MT_INT_BAND2_RX_DONE (MT_INT_RX(MT_RXQ_BAND2) | \ 579 MT_INT_RX(MT_RXQ_BAND2_WA) | \ 580 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 581 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 582 583 #define MT_INT_RRO_RX_DONE (MT_INT_RX(MT_RXQ_RRO_BAND0) | \ 584 MT_INT_RX(MT_RXQ_RRO_BAND1) | \ 585 MT_INT_RX(MT_RXQ_RRO_BAND2) | \ 586 MT_INT_RX(MT_RXQ_RRO_IND) | \ 587 MT_INT_RX(MT_RXQ_RRO_RXDMAD_C) | \ 588 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND0) | \ 589 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND1) | \ 590 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND2)) 591 592 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 593 MT_INT_BAND0_RX_DONE | \ 594 MT_INT_BAND1_RX_DONE | \ 595 MT_INT_BAND2_RX_DONE | \ 596 MT_INT_RRO_RX_DONE) 597 598 #define MT_INT_TX_DONE_FWDL BIT(26) 599 #define MT_INT_TX_DONE_MCU_WM BIT(27) 600 #define MT_INT_TX_DONE_MCU_WA BIT(22) 601 #define MT_INT_TX_DONE_BAND0 BIT(30) 602 #define MT_INT_TX_DONE_BAND1 BIT(31) 603 #define MT_INT_TX_DONE_BAND2 BIT(15) 604 605 #define MT_INT_TX_RX_DONE_EXT (MT_INT_TX_DONE_BAND2 | \ 606 MT_INT_RX_DONE_BAND2_EXT | \ 607 MT_INT_RX_TXFREE_EXT) 608 609 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 610 MT_INT_TX_MCU(MT_MCUQ_WM) | \ 611 MT_INT_TX_MCU(MT_MCUQ_FWDL)) 612 613 #define MT_MCU_CMD MT_WFDMA0(0x1f0) 614 #define MT_MCU_CMD_STOP_DMA BIT(2) 615 #define MT_MCU_CMD_RESET_DONE BIT(3) 616 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 617 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 618 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 619 620 #define MT_MCU_CMD_WA_WDT BIT(31) 621 #define MT_MCU_CMD_WM_WDT BIT(30) 622 #define MT_MCU_CMD_WDT_MASK GENMASK(31, 30) 623 624 /* l1/l2 remap */ 625 #define CONN_BUS_CR_VON_BASE 0x155000 626 #define MT_HIF_REMAP_L1 (CONN_BUS_CR_VON_BASE + __OFFS(HIF_REMAP_L1)) 627 #define MT_HIF_REMAP_L1_MASK_7996 GENMASK(31, 16) 628 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 629 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 630 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 631 #define MT_HIF_REMAP_BASE_L1 __OFFS(HIF_REMAP_BASE_L1) 632 633 #define MT_HIF_REMAP_L2 __OFFS(HIF_REMAP_L2) 634 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 635 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 636 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 637 #define MT_HIF_REMAP_L2_MASK_7990 GENMASK(15, 0) 638 #define MT_HIF_REMAP_L2_OFFSET_7990 GENMASK(15, 0) 639 #define MT_HIF_REMAP_L2_BASE_7990 GENMASK(31, 16) 640 #define MT_HIF_REMAP_BASE_L2 __OFFS(HIF_REMAP_BASE_L2) 641 642 /* for mt7990 only */ 643 #define MT_HIF_REMAP_CBTOP 0x1f6554 644 #define MT_HIF_REMAP_CBTOP_MASK GENMASK(15, 0) 645 #define MT_HIF_REMAP_CBTOP_OFFSET GENMASK(15, 0) 646 #define MT_HIF_REMAP_CBTOP_BASE GENMASK(31, 16) 647 #define MT_HIF_REMAP_BASE_CBTOP 0x1c0000 648 649 #define MT_INFRA_BASE 0x18000000 650 #define MT_WFSYS0_PHY_START 0x18400000 651 #define MT_WFSYS1_PHY_START 0x18800000 652 #define MT_WFSYS1_PHY_END 0x18bfffff 653 #define MT_CBTOP1_PHY_START 0x70000000 654 #define MT_CBTOP1_PHY_END __OFFS(CBTOP1_PHY_END) 655 #define MT_CBTOP2_PHY_START 0xf0000000 656 #define MT_INFRA_MCU_START 0x7c000000 657 #define MT_INFRA_MCU_END __OFFS(INFRA_MCU_END) 658 659 /* FW MODE SYNC */ 660 #define MT_FW_ASSERT_CNT 0x02208274 661 #define MT_FW_DUMP_STATE 0x02209e90 662 663 #define MT_SWDEF_BASE 0x00401400 664 665 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 666 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 667 #define MT_SWDEF_NORMAL_MODE 0 668 669 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040) 670 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) 671 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) 672 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04c) 673 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) 674 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) 675 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) 676 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05c) 677 #define MT_SWDEF_LAMC_WISR6_BN2_STATS MT_SWDEF(0x060) 678 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x064) 679 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x068) 680 #define MT_SWDEF_LAMC_WISR7_BN2_STATS MT_SWDEF(0x06c) 681 682 /* LED */ 683 #define MT_LED_TOP_BASE 0x18013000 684 #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 685 686 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 687 #define MT_LED_CTRL_KICK BIT(7) 688 #define MT_LED_CTRL_BLINK_BAND_SEL BIT(4) 689 #define MT_LED_CTRL_BLINK_MODE BIT(2) 690 #define MT_LED_CTRL_POLARITY BIT(1) 691 692 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 693 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 694 #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 695 696 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 697 698 /* CONN DBG */ 699 #define MT_CONN_DBG_CTL_BASE 0x18023000 700 #define MT_CONN_DBG_CTL(ofs) (MT_CONN_DBG_CTL_BASE + (ofs)) 701 #define MT_CONN_DBG_CTL_OUT_SEL MT_CONN_DBG_CTL(0x604) 702 #define MT_CONN_DBG_CTL_PC_LOG_SEL MT_CONN_DBG_CTL(0x60c) 703 #define MT_CONN_DBG_CTL_PC_LOG MT_CONN_DBG_CTL(0x610) 704 705 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 706 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */ 707 #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8) 708 709 /* MT TOP */ 710 #define MT_TOP_BASE 0xe0000 711 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 712 713 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 714 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 715 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 716 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 717 718 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 719 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 720 721 #define MT_TOP_MISC MT_TOP(0xf0) 722 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 723 724 /* ADIE */ 725 #define MT_ADIE_CHIP_ID(_idx) (0x0f00002c + ((_idx) << 28)) 726 #define MT_ADIE_VERSION_MASK GENMASK(15, 0) 727 #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16) 728 729 #define MT_PAD_GPIO 0x700056f0 730 #define MT_PAD_GPIO_ADIE_COMB GENMASK(16, 15) 731 #define MT_PAD_GPIO_2ADIE_TBTC BIT(19) 732 /* for mt7992 */ 733 #define MT_PAD_GPIO_ADIE_COMB_7992 GENMASK(17, 16) 734 #define MT_PAD_GPIO_ADIE_SINGLE BIT(15) 735 736 #define MT_HW_REV 0x70010204 737 #define MT_HW_REV1 0x8a00 738 739 #define MT_WF_L05_RST 0x70028550 740 #define MT_WF_L05_RST_WF_RST_MASK GENMASK(4, 0) 741 742 #define MT_WF_SUBSYS_RST 0x70028600 743 #define MT_WF_SUBSYS_RST_WHOLE_PATH_RST BIT(0) 744 #define MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT BIT(5) 745 #define MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT BIT(6) 746 #define MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT BIT(16) 747 #define MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE GENMASK(15, 8) 748 749 /* PCIE MAC */ 750 #define MT_PCIE_MAC_BASE 0x74030000 751 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 752 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 753 754 #define MT_PCIE1_MAC_BASE 0x74090000 755 #define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs)) 756 757 #define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188) 758 759 /* PHYRX CSD */ 760 #define MT_WF_PHYRX_CSD_BASE 0x83000000 761 #define MT_WF_PHYRX_CSD(_band, _wf, ofs) (MT_WF_PHYRX_CSD_BASE + \ 762 ((_band) << 20) + \ 763 ((_wf) << 16) + (ofs)) 764 #define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000) 765 766 /* PHYRX CTRL */ 767 #define MT_WF_PHYRX_BAND_BASE 0x83080000 768 #define MT_WF_PHYRX_BAND(_band, ofs) (MT_WF_PHYRX_BAND_BASE + \ 769 ((_band) << 20) + (ofs)) 770 771 #define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) MT_WF_PHYRX_BAND(_band, 0x1054) 772 #define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) MT_WF_PHYRX_BAND(_band, 0x1058) 773 #define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) MT_WF_PHYRX_BAND(_band, 0x105c) 774 #define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) MT_WF_PHYRX_BAND(_band, 0x1060) 775 #define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) MT_WF_PHYRX_BAND(_band, 0x1064) 776 #define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) MT_WF_PHYRX_BAND(_band, 0x1068) 777 778 #define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004) 779 #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0) 780 #define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 781 782 /* PHYRX CSD BAND */ 783 #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230) 784 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 785 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR BIT(29) 786 787 /* CONN MCU EXCP CON */ 788 #define MT_MCU_WM_EXCP_BASE 0x89050000 789 #define MT_MCU_WM_EXCP(ofs) (MT_MCU_WM_EXCP_BASE + (ofs)) 790 #define MT_MCU_WM_EXCP_PC_CTRL MT_MCU_WM_EXCP(0x100) 791 #define MT_MCU_WM_EXCP_PC_LOG MT_MCU_WM_EXCP(0x104) 792 #define MT_MCU_WM_EXCP_LR_CTRL MT_MCU_WM_EXCP(0x200) 793 #define MT_MCU_WM_EXCP_LR_LOG MT_MCU_WM_EXCP(0x204) 794 795 /* CONN AFE CTL CON */ 796 #define MT_AFE_CTL_BASE 0x18043000 797 #define MT_AFE_CTL_BAND(_band, ofs) (MT_AFE_CTL_BASE + \ 798 ((_band) * 0x1000) + (ofs)) 799 #define MT_AFE_CTL_BAND_PLL_03(_band) MT_AFE_CTL_BAND(_band, 0x2c) 800 #define MT_AFE_CTL_BAND_PLL_03_MSB_EN BIT(1) 801 802 #endif 803