1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_REGS_H 7 #define __MT7996_REGS_H 8 9 struct __map { 10 u32 phys; 11 u32 mapped; 12 u32 size; 13 }; 14 15 struct __base { 16 u32 band_base[__MT_MAX_BAND]; 17 }; 18 19 /* used to differentiate between generations */ 20 struct mt7996_reg_desc { 21 const struct __base *base; 22 const u32 *offs_rev; 23 const struct __map *map; 24 u32 map_size; 25 }; 26 27 enum base_rev { 28 WF_AGG_BASE, 29 WF_ARB_BASE, 30 WF_TMAC_BASE, 31 WF_RMAC_BASE, 32 WF_DMA_BASE, 33 WF_WTBLOFF_BASE, 34 WF_ETBF_BASE, 35 WF_LPON_BASE, 36 WF_MIB_BASE, 37 WF_RATE_BASE, 38 __MT_REG_BASE_MAX, 39 }; 40 41 #define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)]) 42 43 enum offs_rev { 44 MIB_RVSR0, 45 MIB_RVSR1, 46 MIB_BTSCR5, 47 MIB_BTSCR6, 48 MIB_RSCR1, 49 MIB_RSCR27, 50 MIB_RSCR28, 51 MIB_RSCR29, 52 MIB_RSCR30, 53 MIB_RSCR31, 54 MIB_RSCR33, 55 MIB_RSCR35, 56 MIB_RSCR36, 57 MIB_BSCR0, 58 MIB_BSCR1, 59 MIB_BSCR2, 60 MIB_BSCR3, 61 MIB_BSCR4, 62 MIB_BSCR5, 63 MIB_BSCR6, 64 MIB_BSCR7, 65 MIB_BSCR17, 66 MIB_TRDR1, 67 HIF_REMAP_L1, 68 HIF_REMAP_BASE_L1, 69 HIF_REMAP_L2, 70 HIF_REMAP_BASE_L2, 71 CBTOP1_PHY_END, 72 INFRA_MCU_END, 73 WTBLON_WDUCR, 74 WTBL_UPDATE, 75 WTBL_ITCR, 76 WTBL_ITCR0, 77 WTBL_ITCR1, 78 __MT_OFFS_MAX, 79 }; 80 81 #define __OFFS(id) (dev->reg.offs_rev[(id)]) 82 83 /* RRO TOP */ 84 #define MT_RRO_TOP_BASE 0xA000 85 #define MT_RRO_TOP(ofs) (MT_RRO_TOP_BASE + (ofs)) 86 87 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8) 88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC) 89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8) 90 #define WF_RRO_AXI_MST_CFG_DIDX_OK BIT(12) 91 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34) 92 #define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE BIT(31) 93 94 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38) 95 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C) 96 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40) 97 #define MT_RRO_IND_CMD_SIGNATURE_BASE1_EN BIT(31) 98 99 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C) 100 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60) 101 #define MT_RRO_PARTICULAR_CONFG_EN BIT(31) 102 #define MT_RRO_PARTICULAR_SID GENMASK(30, 16) 103 104 #define MT_RRO_BA_BITMAP_BASE_EXT0 MT_RRO_TOP(0x70) 105 #define MT_RRO_BA_BITMAP_BASE_EXT1 MT_RRO_TOP(0x74) 106 #define MT_RRO_HOST_INT_ENA MT_RRO_TOP(0x204) 107 #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0) 108 109 #define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400) 110 111 #define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50) 112 #define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16) 113 #define MT_RRO_ACK_SN_CTRL_SESSION_MASK GENMASK(11, 0) 114 115 #define MT_RRO_DBG_RD_CTRL MT_RRO_TOP(0xe0) 116 #define MT_RRO_DBG_RD_ADDR GENMASK(15, 0) 117 #define MT_RRO_DBG_RD_EXEC BIT(31) 118 119 #define MT_RRO_DBG_RDAT_DW(_n) MT_RRO_TOP(0xf0 + (_n) * 0x4) 120 121 #define MT_MCU_INT_EVENT 0x2108 122 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 123 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 124 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 125 126 /* PLE */ 127 #define MT_PLE_BASE 0x820c0000 128 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 129 130 #define MT_FL_Q_EMPTY MT_PLE(0x360) 131 #define MT_FL_Q0_CTRL MT_PLE(0x3e0) 132 #define MT_FL_Q2_CTRL MT_PLE(0x3e8) 133 #define MT_FL_Q3_CTRL MT_PLE(0x3ec) 134 135 #define MT_PLE_FREEPG_CNT MT_PLE(0x380) 136 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384) 137 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c) 138 #define MT_PLE_HIF_PG_INFO MT_PLE(0x388) 139 140 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2)) 141 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 142 143 /* WF MDP TOP */ 144 #define MT_MDP_BASE 0x820cc000 145 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 146 147 #define MT_MDP_DCR2 MT_MDP(0x8e8) 148 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2) 149 150 /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */ 151 #define MT_WF_TMAC_BASE(_band) __BASE(WF_TMAC_BASE, (_band)) 152 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 153 154 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 155 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 156 157 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8) 158 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc) 159 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 160 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 161 162 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014) 163 #define MT_IFS_EIFS_OFDM GENMASK(8, 0) 164 #define MT_IFS_RIFS GENMASK(14, 10) 165 #define MT_IFS_SIFS GENMASK(22, 16) 166 #define MT_IFS_SLOT GENMASK(30, 24) 167 168 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018) 169 #define MT_IFS_EIFS_CCK GENMASK(8, 0) 170 171 /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */ 172 #define MT_WF_DMA_BASE(_band) __BASE(WF_DMA_BASE, (_band)) 173 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 174 175 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 176 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 177 178 #define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054) 179 #define MT_DMA_TCRF1_QIDX GENMASK(15, 13) 180 181 /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */ 182 #define MT_WTBLOFF_BASE(_band) __BASE(WF_WTBLOFF_BASE, (_band)) 183 #define MT_WTBLOFF(_band, ofs) (MT_WTBLOFF_BASE(_band) + (ofs)) 184 185 #define MT_WTBLOFF_RSCR(_band) MT_WTBLOFF(_band, 0x008) 186 #define MT_WTBLOFF_RSCR_RCPI_MODE GENMASK(31, 30) 187 #define MT_WTBLOFF_RSCR_RCPI_PARAM GENMASK(25, 24) 188 189 #define MT_WTBLOFF_ACR(_band) MT_WTBLOFF(_band, 0x010) 190 #define MT_WTBLOFF_ADM_BACKOFFTIME BIT(29) 191 192 /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */ 193 #define MT_WF_ETBF_BASE(_band) __BASE(WF_ETBF_BASE, (_band)) 194 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 195 196 #define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100) 197 #define MT_ETBF_RX_FB_BW GENMASK(10, 8) 198 #define MT_ETBF_RX_FB_NC GENMASK(7, 4) 199 #define MT_ETBF_RX_FB_NR GENMASK(3, 0) 200 201 /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */ 202 #define MT_WF_LPON_BASE(_band) __BASE(WF_LPON_BASE, (_band)) 203 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 204 205 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360) 206 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364) 207 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c) 208 209 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4)) 210 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 211 #define MT_LPON_TCR_SW_WRITE BIT(0) 212 #define MT_LPON_TCR_SW_ADJUST BIT(1) 213 #define MT_LPON_TCR_SW_READ GENMASK(1, 0) 214 215 /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/ 216 /* These counters are (mostly?) clear-on-read. So, some should not 217 * be read at all in case firmware is already reading them. These 218 * are commented with 'DNR' below. The DNR stats will be read by querying 219 * the firmware API for the appropriate message. For counters the driver 220 * does read, the driver should accumulate the counters. 221 */ 222 #define MT_WF_MIB_BASE(_band) __BASE(WF_MIB_BASE, (_band)) 223 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 224 225 #define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR0)) 226 #define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR1)) 227 #define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR2)) 228 #define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR3)) 229 #define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR4)) 230 #define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR5)) 231 #define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR6)) 232 #define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR7)) 233 #define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR17)) 234 235 #define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4) 236 #define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8) 237 #define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0) 238 239 #define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR1)) 240 /* rx mpdu counter, full 32 bits */ 241 #define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR31)) 242 #define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR33)) 243 244 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 245 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 246 247 #define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR0)) 248 249 #define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR35)) 250 #define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR36)) 251 252 /* tx ampdu cnt, full 32 bits */ 253 #define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0) 254 #define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8) 255 256 /* counts all mpdus in ampdu, regardless of success */ 257 #define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc) 258 259 /* counts all successfully tx'd mpdus in ampdu */ 260 #define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0) 261 262 /* rx ampdu count, 32-bit */ 263 #define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR27)) 264 265 /* rx ampdu bytes count, 32-bit */ 266 #define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR28)) 267 268 /* rx ampdu valid subframe count */ 269 #define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR29)) 270 271 /* rx ampdu valid subframe bytes count, 32bits */ 272 #define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR30)) 273 274 /* remaining windows protected stats */ 275 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080) 276 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0) 277 278 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084) 279 #define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0) 280 281 #define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR1)) 282 283 /* rx blockack count, 32 bits */ 284 #define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4) 285 286 #define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0) 287 #define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR5)) 288 #define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR6)) 289 290 #define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0) 291 292 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(MIB_TRDR1) + ((n) << 2)) 293 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2)) 294 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0)) 295 296 /* UMIB */ 297 #define MT_WF_UMIB_BASE 0x820cd000 298 #define MT_WF_UMIB(ofs) (MT_WF_UMIB_BASE + (ofs)) 299 300 #define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + (_band) * 0x164) 301 302 /* WTBLON TOP */ 303 #define MT_WTBLON_TOP_BASE 0x820d4000 304 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 305 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_WDUCR)) 306 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) 307 308 #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) 309 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0) 310 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14) 311 #define MT_WTBL_UPDATE_BUSY BIT(31) 312 313 #define MT_WTBL_ITCR MT_WTBLON_TOP(__OFFS(WTBL_ITCR)) 314 #define MT_WTBL_ITCR_WR BIT(16) 315 #define MT_WTBL_ITCR_EXEC BIT(31) 316 #define MT_WTBL_ITDR0 MT_WTBLON_TOP(__OFFS(WTBL_ITCR0)) 317 #define MT_WTBL_ITDR1 MT_WTBLON_TOP(__OFFS(WTBL_ITCR1)) 318 #define MT_WTBL_SPE_IDX_SEL BIT(6) 319 320 /* WTBL */ 321 #define MT_WTBL_BASE 0x820d8000 322 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 323 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 324 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 325 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 326 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 327 328 /* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */ 329 #define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band)) 330 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 331 332 #define MT_AGG_ACR4(_band) MT_WF_AGG(_band, 0x3c) 333 #define MT_AGG_ACR_PPDU_TXS2H BIT(1) 334 335 /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */ 336 #define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band)) 337 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 338 339 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000) 340 #define MT_ARB_SCR_TX_DISABLE BIT(8) 341 #define MT_ARB_SCR_RX_DISABLE BIT(9) 342 343 /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */ 344 #define MT_WF_RMAC_BASE(_band) __BASE(WF_RMAC_BASE, (_band)) 345 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 346 347 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 348 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 349 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 350 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 351 #define MT_WF_RFCR_DROP_MCAST BIT(5) 352 #define MT_WF_RFCR_DROP_BCAST BIT(6) 353 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 354 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 355 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 356 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 357 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 358 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 359 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 360 #define MT_WF_RFCR_DROP_CTS BIT(14) 361 #define MT_WF_RFCR_DROP_RTS BIT(15) 362 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 363 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 364 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 365 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 366 #define MT_WF_RFCR_DROP_NDPA BIT(20) 367 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 368 369 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 370 #define MT_WF_RFCR1_DROP_ACK BIT(4) 371 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 372 #define MT_WF_RFCR1_DROP_BA BIT(6) 373 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 374 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 375 376 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 377 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 378 #define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16) 379 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0) 380 381 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384) 382 #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16) 383 384 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c) 385 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0) 386 387 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390) 388 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0) 389 390 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0) 391 #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) 392 393 /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */ 394 #define MT_WF_RATE_BASE(_band) __BASE(WF_RATE_BASE, (_band)) 395 #define MT_WF_RATE(_band, ofs) (MT_WF_RATE_BASE(_band) + (ofs)) 396 397 #define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050) 398 #define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0) 399 400 /* WFDMA0 */ 401 #define MT_WFDMA0_BASE 0xd4000 402 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 403 404 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 405 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 406 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 407 408 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 409 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 410 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 411 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 412 413 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154) 414 #define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3) 415 #define MT_WFDMA0_RX_INT_SEL_RING6 BIT(6) 416 417 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 418 419 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 420 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 421 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 422 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 423 #define MT_WFDMA0_GLO_CFG_EXT_EN BIT(26) 424 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 425 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 426 427 #define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268) 428 #define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c) 429 #define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270) 430 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c) 431 432 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 433 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) 434 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) 435 436 #define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4) 437 #define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE BIT(31) 438 #define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE BIT(28) 439 440 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 441 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 442 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 443 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 444 445 /* WFDMA1 */ 446 #define MT_WFDMA1_BASE 0xd5000 447 448 /* WFDMA CSR */ 449 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 450 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 451 452 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 453 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 454 #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) 455 456 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 457 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 458 459 #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) 460 #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) 461 462 #define MT_PCIE_RECOG_ID 0xd7090 463 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 464 #define MT_PCIE_RECOG_ID_SEM BIT(31) 465 466 /* WFDMA0 PCIE1 */ 467 #define MT_WFDMA0_PCIE1_BASE 0xd8000 468 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 469 470 #define MT_INT_PCIE1_SOURCE_CSR_EXT MT_WFDMA0_PCIE1(0x118) 471 #define MT_INT_PCIE1_MASK_CSR MT_WFDMA0_PCIE1(0x11c) 472 473 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 474 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 475 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 476 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 477 478 /* WFDMA COMMON */ 479 #define __RXQ(q) ((q) + __MT_MCUQ_MAX) 480 #define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX) 481 482 #define MT_Q_ID(q) (dev->q_id[(q)]) 483 #define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \ 484 MT_WFDMA1_BASE : MT_WFDMA0_BASE) 485 486 #define MT_MCUQ_ID(q) MT_Q_ID(q) 487 #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 488 #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 489 490 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 491 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 492 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 493 #define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40) 494 495 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 496 MT_MCUQ_ID(q) * 0x4) 497 #define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 498 MT_RXQ_ID(q) * 0x4) 499 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 500 MT_TXQ_ID(q) * 0x4) 501 502 #define MT_INT_SOURCE_CSR MT_WFDMA0(0x200) 503 #define MT_INT_MASK_CSR MT_WFDMA0(0x204) 504 505 #define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200) 506 #define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204) 507 508 #define MT_INT_RX_DONE_BAND0 BIT(12) 509 #define MT_INT_RX_DONE_BAND1 BIT(13) /* for mt7992 */ 510 #define MT_INT_RX_DONE_BAND2 BIT(13) 511 #define MT_INT_RX_DONE_WM BIT(0) 512 #define MT_INT_RX_DONE_WA BIT(1) 513 #define MT_INT_RX_DONE_WA_MAIN BIT(2) 514 #define MT_INT_RX_DONE_WA_EXT BIT(3) /* for mt7992 */ 515 #define MT_INT_RX_DONE_WA_TRI BIT(3) 516 #define MT_INT_RX_TXFREE_MAIN BIT(17) 517 #define MT_INT_RX_TXFREE_TRI BIT(15) 518 #define MT_INT_RX_TXFREE_BAND0_MT7990 BIT(14) 519 #define MT_INT_RX_TXFREE_BAND1_MT7990 BIT(15) 520 #define MT_INT_RX_DONE_BAND2_EXT BIT(23) 521 #define MT_INT_RX_TXFREE_EXT BIT(26) 522 #define MT_INT_MCU_CMD BIT(29) 523 524 #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) 525 #define MT_INT_RX_DONE_RRO_BAND1 BIT(16) 526 #define MT_INT_RX_DONE_RRO_BAND2 BIT(14) 527 #define MT_INT_RX_DONE_RRO_IND BIT(11) 528 #define MT_INT_RX_DONE_MSDU_PG_BAND0 BIT(18) 529 #define MT_INT_RX_DONE_MSDU_PG_BAND1 BIT(19) 530 #define MT_INT_RX_DONE_MSDU_PG_BAND2 BIT(23) 531 532 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 533 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 534 535 #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 536 MT_INT_RX(MT_RXQ_MCU_WA)) 537 538 #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 539 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 540 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 541 542 #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \ 543 MT_INT_RX(MT_RXQ_BAND1_WA) | \ 544 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 545 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 546 547 #define MT_INT_BAND2_RX_DONE (MT_INT_RX(MT_RXQ_BAND2) | \ 548 MT_INT_RX(MT_RXQ_BAND2_WA) | \ 549 MT_INT_RX(MT_RXQ_MAIN_WA) | \ 550 MT_INT_RX(MT_RXQ_TXFREE_BAND0)) 551 552 #define MT_INT_RRO_RX_DONE (MT_INT_RX(MT_RXQ_RRO_BAND0) | \ 553 MT_INT_RX(MT_RXQ_RRO_BAND1) | \ 554 MT_INT_RX(MT_RXQ_RRO_BAND2) | \ 555 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND0) | \ 556 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND1) | \ 557 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND2)) 558 559 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 560 MT_INT_BAND0_RX_DONE | \ 561 MT_INT_BAND1_RX_DONE | \ 562 MT_INT_BAND2_RX_DONE | \ 563 MT_INT_RRO_RX_DONE) 564 565 #define MT_INT_TX_DONE_FWDL BIT(26) 566 #define MT_INT_TX_DONE_MCU_WM BIT(27) 567 #define MT_INT_TX_DONE_MCU_WA BIT(22) 568 #define MT_INT_TX_DONE_BAND0 BIT(30) 569 #define MT_INT_TX_DONE_BAND1 BIT(31) 570 #define MT_INT_TX_DONE_BAND2 BIT(15) 571 572 #define MT_INT_TX_RX_DONE_EXT (MT_INT_TX_DONE_BAND2 | \ 573 MT_INT_RX_DONE_BAND2_EXT | \ 574 MT_INT_RX_TXFREE_EXT) 575 576 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 577 MT_INT_TX_MCU(MT_MCUQ_WM) | \ 578 MT_INT_TX_MCU(MT_MCUQ_FWDL)) 579 580 #define MT_MCU_CMD MT_WFDMA0(0x1f0) 581 #define MT_MCU_CMD_STOP_DMA BIT(2) 582 #define MT_MCU_CMD_RESET_DONE BIT(3) 583 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 584 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 585 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 586 587 #define MT_MCU_CMD_WA_WDT BIT(31) 588 #define MT_MCU_CMD_WM_WDT BIT(30) 589 #define MT_MCU_CMD_WDT_MASK GENMASK(31, 30) 590 591 /* l1/l2 remap */ 592 #define CONN_BUS_CR_VON_BASE 0x155000 593 #define MT_HIF_REMAP_L1 (CONN_BUS_CR_VON_BASE + __OFFS(HIF_REMAP_L1)) 594 #define MT_HIF_REMAP_L1_MASK_7996 GENMASK(31, 16) 595 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 596 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 597 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 598 #define MT_HIF_REMAP_BASE_L1 __OFFS(HIF_REMAP_BASE_L1) 599 600 #define MT_HIF_REMAP_L2 __OFFS(HIF_REMAP_L2) 601 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 602 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 603 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 604 #define MT_HIF_REMAP_L2_MASK_7990 GENMASK(15, 0) 605 #define MT_HIF_REMAP_L2_OFFSET_7990 GENMASK(15, 0) 606 #define MT_HIF_REMAP_L2_BASE_7990 GENMASK(31, 16) 607 #define MT_HIF_REMAP_BASE_L2 __OFFS(HIF_REMAP_BASE_L2) 608 609 /* for mt7990 only */ 610 #define MT_HIF_REMAP_CBTOP 0x1f6554 611 #define MT_HIF_REMAP_CBTOP_MASK GENMASK(15, 0) 612 #define MT_HIF_REMAP_CBTOP_OFFSET GENMASK(15, 0) 613 #define MT_HIF_REMAP_CBTOP_BASE GENMASK(31, 16) 614 #define MT_HIF_REMAP_BASE_CBTOP 0x1c0000 615 616 #define MT_INFRA_BASE 0x18000000 617 #define MT_WFSYS0_PHY_START 0x18400000 618 #define MT_WFSYS1_PHY_START 0x18800000 619 #define MT_WFSYS1_PHY_END 0x18bfffff 620 #define MT_CBTOP1_PHY_START 0x70000000 621 #define MT_CBTOP1_PHY_END __OFFS(CBTOP1_PHY_END) 622 #define MT_CBTOP2_PHY_START 0xf0000000 623 #define MT_INFRA_MCU_START 0x7c000000 624 #define MT_INFRA_MCU_END __OFFS(INFRA_MCU_END) 625 626 /* FW MODE SYNC */ 627 #define MT_FW_ASSERT_CNT 0x02208274 628 #define MT_FW_DUMP_STATE 0x02209e90 629 630 #define MT_SWDEF_BASE 0x00401400 631 632 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 633 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 634 #define MT_SWDEF_NORMAL_MODE 0 635 636 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040) 637 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) 638 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) 639 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04c) 640 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) 641 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) 642 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) 643 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05c) 644 #define MT_SWDEF_LAMC_WISR6_BN2_STATS MT_SWDEF(0x060) 645 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x064) 646 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x068) 647 #define MT_SWDEF_LAMC_WISR7_BN2_STATS MT_SWDEF(0x06c) 648 649 /* LED */ 650 #define MT_LED_TOP_BASE 0x18013000 651 #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 652 653 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 654 #define MT_LED_CTRL_KICK BIT(7) 655 #define MT_LED_CTRL_BLINK_BAND_SEL BIT(4) 656 #define MT_LED_CTRL_BLINK_MODE BIT(2) 657 #define MT_LED_CTRL_POLARITY BIT(1) 658 659 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 660 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 661 #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 662 663 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 664 665 /* CONN DBG */ 666 #define MT_CONN_DBG_CTL_BASE 0x18023000 667 #define MT_CONN_DBG_CTL(ofs) (MT_CONN_DBG_CTL_BASE + (ofs)) 668 #define MT_CONN_DBG_CTL_OUT_SEL MT_CONN_DBG_CTL(0x604) 669 #define MT_CONN_DBG_CTL_PC_LOG_SEL MT_CONN_DBG_CTL(0x60c) 670 #define MT_CONN_DBG_CTL_PC_LOG MT_CONN_DBG_CTL(0x610) 671 672 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 673 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */ 674 #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8) 675 676 /* MT TOP */ 677 #define MT_TOP_BASE 0xe0000 678 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 679 680 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 681 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 682 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 683 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 684 685 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 686 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 687 688 #define MT_TOP_MISC MT_TOP(0xf0) 689 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 690 691 /* ADIE */ 692 #define MT_ADIE_CHIP_ID(_idx) (0x0f00002c + ((_idx) << 28)) 693 #define MT_ADIE_VERSION_MASK GENMASK(15, 0) 694 #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16) 695 696 #define MT_PAD_GPIO 0x700056f0 697 #define MT_PAD_GPIO_ADIE_COMB GENMASK(16, 15) 698 #define MT_PAD_GPIO_2ADIE_TBTC BIT(19) 699 /* for mt7992 */ 700 #define MT_PAD_GPIO_ADIE_COMB_7992 GENMASK(17, 16) 701 #define MT_PAD_GPIO_ADIE_SINGLE BIT(15) 702 703 #define MT_HW_REV 0x70010204 704 #define MT_HW_REV1 0x8a00 705 706 #define MT_WF_SUBSYS_RST 0x70028600 707 708 /* PCIE MAC */ 709 #define MT_PCIE_MAC_BASE 0x74030000 710 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 711 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 712 713 #define MT_PCIE1_MAC_BASE 0x74090000 714 #define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs)) 715 716 #define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188) 717 718 /* PHYRX CSD */ 719 #define MT_WF_PHYRX_CSD_BASE 0x83000000 720 #define MT_WF_PHYRX_CSD(_band, _wf, ofs) (MT_WF_PHYRX_CSD_BASE + \ 721 ((_band) << 20) + \ 722 ((_wf) << 16) + (ofs)) 723 #define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000) 724 725 /* PHYRX CTRL */ 726 #define MT_WF_PHYRX_BAND_BASE 0x83080000 727 #define MT_WF_PHYRX_BAND(_band, ofs) (MT_WF_PHYRX_BAND_BASE + \ 728 ((_band) << 20) + (ofs)) 729 730 #define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) MT_WF_PHYRX_BAND(_band, 0x1054) 731 #define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) MT_WF_PHYRX_BAND(_band, 0x1058) 732 #define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) MT_WF_PHYRX_BAND(_band, 0x105c) 733 #define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) MT_WF_PHYRX_BAND(_band, 0x1060) 734 #define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) MT_WF_PHYRX_BAND(_band, 0x1064) 735 #define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) MT_WF_PHYRX_BAND(_band, 0x1068) 736 737 #define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004) 738 #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0) 739 #define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 740 741 /* PHYRX CSD BAND */ 742 #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230) 743 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 744 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR BIT(29) 745 746 /* CONN MCU EXCP CON */ 747 #define MT_MCU_WM_EXCP_BASE 0x89050000 748 #define MT_MCU_WM_EXCP(ofs) (MT_MCU_WM_EXCP_BASE + (ofs)) 749 #define MT_MCU_WM_EXCP_PC_CTRL MT_MCU_WM_EXCP(0x100) 750 #define MT_MCU_WM_EXCP_PC_LOG MT_MCU_WM_EXCP(0x104) 751 #define MT_MCU_WM_EXCP_LR_CTRL MT_MCU_WM_EXCP(0x200) 752 #define MT_MCU_WM_EXCP_LR_LOG MT_MCU_WM_EXCP(0x204) 753 754 /* CONN AFE CTL CON */ 755 #define MT_AFE_CTL_BASE 0x18043000 756 #define MT_AFE_CTL_BAND(_band, ofs) (MT_AFE_CTL_BASE + \ 757 ((_band) * 0x1000) + (ofs)) 758 #define MT_AFE_CTL_BAND_PLL_03(_band) MT_AFE_CTL_BAND(_band, 0x2c) 759 #define MT_AFE_CTL_BAND_PLL_03_MSB_EN BIT(1) 760 761 #endif 762