1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #ifndef __MT7996_H
7 #define __MT7996_H
8
9 #include <linux/interrupt.h>
10 #include <linux/ktime.h>
11 #include "../mt76_connac.h"
12 #include "regs.h"
13
14 #define MT7996_MAX_RADIOS 3
15 #define MT7996_MAX_INTERFACES 19 /* per-band */
16 #define MT7996_MAX_WMM_SETS 4
17 #define MT7996_WTBL_BMC_SIZE (is_mt7996(&dev->mt76) ? 64 : 32)
18 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)
19 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \
20 mt7996_max_interface_num(dev))
21
22 #define MT7996_WATCHDOG_TIME (HZ / 10)
23 #define MT7996_RESET_TIMEOUT (30 * HZ)
24
25 #define MT7996_TX_RING_SIZE 2048
26 #define MT7996_TX_MCU_RING_SIZE 256
27 #define MT7996_TX_FWDL_RING_SIZE 128
28
29 #define MT7996_RX_RING_SIZE 1536
30 #define MT7996_RX_MCU_RING_SIZE 512
31 #define MT7996_RX_MCU_RING_SIZE_WA 1024
32 /* scatter-gather of mcu event is not supported in connac3 */
33 #define MT7996_RX_MCU_BUF_SIZE (2048 + \
34 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
35
36 #define MT7996_DEVICE_ID 0x7990
37 #define MT7996_DEVICE_ID_2 0x7991
38 #define MT7992_DEVICE_ID 0x7992
39 #define MT7992_DEVICE_ID_2 0x799a
40 #define MT7990_DEVICE_ID 0x7993
41 #define MT7990_DEVICE_ID_2 0x799b
42
43 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"
44 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"
45 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin"
46 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"
47
48 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin"
49 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin"
50 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP
51 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin"
52
53 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin"
54 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin"
55 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin"
56 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin"
57
58 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin"
59 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin"
60 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin"
61 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin"
62
63 #define MT7990_FIRMWARE_WA ""
64 #define MT7990_FIRMWARE_WM "mediatek/mt7996/mt7990_wm.bin"
65 #define MT7990_FIRMWARE_DSP ""
66 #define MT7990_ROM_PATCH "mediatek/mt7996/mt7990_rom_patch.bin"
67
68 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"
69 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin"
70 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin"
71 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin"
72
73 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin"
74 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin"
75 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin"
76 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin"
77 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin"
78
79 #define MT7990_EEPROM_DEFAULT "mediatek/mt7996/mt7990_eeprom.bin"
80 #define MT7990_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7990_eeprom_2i5i.bin"
81
82 #define MT7996_EEPROM_SIZE 7680
83 #define MT7996_EEPROM_BLOCK_SIZE 16
84 #define MT7996_TOKEN_SIZE 16384
85 #define MT7996_HW_TOKEN_SIZE 8192
86
87 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
88 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
89 #define MT7996_IBF_MAX_NC 2
90 #define MT7996_IBF_TIMEOUT 0x18
91 #define MT7996_IBF_TIMEOUT_LEGACY 0x48
92
93 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */
94 #define MT7992_IBF_TIMEOUT 0xff
95
96 #define MT7996_SKU_RATE_NUM 417
97 #define MT7996_SKU_PATH_NUM 494
98
99 #define MT7996_MAX_TWT_AGRT 16
100 #define MT7996_MAX_STA_TWT_AGRT 8
101 #define MT7996_MIN_TWT_DUR 64
102 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)
103
104 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */
105 #define MT7996_BASIC_RATES_TBL 31
106 #define MT7996_BEACON_RATES_TBL 25
107
108 #define MT7996_THERMAL_THROTTLE_MAX 100
109 #define MT7996_CDEV_THROTTLE_MAX 99
110 #define MT7996_CRIT_TEMP_IDX 0
111 #define MT7996_MAX_TEMP_IDX 1
112 #define MT7996_CRIT_TEMP 110
113 #define MT7996_MAX_TEMP 120
114
115 #define MT7996_MAX_HIF_RXD_IN_PG 5
116 #define MT7996_RRO_MSDU_PG_HASH_SIZE 127
117 #define MT7996_RRO_MAX_SESSION 1024
118 #define MT7996_RRO_WINDOW_MAX_LEN 1024
119 #define MT7996_RRO_ADDR_ELEM_LEN 128
120 #define MT7996_RRO_BA_BITMAP_LEN 2
121 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \
122 MT7996_RRO_BA_BITMAP_LEN)
123 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \
124 MT7996_RRO_ADDR_ELEM_LEN)
125 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \
126 MT7996_RRO_BA_BITMAP_SESSION_SIZE)
127
128 #define MT7996_RX_BUF_SIZE (1800 + \
129 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
130 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \
131 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
132
133 /* RRO 3.1 */
134 #define MT7996_RRO_MSDU_PG_CR_CNT 8
135 #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000
136
137 struct mt7996_vif;
138 struct mt7996_sta;
139 struct mt7996_dfs_pulse;
140 struct mt7996_dfs_pattern;
141
142 enum mt7996_ram_type {
143 MT7996_RAM_TYPE_WM,
144 MT7996_RAM_TYPE_WA,
145 MT7996_RAM_TYPE_DSP,
146 };
147
148 enum mt7996_var_type {
149 MT7996_VAR_TYPE_444,
150 MT7996_VAR_TYPE_233,
151 };
152
153 enum mt7992_var_type {
154 MT7992_VAR_TYPE_44,
155 MT7992_VAR_TYPE_23,
156 };
157
158 enum mt7990_var_type {
159 MT7990_VAR_TYPE_23,
160 };
161
162 enum mt7996_fem_type {
163 MT7996_FEM_EXT,
164 MT7996_FEM_INT,
165 MT7996_FEM_MIX,
166 };
167
168 enum mt7996_txq_id {
169 MT7996_TXQ_FWDL = 16,
170 MT7996_TXQ_MCU_WM,
171 MT7996_TXQ_BAND0,
172 MT7996_TXQ_BAND1,
173 MT7996_TXQ_MCU_WA,
174 MT7996_TXQ_BAND2,
175 };
176
177 enum mt7996_rxq_id {
178 MT7996_RXQ_MCU_WM = 0,
179 MT7996_RXQ_MCU_WA,
180 MT7996_RXQ_MCU_WA_MAIN = 2,
181 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */
182 MT7996_RXQ_MCU_WA_TRI = 3,
183 MT7996_RXQ_BAND0 = 4,
184 MT7996_RXQ_BAND1 = 5, /* for mt7992 */
185 MT7996_RXQ_BAND2 = 5,
186 MT7996_RXQ_RRO_BAND0 = 8,
187 MT7996_RXQ_RRO_BAND1 = 9,
188 MT7996_RXQ_RRO_BAND2 = 6,
189 MT7996_RXQ_MSDU_PG_BAND0 = 10,
190 MT7996_RXQ_MSDU_PG_BAND1 = 11,
191 MT7996_RXQ_MSDU_PG_BAND2 = 12,
192 MT7996_RXQ_TXFREE0 = 9,
193 MT7996_RXQ_TXFREE1 = 9,
194 MT7996_RXQ_TXFREE2 = 7,
195 MT7996_RXQ_RRO_IND = 0,
196 MT7996_RXQ_RRO_RXDMAD_C = 0,
197 MT7990_RXQ_TXFREE0 = 6,
198 MT7990_RXQ_TXFREE1 = 7,
199 };
200
201 struct mt7996_twt_flow {
202 struct list_head list;
203 u64 start_tsf;
204 u64 tsf;
205 u32 duration;
206 u16 wcid;
207 __le16 mantissa;
208 u8 exp;
209 u8 table_id;
210 u8 id;
211 u8 protection:1;
212 u8 flowtype:1;
213 u8 trigger:1;
214 u8 sched:1;
215 };
216
217 DECLARE_EWMA(avg_signal, 10, 8)
218
219 struct mt7996_sta_link {
220 struct mt76_wcid wcid; /* must be first */
221
222 struct mt7996_sta *sta;
223
224 struct list_head rc_list;
225 u32 airtime_ac[8];
226
227 int ack_signal;
228 struct ewma_avg_signal avg_ack_signal;
229
230 unsigned long changed;
231
232 struct mt76_connac_sta_key_conf bip;
233
234 struct {
235 u8 flowid_mask;
236 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];
237 } twt;
238
239 struct rcu_head rcu_head;
240 };
241
242 struct mt7996_sta {
243 struct mt7996_sta_link deflink; /* must be first */
244 struct mt7996_sta_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
245 u8 deflink_id;
246 u8 seclink_id;
247
248 struct mt7996_vif *vif;
249 };
250
251 struct mt7996_vif_link {
252 struct mt76_vif_link mt76; /* must be first */
253
254 struct mt7996_sta_link msta_link;
255 struct mt7996_phy *phy;
256
257 struct cfg80211_bitrate_mask bitrate_mask;
258
259 u8 mld_idx;
260 };
261
262 struct mt7996_vif_link_info {
263 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
264 };
265
266 struct mt7996_vif {
267 struct mt7996_vif_link deflink; /* must be first */
268 struct mt76_vif_data mt76;
269
270 struct mt7996_vif_link_info link_info[IEEE80211_MLD_MAX_NUM_LINKS];
271
272 u8 mld_group_idx;
273 u8 mld_remap_idx;
274 };
275
276 /* crash-dump */
277 struct mt7996_crash_data {
278 guid_t guid;
279 struct timespec64 timestamp;
280
281 u8 *memdump_buf;
282 size_t memdump_buf_len;
283 };
284
285 struct mt7996_hif {
286 struct list_head list;
287
288 struct device *dev;
289 void __iomem *regs;
290 int irq;
291
292 enum pci_bus_speed speed;
293 enum pcie_link_width width;
294 };
295
296 #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24)
297 #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4)
298 #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0)
299 struct mt7996_wed_rro_addr {
300 __le32 head_low;
301 __le32 data;
302 };
303
304 struct mt7996_wed_rro_session_id {
305 struct list_head list;
306 u16 id;
307 };
308
309 struct mt7996_msdu_page {
310 struct list_head list;
311
312 struct mt76_queue *q;
313 dma_addr_t dma_addr;
314 void *buf;
315 };
316
317 /* data1 */
318 #define RRO_HIF_DATA1_LS_MASK BIT(30)
319 #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16)
320 /* data4 */
321 #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0)
322 struct mt7996_rro_hif {
323 __le32 data0;
324 __le32 data1;
325 __le32 data2;
326 __le32 data3;
327 __le32 data4;
328 __le32 data5;
329 };
330
331 #define MSDU_PAGE_INFO_OWNER_MASK BIT(31)
332 #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0)
333 struct mt7996_msdu_page_info {
334 struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG];
335 __le32 pg_low;
336 __le32 data;
337 };
338
339 #define MT7996_MAX_RRO_RRS_RING 4
340 struct mt7996_rro_queue_regs_emi {
341 struct {
342 __le16 idx;
343 __le16 rsv;
344 } ring[MT7996_MAX_RRO_RRS_RING];
345 };
346
347 struct mt7996_phy {
348 struct mt76_phy *mt76;
349 struct mt7996_dev *dev;
350
351 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
352
353 struct thermal_cooling_device *cdev;
354 u8 cdev_state;
355 u8 throttle_state;
356 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
357
358 u32 rxfilter;
359 u64 omac_mask;
360
361 u16 noise;
362
363 s16 coverage_class;
364 u8 slottime;
365
366 u16 beacon_rate;
367
368 u32 rx_ampdu_ts;
369 u32 ampdu_ref;
370 int txpower;
371
372 struct mt76_mib_stats mib;
373 struct mt76_channel_state state_ts;
374
375 u16 orig_chainmask;
376 u16 orig_antenna_mask;
377
378 bool has_aux_rx;
379 bool counter_reset;
380 };
381
382 struct mt7996_dev {
383 union { /* must be first */
384 struct mt76_dev mt76;
385 struct mt76_phy mphy;
386 };
387
388 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS];
389 struct wiphy_radio radios[MT7996_MAX_RADIOS];
390 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS];
391
392 struct mt7996_hif *hif2;
393 struct mt7996_reg_desc reg;
394 u8 q_id[MT7996_MAX_QUEUE];
395 u32 q_int_mask[MT7996_MAX_QUEUE];
396 u32 q_wfdma_mask;
397
398 u64 mld_idx_mask;
399 u64 mld_remap_idx_mask;
400
401 const struct mt76_bus_ops *bus_ops;
402 struct mt7996_phy phy;
403
404 /* monitor rx chain configured channel */
405 struct cfg80211_chan_def rdd2_chandef;
406 struct mt7996_phy *rdd2_phy;
407
408 u16 chainmask;
409 u8 chainshift[__MT_MAX_BAND];
410 u32 hif_idx;
411
412 struct work_struct init_work;
413 struct work_struct rc_work;
414 struct work_struct dump_work;
415 struct work_struct reset_work;
416 wait_queue_head_t reset_wait;
417 struct {
418 u32 state;
419 u32 wa_reset_count;
420 u32 wm_reset_count;
421 bool hw_full_reset:1;
422 bool hw_init_done:1;
423 bool restart:1;
424 } recovery;
425
426 /* protects coredump data */
427 struct mutex dump_mutex;
428 #ifdef CONFIG_DEV_COREDUMP
429 struct {
430 struct mt7996_crash_data *crash_data;
431 } coredump;
432 #endif
433
434 struct list_head sta_rc_list;
435 struct list_head twt_list;
436
437 u32 hw_pattern;
438
439 bool flash_mode:1;
440 bool has_eht:1;
441
442 struct {
443 struct {
444 void *ptr;
445 dma_addr_t phy_addr;
446 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN];
447 struct {
448 void *ptr;
449 dma_addr_t phy_addr;
450 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN];
451 struct {
452 void *ptr;
453 dma_addr_t phy_addr;
454 } session;
455 struct {
456 void *ptr;
457 dma_addr_t phy_addr;
458 } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT];
459 struct {
460 struct mt7996_rro_queue_regs_emi *ptr;
461 dma_addr_t phy_addr;
462 } emi_rings_cpu;
463 struct {
464 struct mt7996_rro_queue_regs_emi *ptr;
465 dma_addr_t phy_addr;
466 } emi_rings_dma;
467
468 struct work_struct work;
469 struct list_head poll_list;
470 spinlock_t lock;
471
472 struct list_head page_cache;
473 struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE];
474 } wed_rro;
475
476 bool ibf;
477 u8 fw_debug_wm;
478 u8 fw_debug_wa;
479 u8 fw_debug_bin;
480 u16 fw_debug_seq;
481
482 struct dentry *debugfs_dir;
483 struct rchan *relay_fwlog;
484
485 struct {
486 u16 table_mask;
487 u8 n_agrt;
488 } twt;
489
490 spinlock_t reg_lock;
491
492 u8 wtbl_size_group;
493 struct {
494 u8 type:4;
495 u8 fem:4;
496 } var;
497 };
498
499 enum {
500 WFDMA0 = 0x0,
501 WFDMA1,
502 WFDMA_EXT,
503 __MT_WFDMA_MAX,
504 };
505
506 enum rdd_idx {
507 MT_RDD_IDX_BAND2, /* RDD idx for band idx 2 */
508 MT_RDD_IDX_BAND1, /* RDD idx for band idx 1 */
509 MT_RDD_IDX_BACKGROUND, /* RDD idx for background chain */
510 };
511
512 enum mt7996_rdd_cmd {
513 RDD_STOP,
514 RDD_START,
515 RDD_DET_MODE,
516 RDD_RADAR_EMULATE,
517 RDD_START_TXQ = 20,
518 RDD_CAC_START = 50,
519 RDD_CAC_END,
520 RDD_NORMAL_START,
521 RDD_DISABLE_DFS_CAL,
522 RDD_PULSE_DBG,
523 RDD_READ_PULSE,
524 RDD_RESUME_BF,
525 RDD_IRQ_OFF,
526 };
527
528 static inline int
mt7996_get_rdd_idx(struct mt7996_phy * phy,bool is_background)529 mt7996_get_rdd_idx(struct mt7996_phy *phy, bool is_background)
530 {
531 if (!phy->mt76->cap.has_5ghz)
532 return -1;
533
534 if (is_background)
535 return MT_RDD_IDX_BACKGROUND;
536
537 if (phy->mt76->band_idx == MT_BAND2)
538 return MT_RDD_IDX_BAND2;
539
540 return MT_RDD_IDX_BAND1;
541 }
542
543 static inline struct mt7996_dev *
mt7996_hw_dev(struct ieee80211_hw * hw)544 mt7996_hw_dev(struct ieee80211_hw *hw)
545 {
546 struct mt76_phy *phy = hw->priv;
547
548 return container_of(phy->dev, struct mt7996_dev, mt76);
549 }
550
551 static inline struct mt7996_phy *
__mt7996_phy(struct mt7996_dev * dev,enum mt76_band_id band)552 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)
553 {
554 struct mt76_phy *phy = dev->mt76.phys[band];
555
556 if (!phy)
557 return NULL;
558
559 return phy->priv;
560 }
561
562 static inline struct mt7996_phy *
mt7996_phy2(struct mt7996_dev * dev)563 mt7996_phy2(struct mt7996_dev *dev)
564 {
565 return __mt7996_phy(dev, MT_BAND1);
566 }
567
568 static inline struct mt7996_phy *
mt7996_phy3(struct mt7996_dev * dev)569 mt7996_phy3(struct mt7996_dev *dev)
570 {
571 return __mt7996_phy(dev, MT_BAND2);
572 }
573
574 static inline bool
mt7996_band_valid(struct mt7996_dev * dev,u8 band)575 mt7996_band_valid(struct mt7996_dev *dev, u8 band)
576 {
577 if (!is_mt7996(&dev->mt76))
578 return band <= MT_BAND1;
579
580 return band <= MT_BAND2;
581 }
582
583 static inline struct mt7996_phy *
mt7996_band_phy(struct mt7996_dev * dev,enum nl80211_band band)584 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band)
585 {
586 struct mt76_phy *mphy;
587
588 mphy = dev->mt76.band_phys[band];
589 if (!mphy)
590 return NULL;
591
592 return mphy->priv;
593 }
594
595 static inline struct mt7996_vif_link *
mt7996_vif_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,int link_id)596 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id)
597 {
598 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id);
599 }
600
601 static inline struct mt7996_phy *
mt7996_vif_link_phy(struct mt7996_vif_link * link)602 mt7996_vif_link_phy(struct mt7996_vif_link *link)
603 {
604 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76);
605
606 if (!mphy)
607 return NULL;
608
609 return mphy->priv;
610 }
611
612 static inline struct mt7996_vif_link *
mt7996_vif_conf_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)613 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif,
614 struct ieee80211_bss_conf *link_conf)
615 {
616 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif,
617 link_conf);
618 }
619
620 #define mt7996_for_each_phy(dev, phy) \
621 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \
622 if (((phy) = (dev)->radio_phy[__i]) != NULL)
623
624 extern const struct ieee80211_ops mt7996_ops;
625 extern struct pci_driver mt7996_pci_driver;
626 extern struct pci_driver mt7996_hif_driver;
627
628 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
629 void __iomem *mem_base, u32 device_id);
630 void mt7996_rro_hw_init(struct mt7996_dev *dev);
631 void mt7996_wfsys_reset(struct mt7996_dev *dev);
632 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);
633 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link);
634 int mt7996_register_device(struct mt7996_dev *dev);
635 void mt7996_unregister_device(struct mt7996_dev *dev);
636 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif,
637 struct ieee80211_bss_conf *link_conf,
638 struct mt76_vif_link *mlink);
639 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif,
640 struct ieee80211_bss_conf *link_conf,
641 struct mt76_vif_link *mlink);
642 int mt7996_eeprom_init(struct mt7996_dev *dev);
643 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);
644 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,
645 struct ieee80211_channel *chan);
646 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);
647 bool mt7996_eeprom_has_background_radar(struct mt7996_dev *dev);
648 int mt7996_dma_init(struct mt7996_dev *dev);
649 void mt7996_dma_reset(struct mt7996_dev *dev, bool force);
650 void mt7996_dma_prefetch(struct mt7996_dev *dev);
651 void mt7996_dma_cleanup(struct mt7996_dev *dev);
652 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset);
653 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx,
654 int n_desc, int ring_base, struct mtk_wed_device *wed);
655 void mt7996_init_txpower(struct mt7996_phy *phy);
656 int mt7996_txbf_init(struct mt7996_dev *dev);
657 void mt7996_reset(struct mt7996_dev *dev);
658 int mt7996_run(struct mt7996_phy *phy);
659 int mt7996_mcu_init(struct mt7996_dev *dev);
660 int mt7996_mcu_init_firmware(struct mt7996_dev *dev);
661 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,
662 struct mt7996_vif_link *link,
663 struct mt7996_twt_flow *flow,
664 int cmd);
665 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
666 struct ieee80211_bss_conf *link_conf,
667 struct mt76_vif_link *mlink, bool enable);
668 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
669 struct ieee80211_bss_conf *link_conf,
670 struct mt76_vif_link *mlink,
671 struct mt7996_sta_link *msta_link, int enable);
672 int mt7996_mcu_add_sta(struct mt7996_dev *dev,
673 struct ieee80211_bss_conf *link_conf,
674 struct ieee80211_link_sta *link_sta,
675 struct mt7996_vif_link *link,
676 struct mt7996_sta_link *msta_link,
677 int conn_state, bool newly);
678 int mt7996_mcu_teardown_mld_sta(struct mt7996_dev *dev,
679 struct mt7996_vif_link *link,
680 struct mt7996_sta_link *msta_link);
681 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,
682 struct ieee80211_ampdu_params *params,
683 struct ieee80211_vif *vif, bool enable);
684 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,
685 struct ieee80211_ampdu_params *params,
686 struct ieee80211_vif *vif, bool enable);
687 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev,
688 struct mt76_vif_link *mlink,
689 struct cfg80211_he_bss_color *he_bss_color);
690 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
691 struct ieee80211_bss_conf *link_conf, bool enabled);
692 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
693 struct ieee80211_bss_conf *link_conf,
694 struct mt7996_vif_link *link, u32 changed);
695 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy,
696 struct mt7996_vif_link *link,
697 struct ieee80211_he_obss_pd *he_obss_pd);
698 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct mt7996_sta *msta,
699 struct ieee80211_vif *vif, u8 link_id,
700 bool changed);
701 int mt7996_set_channel(struct mt76_phy *mphy);
702 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);
703 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif,
704 struct ieee80211_bss_conf *link_conf);
705 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,
706 void *data, u16 version);
707 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct mt7996_sta *msta,
708 void *data, u8 link_id, u32 field);
709 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);
710 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len);
711 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num);
712 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);
713 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);
714 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);
715 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);
716 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,
717 const struct mt7996_dfs_pulse *pulse);
718 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,
719 const struct mt7996_dfs_pattern *pattern);
720 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);
721 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);
722 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif,
723 struct ieee80211_bss_conf *link_conf);
724 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);
725 int mt7996_mcu_get_temperature(struct mt7996_phy *phy);
726 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state);
727 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable);
728 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy);
729 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 rdd_idx, u8 val);
730 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,
731 struct cfg80211_chan_def *chandef);
732 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,
733 u16 rate_idx, bool beacon);
734 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
735 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
736 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
737 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
738 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
739 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
740 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);
741 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);
742 void mt7996_mcu_exit(struct mt7996_dev *dev);
743 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag);
744 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id);
745 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled);
746
mt7996_has_hwrro(struct mt7996_dev * dev)747 static inline bool mt7996_has_hwrro(struct mt7996_dev *dev)
748 {
749 return dev->mt76.hwrro_mode != MT76_HWRRO_OFF;
750 }
751
mt7996_max_interface_num(struct mt7996_dev * dev)752 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)
753 {
754 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) +
755 mt7996_band_valid(dev, MT_BAND2)),
756 MT7996_WTBL_BMC_SIZE);
757 }
758
mt7996_wtbl_size(struct mt7996_dev * dev)759 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)
760 {
761 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE;
762 }
763
764 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
765 u32 clear, u32 set);
766
mt7996_irq_enable(struct mt7996_dev * dev,u32 mask)767 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)
768 {
769 if (dev->hif2)
770 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);
771 else
772 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
773
774 tasklet_schedule(&dev->mt76.irq_tasklet);
775 }
776
mt7996_irq_disable(struct mt7996_dev * dev,u32 mask)777 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)
778 {
779 if (dev->hif2)
780 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);
781 else
782 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
783 }
784
785 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
786 size_t len);
787
mt7996_rx_chainmask(struct mt7996_phy * phy)788 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy)
789 {
790 int max_nss = hweight16(phy->orig_antenna_mask);
791 int cur_nss = hweight8(phy->mt76->antenna_mask);
792 u16 tx_chainmask = phy->mt76->chainmask;
793
794 if (cur_nss != max_nss)
795 return tx_chainmask;
796
797 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx);
798 }
799
mt7996_has_wa(struct mt7996_dev * dev)800 static inline bool mt7996_has_wa(struct mt7996_dev *dev)
801 {
802 return !is_mt7990(&dev->mt76);
803 }
804
805 void mt7996_mac_init(struct mt7996_dev *dev);
806 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);
807 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);
808 void mt7996_mac_reset_counters(struct mt7996_phy *phy);
809 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);
810 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
811 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
812 struct sk_buff *skb, struct mt76_wcid *wcid,
813 struct ieee80211_key_conf *key, int pid,
814 enum mt76_txq_id qid, u32 changed);
815 void mt7996_mac_update_beacons(struct mt7996_phy *phy);
816 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
817 void mt7996_mac_work(struct work_struct *work);
818 void mt7996_mac_reset_work(struct work_struct *work);
819 void mt7996_mac_dump_work(struct work_struct *work);
820 void mt7996_mac_sta_rc_work(struct work_struct *work);
821 void mt7996_mac_update_stats(struct mt7996_phy *phy);
822 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,
823 struct mt7996_vif_link *link,
824 struct mt7996_sta_link *msta_link,
825 u8 flowid);
826 void mt7996_mac_sta_deinit_link(struct mt7996_dev *dev,
827 struct mt7996_sta_link *msta_link);
828 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,
829 struct ieee80211_sta *sta,
830 struct ieee80211_twt_setup *twt);
831 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
832 enum mt76_txq_id qid, struct mt76_wcid *wcid,
833 struct ieee80211_sta *sta,
834 struct mt76_tx_info *tx_info);
835 void mt7996_tx_token_put(struct mt7996_dev *dev);
836 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
837 struct sk_buff *skb, u32 *info);
838 void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev);
839 int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q,
840 dma_addr_t dma_addr, void *data);
841 void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data);
842 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);
843 void mt7996_stats_work(struct work_struct *work);
844 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);
845 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);
846 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);
847 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);
848 void mt7996_update_channel(struct mt76_phy *mphy);
849 int mt7996_init_debugfs(struct mt7996_dev *dev);
850 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);
851 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);
852 int mt7996_mcu_add_key(struct mt76_dev *dev, struct mt7996_vif_link *link,
853 struct ieee80211_key_conf *key, int mcu_cmd,
854 struct mt76_wcid *wcid, enum set_key_cmd cmd);
855 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev,
856 struct mt7996_vif_link *link,
857 struct mt7996_sta_link *msta_link,
858 struct ieee80211_key_conf *key);
859 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,
860 struct ieee80211_vif *vif,
861 struct mt7996_vif_link *link,
862 struct mt7996_sta_link *msta_link);
863 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode);
864 #ifdef CONFIG_MAC80211_DEBUGFS
865 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
866 struct ieee80211_sta *sta, struct dentry *dir);
867 void mt7996_link_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
868 struct ieee80211_link_sta *link_sta,
869 struct dentry *dir);
870 #endif
871 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
872 bool hif2, int *irq);
873 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
874
875 #ifdef CONFIG_MTK_DEBUG
876 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
877 #endif
878
879 int mt7996_dma_rro_init(struct mt7996_dev *dev);
880
881 #ifdef CONFIG_MT7996_NPU
882 int mt7996_npu_hw_init(struct mt7996_dev *dev);
883 int mt7996_npu_hw_stop(struct mt7996_dev *dev);
884 int mt7996_npu_rx_queues_init(struct mt7996_dev *dev);
885 #else
mt7996_npu_hw_init(struct mt7996_dev * dev)886 static inline int mt7996_npu_hw_init(struct mt7996_dev *dev)
887 {
888 return 0;
889 }
890
mt7996_npu_hw_stop(struct mt7996_dev * dev)891 static inline int mt7996_npu_hw_stop(struct mt7996_dev *dev)
892 {
893 return 0;
894 }
895
mt7996_npu_rx_queues_init(struct mt7996_dev * dev)896 static inline int mt7996_npu_rx_queues_init(struct mt7996_dev *dev)
897 {
898 return 0;
899 }
900 #endif /* CONFIG_MT7996_NPU */
901
902 #endif
903