1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2025 Arm Ltd.
3
4 #ifndef MPAM_INTERNAL_H
5 #define MPAM_INTERNAL_H
6
7 #include <linux/arm_mpam.h>
8 #include <linux/atomic.h>
9 #include <linux/bitmap.h>
10 #include <linux/cpumask.h>
11 #include <linux/io.h>
12 #include <linux/jump_label.h>
13 #include <linux/llist.h>
14 #include <linux/mutex.h>
15 #include <linux/resctrl.h>
16 #include <linux/spinlock.h>
17 #include <linux/srcu.h>
18 #include <linux/types.h>
19
20 #include <asm/mpam.h>
21
22 #define MPAM_MSC_MAX_NUM_RIS 16
23
24 struct platform_device;
25
26 #ifdef CONFIG_MPAM_KUNIT_TEST
27 #define PACKED_FOR_KUNIT __packed
28 #else
29 #define PACKED_FOR_KUNIT
30 #endif
31
32 /*
33 * This 'mon' values must not alias an actual monitor, so must be larger than
34 * U16_MAX, but not be confused with an errno value, so smaller than
35 * (u32)-SZ_4K.
36 * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor.
37 */
38 #define USE_PRE_ALLOCATED (U16_MAX + 1)
39
mpam_is_enabled(void)40 static inline bool mpam_is_enabled(void)
41 {
42 return static_branch_likely(&mpam_enabled);
43 }
44
45 /*
46 * Structures protected by SRCU may not be freed for a surprising amount of
47 * time (especially if perf is running). To ensure the MPAM error interrupt can
48 * tear down all the structures, build a list of objects that can be garbage
49 * collected once synchronize_srcu() has returned.
50 * If pdev is non-NULL, use devm_kfree().
51 */
52 struct mpam_garbage {
53 /* member of mpam_garbage */
54 struct llist_node llist;
55
56 void *to_free;
57 struct platform_device *pdev;
58 };
59
60 struct mpam_msc {
61 /* member of mpam_all_msc */
62 struct list_head all_msc_list;
63
64 int id;
65 struct platform_device *pdev;
66
67 /* Not modified after mpam_is_enabled() becomes true */
68 enum mpam_msc_iface iface;
69 u32 nrdy_usec;
70 cpumask_t accessibility;
71 bool has_extd_esr;
72
73 int reenable_error_ppi;
74 struct mpam_msc * __percpu *error_dev_id;
75
76 atomic_t online_refs;
77
78 /*
79 * probe_lock is only taken during discovery. After discovery these
80 * properties become read-only and the lists are protected by SRCU.
81 */
82 struct mutex probe_lock;
83 bool probed;
84 u16 partid_max;
85 u8 pmg_max;
86 unsigned long ris_idxs;
87 u32 ris_max;
88 u32 iidr;
89 u16 quirks;
90
91 /*
92 * error_irq_lock is taken when registering/unregistering the error
93 * interrupt and maniupulating the below flags.
94 */
95 struct mutex error_irq_lock;
96 bool error_irq_req;
97 bool error_irq_hw_enabled;
98
99 /* mpam_msc_ris of this component */
100 struct list_head ris;
101
102 /*
103 * part_sel_lock protects access to the MSC hardware registers that are
104 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary
105 * by RIS).
106 * If needed, take msc->probe_lock first.
107 */
108 struct mutex part_sel_lock;
109
110 /*
111 * cfg_lock protects the msc configuration and guards against mbwu_state
112 * save and restore racing.
113 */
114 struct mutex cfg_lock;
115
116 /*
117 * mon_sel_lock protects access to the MSC hardware registers that are
118 * affected by MPAMCFG_MON_SEL, and the mbwu_state.
119 * Access to mon_sel is needed from both process and interrupt contexts,
120 * but is complicated by firmware-backed platforms that can't make any
121 * access unless they can sleep.
122 * Always use the mpam_mon_sel_lock() helpers.
123 * Accesses to mon_sel need to be able to fail if they occur in the wrong
124 * context.
125 * If needed, take msc->probe_lock first.
126 */
127 raw_spinlock_t _mon_sel_lock;
128 unsigned long _mon_sel_flags;
129
130 void __iomem *mapped_hwpage;
131 size_t mapped_hwpage_sz;
132
133 /* Values only used on some platforms for quirks */
134 u32 t241_id;
135
136 struct mpam_garbage garbage;
137 };
138
139 /* Returning false here means accesses to mon_sel must fail and report an error. */
mpam_mon_sel_lock(struct mpam_msc * msc)140 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc)
141 {
142 /* Locking will require updating to support a firmware backed interface */
143 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO))
144 return false;
145
146 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags);
147 return true;
148 }
149
mpam_mon_sel_unlock(struct mpam_msc * msc)150 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc)
151 {
152 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags);
153 }
154
mpam_mon_sel_lock_held(struct mpam_msc * msc)155 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc)
156 {
157 lockdep_assert_held_once(&msc->_mon_sel_lock);
158 }
159
mpam_mon_sel_lock_init(struct mpam_msc * msc)160 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc)
161 {
162 raw_spin_lock_init(&msc->_mon_sel_lock);
163 }
164
165 /* Bits for mpam features bitmaps */
166 enum mpam_device_features {
167 mpam_feat_cpor_part,
168 mpam_feat_cmax_softlim,
169 mpam_feat_cmax_cmax,
170 mpam_feat_cmax_cmin,
171 mpam_feat_cmax_cassoc,
172 mpam_feat_mbw_part,
173 mpam_feat_mbw_min,
174 mpam_feat_mbw_max,
175 mpam_feat_mbw_prop,
176 mpam_feat_intpri_part,
177 mpam_feat_intpri_part_0_low,
178 mpam_feat_dspri_part,
179 mpam_feat_dspri_part_0_low,
180 mpam_feat_msmon,
181 mpam_feat_msmon_csu,
182 mpam_feat_msmon_csu_capture,
183 mpam_feat_msmon_csu_xcl,
184 mpam_feat_msmon_csu_hw_nrdy,
185 mpam_feat_msmon_mbwu,
186 mpam_feat_msmon_mbwu_31counter,
187 mpam_feat_msmon_mbwu_44counter,
188 mpam_feat_msmon_mbwu_63counter,
189 mpam_feat_msmon_mbwu_capture,
190 mpam_feat_msmon_mbwu_rwbw,
191 mpam_feat_msmon_mbwu_hw_nrdy,
192 mpam_feat_partid_nrw,
193 MPAM_FEATURE_LAST
194 };
195
196 struct mpam_props {
197 DECLARE_BITMAP(features, MPAM_FEATURE_LAST);
198
199 u16 cpbm_wd;
200 u16 mbw_pbm_bits;
201 u16 bwa_wd;
202 u16 cmax_wd;
203 u16 cassoc_wd;
204 u16 intpri_wd;
205 u16 dspri_wd;
206 u16 num_csu_mon;
207 u16 num_mbwu_mon;
208
209 /*
210 * Kunit tests use memset() to set up feature combinations that should be
211 * removed, and will false-positive if the compiler introduces padding that
212 * isn't cleared during sanitisation.
213 */
214 } PACKED_FOR_KUNIT;
215
216 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features)
217 /*
218 * The non-atomic get/set operations are used because if struct mpam_props is
219 * packed, the alignment requirements for atomics aren't met.
220 */
221 #define mpam_set_feature(_feat, x) __set_bit(_feat, (x)->features)
222 #define mpam_clear_feature(_feat, x) __clear_bit(_feat, (x)->features)
223
224 /* Workaround bits for msc->quirks */
225 enum mpam_device_quirks {
226 T241_SCRUB_SHADOW_REGS,
227 T241_FORCE_MBW_MIN_TO_ONE,
228 T241_MBW_COUNTER_SCALE_64,
229 IGNORE_CSU_NRDY,
230 MPAM_QUIRK_LAST
231 };
232
233 #define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks))
234 #define mpam_set_quirk(_quirk, x) ((x)->quirks |= (1 << (_quirk)))
235
236 struct mpam_quirk {
237 int (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk);
238
239 u32 iidr;
240 u32 iidr_mask;
241
242 enum mpam_device_quirks workaround;
243 };
244
245 #define MPAM_IIDR_MATCH_ONE (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0xfff) | \
246 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0xf) | \
247 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf) | \
248 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff))
249
250 #define MPAM_IIDR_NVIDIA_T241 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0x241) | \
251 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \
252 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \
253 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b))
254
255 #define MPAM_IIDR_ARM_CMN_650 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0) | \
256 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \
257 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \
258 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x43b))
259
260 /* The values for MSMON_CFG_MBWU_FLT.RWBW */
261 enum mon_filter_options {
262 COUNT_BOTH = 0,
263 COUNT_WRITE = 1,
264 COUNT_READ = 2,
265 };
266
267 struct mon_cfg {
268 /*
269 * mon must be large enough to hold out of range values like
270 * USE_PRE_ALLOCATED
271 */
272 u32 mon;
273 u8 pmg;
274 bool match_pmg;
275 bool csu_exclude_clean;
276 u32 partid;
277 enum mon_filter_options opts;
278 };
279
280 /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */
281 struct msmon_mbwu_state {
282 bool enabled;
283 bool reset_on_next_read;
284 struct mon_cfg cfg;
285
286 /*
287 * The value to add to the new reading to account for power management,
288 * and overflow.
289 */
290 u64 correction;
291
292 struct mpam_garbage garbage;
293 };
294
295 struct mpam_class {
296 /* mpam_components in this class */
297 struct list_head components;
298
299 cpumask_t affinity;
300
301 struct mpam_props props;
302 u32 nrdy_usec;
303 u16 quirks;
304 u8 level;
305 enum mpam_class_types type;
306
307 /* member of mpam_classes */
308 struct list_head classes_list;
309
310 struct ida ida_csu_mon;
311 struct ida ida_mbwu_mon;
312
313 struct mpam_garbage garbage;
314 };
315
316 struct mpam_config {
317 /* Which configuration values are valid. */
318 DECLARE_BITMAP(features, MPAM_FEATURE_LAST);
319
320 u32 cpbm;
321 u32 mbw_pbm;
322 u16 mbw_max;
323
324 struct mpam_garbage garbage;
325 };
326
327 struct mpam_component {
328 u32 comp_id;
329
330 /* mpam_vmsc in this component */
331 struct list_head vmsc;
332
333 cpumask_t affinity;
334
335 /*
336 * Array of configuration values, indexed by partid.
337 * Read from cpuhp callbacks, hold the cpuhp lock when writing.
338 */
339 struct mpam_config *cfg;
340
341 /* member of mpam_class:components */
342 struct list_head class_list;
343
344 /* parent: */
345 struct mpam_class *class;
346
347 struct mpam_garbage garbage;
348 };
349
350 struct mpam_vmsc {
351 /* member of mpam_component:vmsc_list */
352 struct list_head comp_list;
353
354 /* mpam_msc_ris in this vmsc */
355 struct list_head ris;
356
357 struct mpam_props props;
358
359 /* All RIS in this vMSC are members of this MSC */
360 struct mpam_msc *msc;
361
362 /* parent: */
363 struct mpam_component *comp;
364
365 struct mpam_garbage garbage;
366 };
367
368 struct mpam_msc_ris {
369 u8 ris_idx;
370 u64 idr;
371 struct mpam_props props;
372 bool in_reset_state;
373
374 cpumask_t affinity;
375
376 /* member of mpam_vmsc:ris */
377 struct list_head vmsc_list;
378
379 /* member of mpam_msc:ris */
380 struct list_head msc_list;
381
382 /* parent: */
383 struct mpam_vmsc *vmsc;
384
385 /* msmon mbwu configuration is preserved over reset */
386 struct msmon_mbwu_state *mbwu_state;
387
388 struct mpam_garbage garbage;
389 };
390
391 struct mpam_resctrl_dom {
392 struct mpam_component *ctrl_comp;
393
394 /*
395 * There is no single mon_comp because different events may be backed
396 * by different class/components. mon_comp is indexed by the event
397 * number.
398 */
399 struct mpam_component *mon_comp[QOS_NUM_EVENTS];
400
401 struct rdt_ctrl_domain resctrl_ctrl_dom;
402 struct rdt_l3_mon_domain resctrl_mon_dom;
403 };
404
405 struct mpam_resctrl_res {
406 struct mpam_class *class;
407 struct rdt_resource resctrl_res;
408 bool cdp_enabled;
409 };
410
411 struct mpam_resctrl_mon {
412 struct mpam_class *class;
413
414 /* per-class data that resctrl needs will live here */
415 };
416
mpam_alloc_csu_mon(struct mpam_class * class)417 static inline int mpam_alloc_csu_mon(struct mpam_class *class)
418 {
419 struct mpam_props *cprops = &class->props;
420
421 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops))
422 return -EOPNOTSUPP;
423
424 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1,
425 GFP_KERNEL);
426 }
427
mpam_free_csu_mon(struct mpam_class * class,int csu_mon)428 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon)
429 {
430 ida_free(&class->ida_csu_mon, csu_mon);
431 }
432
mpam_alloc_mbwu_mon(struct mpam_class * class)433 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class)
434 {
435 struct mpam_props *cprops = &class->props;
436
437 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops))
438 return -EOPNOTSUPP;
439
440 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1,
441 GFP_KERNEL);
442 }
443
mpam_free_mbwu_mon(struct mpam_class * class,int mbwu_mon)444 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon)
445 {
446 ida_free(&class->ida_mbwu_mon, mbwu_mon);
447 }
448
449 /* List of all classes - protected by srcu*/
450 extern struct srcu_struct mpam_srcu;
451 extern struct list_head mpam_classes;
452
453 /* System wide partid/pmg values */
454 extern u16 mpam_partid_max;
455 extern u8 mpam_pmg_max;
456
457 /* Scheduled work callback to enable mpam once all MSC have been probed */
458 void mpam_enable(struct work_struct *work);
459 void mpam_disable(struct work_struct *work);
460
461 /* Reset all the RIS in a class under cpus_read_lock() */
462 void mpam_reset_class_locked(struct mpam_class *class);
463
464 int mpam_apply_config(struct mpam_component *comp, u16 partid,
465 struct mpam_config *cfg);
466
467 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx,
468 enum mpam_device_features, u64 *val);
469 void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx);
470
471 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
472 cpumask_t *affinity);
473
474 #ifdef CONFIG_RESCTRL_FS
475 int mpam_resctrl_setup(void);
476 void mpam_resctrl_exit(void);
477 int mpam_resctrl_online_cpu(unsigned int cpu);
478 void mpam_resctrl_offline_cpu(unsigned int cpu);
479 void mpam_resctrl_teardown_class(struct mpam_class *class);
480 #else
mpam_resctrl_setup(void)481 static inline int mpam_resctrl_setup(void) { return 0; }
mpam_resctrl_exit(void)482 static inline void mpam_resctrl_exit(void) { }
mpam_resctrl_online_cpu(unsigned int cpu)483 static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; }
mpam_resctrl_offline_cpu(unsigned int cpu)484 static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { }
mpam_resctrl_teardown_class(struct mpam_class * class)485 static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { }
486 #endif /* CONFIG_RESCTRL_FS */
487
488 /*
489 * MPAM MSCs have the following register layout. See:
490 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System
491 * Component Specification.
492 * https://developer.arm.com/documentation/ihi0099/aa/
493 */
494 #define MPAM_ARCHITECTURE_V1 0x10
495
496 /* Memory mapped control pages */
497 /* ID Register offsets in the memory mapped page */
498 #define MPAMF_IDR 0x0000 /* features id register */
499 #define MPAMF_IIDR 0x0018 /* implementer id register */
500 #define MPAMF_AIDR 0x0020 /* architectural id register */
501 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
502 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
503 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
504 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
505 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
506 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */
507 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */
508 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */
509 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */
510
511 /* Configuration and Status Register offsets in the memory mapped page */
512 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */
513 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */
514 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */
515 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */
516 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */
517 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */
518 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */
519 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */
520 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */
521 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */
522 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */
523 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */
524
525 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */
526 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */
527 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */
528 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */
529 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */
530 #define MSMON_CSU 0x0840 /* current cache-usage */
531 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */
532 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */
533 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */
534 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */
535 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */
536 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */
537 #define MPAMF_ESR 0x00F8 /* error status register */
538 #define MPAMF_ECR 0x00F0 /* error control register */
539
540 /* MPAMF_IDR - MPAM features ID register */
541 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0)
542 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16)
543 #define MPAMF_IDR_HAS_CCAP_PART BIT(24)
544 #define MPAMF_IDR_HAS_CPOR_PART BIT(25)
545 #define MPAMF_IDR_HAS_MBW_PART BIT(26)
546 #define MPAMF_IDR_HAS_PRI_PART BIT(27)
547 #define MPAMF_IDR_EXT BIT(28)
548 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29)
549 #define MPAMF_IDR_HAS_MSMON BIT(30)
550 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31)
551 #define MPAMF_IDR_HAS_RIS BIT(32)
552 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38)
553 #define MPAMF_IDR_HAS_ESR BIT(39)
554 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56)
555
556 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
557 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16)
558 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17)
559 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31)
560
561 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
562 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0)
563
564 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
565 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0)
566 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8)
567 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28)
568 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29)
569 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30)
570 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31)
571
572 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
573 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
574 #define MPAMF_MBW_IDR_HAS_MIN BIT(10)
575 #define MPAMF_MBW_IDR_HAS_MAX BIT(11)
576 #define MPAMF_MBW_IDR_HAS_PBM BIT(12)
577 #define MPAMF_MBW_IDR_HAS_PROP BIT(13)
578 #define MPAMF_MBW_IDR_WINDWR BIT(14)
579 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)
580
581 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
582 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0)
583 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1)
584 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)
585 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16)
586 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17)
587 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)
588
589 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
590 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)
591 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24)
592 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25)
593 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26)
594 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27)
595 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29)
596 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30)
597 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31)
598
599 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
600 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)
601 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28)
602 #define MPAMF_MBWUMON_IDR_LWD BIT(29)
603 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30)
604 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31)
605
606 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */
607 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0)
608
609 /* MPAMF_IIDR - MPAM implementation ID register */
610 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0)
611 #define MPAMF_IIDR_REVISION GENMASK(15, 12)
612 #define MPAMF_IIDR_VARIANT GENMASK(19, 16)
613 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20)
614
615 /* MPAMF_AIDR - MPAM architecture ID register */
616 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0)
617 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4)
618
619 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */
620 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0)
621 #define MPAMCFG_PART_SEL_INTERNAL BIT(16)
622 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24)
623
624 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */
625 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0)
626
627 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */
628 #define MPAMCFG_CMAX_SOFTLIM BIT(31)
629 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0)
630
631 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */
632 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0)
633
634 /*
635 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration
636 * register
637 */
638 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0)
639
640 /*
641 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration
642 * register
643 */
644 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0)
645 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31)
646
647 /*
648 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width
649 * register
650 */
651 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0)
652 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8)
653
654 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */
655 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0)
656 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16)
657
658 /*
659 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning
660 * configuration register
661 */
662 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0)
663 #define MPAMCFG_MBW_PROP_EN BIT(31)
664
665 /*
666 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register
667 */
668 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0)
669 #define MPAMCFG_INTPARTID_INTERNAL BIT(16)
670
671 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */
672 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0)
673 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24)
674
675 /* MPAMF_ESR - MPAM Error Status Register */
676 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0)
677 #define MPAMF_ESR_PMG GENMASK(23, 16)
678 #define MPAMF_ESR_ERRCODE GENMASK(27, 24)
679 #define MPAMF_ESR_OVRWR BIT(31)
680 #define MPAMF_ESR_RIS GENMASK(35, 32)
681
682 /* MPAMF_ECR - MPAM Error Control Register */
683 #define MPAMF_ECR_INTEN BIT(0)
684
685 /* Error conditions in accessing memory mapped registers */
686 #define MPAM_ERRCODE_NONE 0
687 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1
688 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2
689 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3
690 #define MPAM_ERRCODE_REQ_PMG_RANGE 4
691 #define MPAM_ERRCODE_MONITOR_RANGE 5
692 #define MPAM_ERRCODE_INTPARTID_RANGE 6
693 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7
694 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8
695 #define MPAM_ERRCODE_RIS_NO_CONTROL 9
696 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10
697 #define MPAM_ERRCODE_RIS_NO_MONITOR 11
698
699 /*
700 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage
701 * usage monitor control register
702 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory
703 * bandwidth usage monitor control register
704 */
705 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0)
706 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15)
707 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16)
708 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17)
709 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19)
710 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20)
711 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24)
712 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25)
713 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26)
714 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27)
715 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28)
716 #define MSMON_CFG_x_CTL_EN BIT(31)
717
718 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42
719 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43
720
721 /*
722 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage
723 * usage monitor filter register
724 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
725 * bandwidth usage monitor filter register
726 */
727 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0)
728 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16)
729
730 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30)
731 #define MSMON_CFG_CSU_FLT_XCL BIT(31)
732
733 /*
734 * MSMON_CSU - Memory system performance monitor cache storage usage monitor
735 * register
736 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage
737 * capture register
738 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage
739 * monitor register
740 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
741 * capture register
742 */
743 #define MSMON___VALUE GENMASK(30, 0)
744 #define MSMON___NRDY BIT(31)
745 #define MSMON___L_NRDY BIT(63)
746 #define MSMON___L_VALUE GENMASK(43, 0)
747 #define MSMON___LWD_VALUE GENMASK(62, 0)
748
749 /*
750 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event
751 * generation register
752 */
753 #define MSMON_CAPT_EVNT_NOW BIT(0)
754
755 #endif /* MPAM_INTERNAL_H */
756