1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Register definition file for Samsung MFC V6.x Interface (FIMV) driver 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com/ 7 */ 8 9 #ifndef _REGS_FIMV_V6_H 10 #define _REGS_FIMV_V6_H 11 12 #include <linux/kernel.h> 13 #include <linux/sizes.h> 14 15 #define S5P_FIMV_REG_SIZE_V6 (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) 16 #define S5P_FIMV_REG_COUNT_V6 ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4) 17 18 /* Number of bits that the buffer address should be shifted for particular 19 * MFC buffers. */ 20 #define S5P_FIMV_MEM_OFFSET_V6 0 21 22 #define S5P_FIMV_START_ADDR_V6 0x0000 23 #define S5P_FIMV_END_ADDR_V6 0xfd80 24 25 #define S5P_FIMV_REG_CLEAR_BEGIN_V6 0xf000 26 #define S5P_FIMV_REG_CLEAR_COUNT_V6 1024 27 28 /* Codec Common Registers */ 29 #define S5P_FIMV_RISC_ON_V6 0x0000 30 #define S5P_FIMV_RISC2HOST_INT_V6 0x003C 31 #define S5P_FIMV_HOST2RISC_INT_V6 0x0044 32 #define S5P_FIMV_RISC_BASE_ADDRESS_V6 0x0054 33 34 #define S5P_FIMV_MFC_RESET_V6 0x1070 35 36 #define S5P_FIMV_HOST2RISC_CMD_V6 0x1100 37 #define S5P_FIMV_H2R_CMD_EMPTY_V6 0 38 #define S5P_FIMV_H2R_CMD_SYS_INIT_V6 1 39 #define S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6 2 40 #define S5P_FIMV_CH_SEQ_HEADER_V6 3 41 #define S5P_FIMV_CH_INIT_BUFS_V6 4 42 #define S5P_FIMV_CH_FRAME_START_V6 5 43 #define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6 6 44 #define S5P_FIMV_H2R_CMD_SLEEP_V6 7 45 #define S5P_FIMV_H2R_CMD_WAKEUP_V6 8 46 #define S5P_FIMV_CH_LAST_FRAME_V6 9 47 #define S5P_FIMV_H2R_CMD_FLUSH_V6 10 48 #define S5P_FIMV_H2R_CMD_NAL_ABORT_V6 11 49 /* RMVME: REALLOC used? */ 50 #define S5P_FIMV_CH_FRAME_START_REALLOC_V6 5 51 52 #define S5P_FIMV_RISC2HOST_CMD_V6 0x1104 53 #define S5P_FIMV_R2H_CMD_EMPTY_V6 0 54 #define S5P_FIMV_R2H_CMD_SYS_INIT_RET_V6 1 55 #define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET_V6 2 56 #define S5P_FIMV_R2H_CMD_SEQ_DONE_RET_V6 3 57 #define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET_V6 4 58 59 #define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET_V6 6 60 #define S5P_FIMV_R2H_CMD_SLEEP_RET_V6 7 61 #define S5P_FIMV_R2H_CMD_WAKEUP_RET_V6 8 62 #define S5P_FIMV_R2H_CMD_COMPLETE_SEQ_RET_V6 9 63 #define S5P_FIMV_R2H_CMD_DPB_FLUSH_RET_V6 10 64 #define S5P_FIMV_R2H_CMD_NAL_ABORT_RET_V6 11 65 #define S5P_FIMV_R2H_CMD_FW_STATUS_RET_V6 12 66 #define S5P_FIMV_R2H_CMD_FRAME_DONE_RET_V6 13 67 #define S5P_FIMV_R2H_CMD_FIELD_DONE_RET_V6 14 68 #define S5P_FIMV_R2H_CMD_SLICE_DONE_RET_V6 15 69 #define S5P_FIMV_R2H_CMD_ENC_BUFFER_FUL_RET_V6 16 70 #define S5P_FIMV_R2H_CMD_ERR_RET_V6 32 71 72 #define S5P_FIMV_MFC_BUS_RESET_CTRL 0x7110 73 #define S5P_FIMV_FW_VERSION_V6 0xf000 74 75 #define S5P_FIMV_INSTANCE_ID_V6 0xf008 76 #define S5P_FIMV_CODEC_TYPE_V6 0xf00c 77 #define S5P_FIMV_CONTEXT_MEM_ADDR_V6 0xf014 78 #define S5P_FIMV_CONTEXT_MEM_SIZE_V6 0xf018 79 #define S5P_FIMV_PIXEL_FORMAT_V6 0xf020 80 81 #define S5P_FIMV_METADATA_ENABLE_V6 0xf024 82 #define S5P_FIMV_DBG_BUFFER_ADDR_V6 0xf030 83 #define S5P_FIMV_DBG_BUFFER_SIZE_V6 0xf034 84 #define S5P_FIMV_RET_INSTANCE_ID_V6 0xf070 85 86 #define S5P_FIMV_ERROR_CODE_V6 0xf074 87 #define S5P_FIMV_ERR_WARNINGS_START_V6 160 88 #define S5P_FIMV_ERR_DEC_MASK_V6 0xffff 89 #define S5P_FIMV_ERR_DEC_SHIFT_V6 0 90 #define S5P_FIMV_ERR_DSPL_MASK_V6 0xffff0000 91 #define S5P_FIMV_ERR_DSPL_SHIFT_V6 16 92 93 #define S5P_FIMV_DBG_BUFFER_OUTPUT_SIZE_V6 0xf078 94 #define S5P_FIMV_METADATA_STATUS_V6 0xf07C 95 #define S5P_FIMV_METADATA_ADDR_MB_INFO_V6 0xf080 96 #define S5P_FIMV_METADATA_SIZE_MB_INFO_V6 0xf084 97 98 /* Decoder Registers */ 99 #define S5P_FIMV_D_CRC_CTRL_V6 0xf0b0 100 #define S5P_FIMV_D_DEC_OPTIONS_V6 0xf0b4 101 #define S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6 4 102 #define S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6 3 103 #define S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6 1 104 #define S5P_FIMV_D_OPT_LF_CTRL_MASK_V6 0x3 105 #define S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6 0 106 107 #define S5P_FIMV_D_DISPLAY_DELAY_V6 0xf0b8 108 109 #define S5P_FIMV_D_SET_FRAME_WIDTH_V6 0xf0bc 110 #define S5P_FIMV_D_SET_FRAME_HEIGHT_V6 0xf0c0 111 112 #define S5P_FIMV_D_SEI_ENABLE_V6 0xf0c4 113 114 /* Buffer setting registers */ 115 #define S5P_FIMV_D_MIN_NUM_DPB_V6 0xf0f0 116 #define S5P_FIMV_D_MIN_LUMA_DPB_SIZE_V6 0xf0f4 117 #define S5P_FIMV_D_MIN_CHROMA_DPB_SIZE_V6 0xf0f8 118 #define S5P_FIMV_D_MVC_NUM_VIEWS_V6 0xf0fc 119 #define S5P_FIMV_D_MIN_NUM_MV_V6 0xf100 120 #define S5P_FIMV_D_NUM_DPB_V6 0xf130 121 #define S5P_FIMV_D_LUMA_DPB_SIZE_V6 0xf134 122 #define S5P_FIMV_D_CHROMA_DPB_SIZE_V6 0xf138 123 #define S5P_FIMV_D_MV_BUFFER_SIZE_V6 0xf13c 124 125 #define S5P_FIMV_D_LUMA_DPB_V6 0xf140 126 #define S5P_FIMV_D_CHROMA_DPB_V6 0xf240 127 #define S5P_FIMV_D_MV_BUFFER_V6 0xf340 128 129 #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6 0xf440 130 #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6 0xf444 131 #define S5P_FIMV_D_METADATA_BUFFER_ADDR_V6 0xf448 132 #define S5P_FIMV_D_METADATA_BUFFER_SIZE_V6 0xf44c 133 #define S5P_FIMV_D_NUM_MV_V6 0xf478 134 #define S5P_FIMV_D_CPB_BUFFER_ADDR_V6 0xf4b0 135 #define S5P_FIMV_D_CPB_BUFFER_SIZE_V6 0xf4b4 136 137 #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER_V6 0xf4b8 138 #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6 0xf4bc 139 #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V6 0xf4c0 140 #define S5P_FIMV_D_SLICE_IF_ENABLE_V6 0xf4c4 141 #define S5P_FIMV_D_PICTURE_TAG_V6 0xf4c8 142 #define S5P_FIMV_D_STREAM_DATA_SIZE_V6 0xf4d0 143 #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6 0xf47c 144 145 /* Display information register */ 146 #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6 0xf500 147 #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6 0xf504 148 149 /* Display status */ 150 #define S5P_FIMV_D_DISPLAY_STATUS_V6 0xf508 151 152 #define S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6 0xf50c 153 #define S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6 0xf510 154 155 #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6 0xf514 156 157 #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V6 0xf518 158 #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V6 0xf51c 159 #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V6 0xf520 160 #define S5P_FIMV_D_DISPLAY_LUMA_CRC_TOP_V6 0xf524 161 #define S5P_FIMV_D_DISPLAY_CHROMA_CRC_TOP_V6 0xf528 162 #define S5P_FIMV_D_DISPLAY_LUMA_CRC_BOT_V6 0xf52c 163 #define S5P_FIMV_D_DISPLAY_CHROMA_CRC_BOT_V6 0xf530 164 #define S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6 0xf534 165 #define S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6 0xf538 166 167 /* Decoded picture information register */ 168 #define S5P_FIMV_D_DECODED_FRAME_WIDTH_V6 0xf53c 169 #define S5P_FIMV_D_DECODED_FRAME_HEIGHT_V6 0xf540 170 #define S5P_FIMV_D_DECODED_STATUS_V6 0xf544 171 #define S5P_FIMV_DEC_CRC_GEN_MASK_V6 0x1 172 #define S5P_FIMV_DEC_CRC_GEN_SHIFT_V6 6 173 174 #define S5P_FIMV_D_DECODED_LUMA_ADDR_V6 0xf548 175 #define S5P_FIMV_D_DECODED_CHROMA_ADDR_V6 0xf54c 176 177 #define S5P_FIMV_D_DECODED_FRAME_TYPE_V6 0xf550 178 #define S5P_FIMV_DECODE_FRAME_MASK_V6 7 179 180 #define S5P_FIMV_D_DECODED_CROP_INFO1_V6 0xf554 181 #define S5P_FIMV_D_DECODED_CROP_INFO2_V6 0xf558 182 #define S5P_FIMV_D_DECODED_PICTURE_PROFILE_V6 0xf55c 183 #define S5P_FIMV_D_DECODED_NAL_SIZE_V6 0xf560 184 #define S5P_FIMV_D_DECODED_LUMA_CRC_TOP_V6 0xf564 185 #define S5P_FIMV_D_DECODED_CHROMA_CRC_TOP_V6 0xf568 186 #define S5P_FIMV_D_DECODED_LUMA_CRC_BOT_V6 0xf56c 187 #define S5P_FIMV_D_DECODED_CHROMA_CRC_BOT_V6 0xf570 188 189 /* Returned value register for specific setting */ 190 #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6 0xf574 191 #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6 0xf578 192 #define S5P_FIMV_D_RET_PICTURE_TIME_TOP_V6 0xf57c 193 #define S5P_FIMV_D_RET_PICTURE_TIME_BOT_V6 0xf580 194 #define S5P_FIMV_D_CHROMA_FORMAT_V6 0xf588 195 #define S5P_FIMV_D_MPEG4_INFO_V6 0xf58c 196 #define S5P_FIMV_D_H264_INFO_V6 0xf590 197 198 #define S5P_FIMV_D_METADATA_ADDR_CONCEALED_MB_V6 0xf594 199 #define S5P_FIMV_D_METADATA_SIZE_CONCEALED_MB_V6 0xf598 200 #define S5P_FIMV_D_METADATA_ADDR_VC1_PARAM_V6 0xf59c 201 #define S5P_FIMV_D_METADATA_SIZE_VC1_PARAM_V6 0xf5a0 202 #define S5P_FIMV_D_METADATA_ADDR_SEI_NAL_V6 0xf5a4 203 #define S5P_FIMV_D_METADATA_SIZE_SEI_NAL_V6 0xf5a8 204 #define S5P_FIMV_D_METADATA_ADDR_VUI_V6 0xf5ac 205 #define S5P_FIMV_D_METADATA_SIZE_VUI_V6 0xf5b0 206 207 #define S5P_FIMV_D_MVC_VIEW_ID_V6 0xf5b4 208 209 /* SEI related information */ 210 #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6 0xf5f0 211 #define S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID_V6 0xf5f4 212 #define S5P_FIMV_D_FRAME_PACK_SEI_INFO_V6 0xf5f8 213 #define S5P_FIMV_D_FRAME_PACK_GRID_POS_V6 0xf5fc 214 215 /* Encoder Registers */ 216 #define S5P_FIMV_E_FRAME_WIDTH_V6 0xf770 217 #define S5P_FIMV_E_FRAME_HEIGHT_V6 0xf774 218 #define S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6 0xf778 219 #define S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6 0xf77c 220 #define S5P_FIMV_E_FRAME_CROP_OFFSET_V6 0xf780 221 #define S5P_FIMV_E_ENC_OPTIONS_V6 0xf784 222 #define S5P_FIMV_E_PICTURE_PROFILE_V6 0xf788 223 #define S5P_FIMV_E_FIXED_PICTURE_QP_V6 0xf790 224 225 #define S5P_FIMV_E_RC_CONFIG_V6 0xf794 226 #define S5P_FIMV_E_RC_QP_BOUND_V6 0xf798 227 #define S5P_FIMV_E_RC_RPARAM_V6 0xf79c 228 #define S5P_FIMV_E_MB_RC_CONFIG_V6 0xf7a0 229 #define S5P_FIMV_E_PADDING_CTRL_V6 0xf7a4 230 #define S5P_FIMV_E_MV_HOR_RANGE_V6 0xf7ac 231 #define S5P_FIMV_E_MV_VER_RANGE_V6 0xf7b0 232 #define S5P_FIMV_E_MV_RANGE_V6_MASK 0x3fff 233 234 #define S5P_FIMV_E_VBV_BUFFER_SIZE_V6 0xf84c 235 #define S5P_FIMV_E_VBV_INIT_DELAY_V6 0xf850 236 #define S5P_FIMV_E_NUM_DPB_V6 0xf890 237 #define S5P_FIMV_E_LUMA_DPB_V6 0xf8c0 238 #define S5P_FIMV_E_CHROMA_DPB_V6 0xf904 239 #define S5P_FIMV_E_ME_BUFFER_V6 0xf948 240 241 #define S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6 0xf98c 242 #define S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6 0xf990 243 #define S5P_FIMV_E_TMV_BUFFER0_V6 0xf994 244 #define S5P_FIMV_E_TMV_BUFFER1_V6 0xf998 245 #define S5P_FIMV_E_SOURCE_LUMA_ADDR_V6 0xf9f0 246 #define S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6 0xf9f4 247 #define S5P_FIMV_E_STREAM_BUFFER_ADDR_V6 0xf9f8 248 #define S5P_FIMV_E_STREAM_BUFFER_SIZE_V6 0xf9fc 249 #define S5P_FIMV_E_ROI_BUFFER_ADDR_V6 0xfA00 250 251 #define S5P_FIMV_E_PARAM_CHANGE_V6 0xfa04 252 #define S5P_FIMV_E_IR_SIZE_V6 0xfa08 253 #define S5P_FIMV_E_GOP_CONFIG_V6 0xfa0c 254 #define S5P_FIMV_E_MSLICE_MODE_V6 0xfa10 255 #define S5P_FIMV_E_MSLICE_SIZE_MB_V6 0xfa14 256 #define S5P_FIMV_E_MSLICE_SIZE_BITS_V6 0xfa18 257 #define S5P_FIMV_E_FRAME_INSERTION_V6 0xfa1c 258 259 #define S5P_FIMV_E_RC_FRAME_RATE_V6 0xfa20 260 #define S5P_FIMV_E_RC_BIT_RATE_V6 0xfa24 261 #define S5P_FIMV_E_RC_QP_OFFSET_V6 0xfa28 262 #define S5P_FIMV_E_RC_ROI_CTRL_V6 0xfa2c 263 #define S5P_FIMV_E_PICTURE_TAG_V6 0xfa30 264 #define S5P_FIMV_E_BIT_COUNT_ENABLE_V6 0xfa34 265 #define S5P_FIMV_E_MAX_BIT_COUNT_V6 0xfa38 266 #define S5P_FIMV_E_MIN_BIT_COUNT_V6 0xfa3c 267 268 #define S5P_FIMV_E_METADATA_BUFFER_ADDR_V6 0xfa40 269 #define S5P_FIMV_E_METADATA_BUFFER_SIZE_V6 0xfa44 270 #define S5P_FIMV_E_STREAM_SIZE_V6 0xfa80 271 #define S5P_FIMV_E_SLICE_TYPE_V6 0xfa84 272 #define S5P_FIMV_E_PICTURE_COUNT_V6 0xfa88 273 #define S5P_FIMV_E_RET_PICTURE_TAG_V6 0xfa8c 274 #define S5P_FIMV_E_STREAM_BUFFER_WRITE_POINTER_V6 0xfa90 275 276 #define S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6 0xfa94 277 #define S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6 0xfa98 278 #define S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6 0xfa9c 279 #define S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6 0xfaa0 280 #define S5P_FIMV_E_METADATA_ADDR_ENC_SLICE_V6 0xfaa4 281 #define S5P_FIMV_E_METADATA_SIZE_ENC_SLICE_V6 0xfaa8 282 283 #define S5P_FIMV_E_MPEG4_OPTIONS_V6 0xfb10 284 #define S5P_FIMV_E_MPEG4_HEC_PERIOD_V6 0xfb14 285 #define S5P_FIMV_E_ASPECT_RATIO_V6 0xfb50 286 #define S5P_FIMV_E_EXTENDED_SAR_V6 0xfb54 287 288 #define S5P_FIMV_E_H264_OPTIONS_V6 0xfb58 289 #define S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6 0xfb5c 290 #define S5P_FIMV_E_H264_LF_BETA_OFFSET_V6 0xfb60 291 #define S5P_FIMV_E_H264_I_PERIOD_V6 0xfb64 292 293 #define S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6 0xfb68 294 #define S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6 0xfb6c 295 #define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6 0xfb70 296 #define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6 0xfb74 297 #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 0xfb78 298 #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_1_V6 0xfb7c 299 #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_2_V6 0xfb80 300 #define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_3_V6 0xfb84 301 302 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 0xfb88 303 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_1_V6 0xfb8c 304 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_2_V6 0xfb90 305 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_3_V6 0xfb94 306 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_4_V6 0xfb98 307 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_5_V6 0xfb9c 308 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_6_V6 0xfba0 309 #define S5P_FIMV_E_H264_ASO_SLICE_ORDER_7_V6 0xfba4 310 311 #define S5P_FIMV_E_H264_CHROMA_QP_OFFSET_V6 0xfba8 312 #define S5P_FIMV_E_H264_NUM_T_LAYER_V6 0xfbac 313 314 #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 0xfbb0 315 #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER1_V6 0xfbb4 316 #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER2_V6 0xfbb8 317 #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER3_V6 0xfbbc 318 #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER4_V6 0xfbc0 319 #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER5_V6 0xfbc4 320 #define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER6_V6 0xfbc8 321 322 #define S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6 0xfc4c 323 #define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE_V6 0 324 #define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_TOP_BOTTOM_V6 1 325 #define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_TEMPORAL_V6 2 326 327 #define S5P_FIMV_E_MVC_FRAME_QP_VIEW1_V6 0xfd40 328 #define S5P_FIMV_E_MVC_RC_FRAME_RATE_VIEW1_V6 0xfd44 329 #define S5P_FIMV_E_MVC_RC_BIT_RATE_VIEW1_V6 0xfd48 330 #define S5P_FIMV_E_MVC_RC_QBOUND_VIEW1_V6 0xfd4c 331 #define S5P_FIMV_E_MVC_RC_RPARA_VIEW1_V6 0xfd50 332 #define S5P_FIMV_E_MVC_INTER_VIEW_PREDICTION_ON_V6 0xfd80 333 334 /* Codec numbers */ 335 #define S5P_FIMV_CODEC_NONE_V6 -1 336 337 338 #define S5P_FIMV_CODEC_H264_DEC_V6 0 339 #define S5P_FIMV_CODEC_H264_MVC_DEC_V6 1 340 341 #define S5P_FIMV_CODEC_MPEG4_DEC_V6 3 342 #define S5P_FIMV_CODEC_FIMV1_DEC_V6 4 343 #define S5P_FIMV_CODEC_FIMV2_DEC_V6 5 344 #define S5P_FIMV_CODEC_FIMV3_DEC_V6 6 345 #define S5P_FIMV_CODEC_FIMV4_DEC_V6 7 346 #define S5P_FIMV_CODEC_H263_DEC_V6 8 347 #define S5P_FIMV_CODEC_VC1RCV_DEC_V6 9 348 #define S5P_FIMV_CODEC_VC1_DEC_V6 10 349 /* FIXME: Add 11~12 */ 350 #define S5P_FIMV_CODEC_MPEG2_DEC_V6 13 351 #define S5P_FIMV_CODEC_VP8_DEC_V6 14 352 /* FIXME: Add 15~16 */ 353 #define S5P_FIMV_CODEC_H264_ENC_V6 20 354 #define S5P_FIMV_CODEC_H264_MVC_ENC_V6 21 355 356 #define S5P_FIMV_CODEC_MPEG4_ENC_V6 23 357 #define S5P_FIMV_CODEC_H263_ENC_V6 24 358 359 #define S5P_FIMV_NV12M_HALIGN_V6 16 360 #define S5P_FIMV_NV12MT_HALIGN_V6 16 361 #define S5P_FIMV_NV12MT_VALIGN_V6 16 362 363 #define S5P_FIMV_TMV_BUFFER_ALIGN_V6 16 364 #define S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6 256 365 #define S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6 256 366 #define S5P_FIMV_ME_BUFFER_ALIGN_V6 256 367 #define S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6 256 368 369 #define S5P_FIMV_LUMA_MB_TO_PIXEL_V6 256 370 #define S5P_FIMV_CHROMA_MB_TO_PIXEL_V6 128 371 #define S5P_FIMV_NUM_TMV_BUFFERS_V6 2 372 373 #define S5P_FIMV_MAX_FRAME_SIZE_V6 (2 * SZ_1M) 374 #define S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6 16 375 #define S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6 16 376 377 /* Buffer size requirements defined by hardware */ 378 #define S5P_FIMV_TMV_BUFFER_SIZE_V6(w, h) (((w) + 1) * ((h) + 3) * 8) 379 #define S5P_FIMV_ME_BUFFER_SIZE_V6(imw, imh, mbw, mbh) \ 380 (((((imw + 127) / 64) * 16) * DIV_ROUND_UP(imh, 64) * 256) + \ 381 (DIV_ROUND_UP((mbw) * (mbh), 32) * 16)) 382 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(w, h) (((w) * 192) + 64) 383 #define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(w, h) \ 384 ((w) * 144 + 8192 * (h) + 49216 + 1048576) 385 #define S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(w, h) \ 386 (2096 * ((w) + (h) + 1)) 387 #define S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(w, h) \ 388 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(w, h) 389 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(w, h) \ 390 ((w) * 32 + (h) * 128 + (((w) + 1) / 2) * 64 + 2112) 391 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(w, h) \ 392 (((w) * 64) + (((w) + 1) * 16) + (4096 * 16)) 393 #define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(w, h) \ 394 (((w) * 16) + (((w) + 1) * 16)) 395 396 /* MFC Context buffer sizes */ 397 #define MFC_CTX_BUF_SIZE_V6 (28 * SZ_1K) /* 28KB */ 398 #define MFC_H264_DEC_CTX_BUF_SIZE_V6 (2 * SZ_1M) /* 2MB */ 399 #define MFC_OTHER_DEC_CTX_BUF_SIZE_V6 (20 * SZ_1K) /* 20KB */ 400 #define MFC_H264_ENC_CTX_BUF_SIZE_V6 (100 * SZ_1K) /* 100KB */ 401 #define MFC_OTHER_ENC_CTX_BUF_SIZE_V6 (12 * SZ_1K) /* 12KB */ 402 403 /* MFCv6 variant defines */ 404 #define MAX_FW_SIZE_V6 (SZ_512K) /* 512KB */ 405 #define MAX_CPB_SIZE_V6 (3 * SZ_1M) /* 3MB */ 406 #define MFC_VERSION_V6 0x61 407 #define MFC_NUM_PORTS_V6 1 408 409 #endif /* _REGS_FIMV_V6_H */ 410