1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11 #ifndef __SOF_AMD_ACP_H
12 #define __SOF_AMD_ACP_H
13
14 #include <linux/dmi.h>
15 #include <linux/soundwire/sdw_amd.h>
16 #include "../sof-priv.h"
17 #include "../sof-audio.h"
18
19 #define ACP_MAX_STREAM 8
20
21 #define ACP_DSP_BAR 0
22
23 #define ACP_HW_SEM_RETRY_COUNT 10000
24 #define ACP_REG_POLL_INTERVAL 500
25 #define ACP_REG_POLL_TIMEOUT_US 2000
26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000
27
28 #define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01
29 #define ACP3X_PGFSM_STATUS_MASK 0x03
30 #define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07
31 #define ACP6X_PGFSM_STATUS_MASK 0x0F
32 #define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F
33 #define ACP70_PGFSM_STATUS_MASK 0xFF
34
35 #define ACP_POWERED_ON 0x00
36 #define ACP_ASSERT_RESET 0x01
37 #define ACP_RELEASE_RESET 0x00
38 #define ACP_SOFT_RESET_DONE_MASK 0x00010001
39 #define ACP_DSP_ASSERT_RESET 0x04
40 #define ACP_DSP_RELEASE_RESET 0x00
41 #define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004
42
43 #define ACP_DSP_INTR_EN_MASK 0x00000001
44 #define ACP3X_SRAM_PTE_OFFSET 0x02050000
45 #define ACP5X_SRAM_PTE_OFFSET 0x02050000
46 #define ACP6X_SRAM_PTE_OFFSET 0x03800000
47 #define ACP70_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET
48 #define PAGE_SIZE_4K_ENABLE 0x2
49 #define ACP_PAGE_SIZE 0x1000
50 #define ACP_DMA_CH_RUN 0x02
51 #define ACP_MAX_DESC_CNT 0x02
52 #define DSP_FW_RUN_ENABLE 0x01
53 #define ACP_SHA_RUN 0x01
54 #define ACP_SHA_RESET 0x02
55 #define ACP_SHA_HEADER 0x01
56 #define ACP_DMA_CH_RST 0x01
57 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10
58 #define ACP_ATU_CACHE_INVALID 0x01
59 #define ACP_MAX_DESC 128
60 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0
61
62 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000
63 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000
64 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000
65 #define ACP_IRAM_BASE_ADDRESS 0x000000
66 #define ACP_DRAM_BASE_ADDRESS 0x01000000
67 #define ACP_DRAM_PAGE_COUNT 128
68 #define ACP_SRAM_BASE_ADDRESS 0x3806000
69 #define ACP7X_SRAM_BASE_ADDRESS 0x380C000
70 #define ACP_DSP_TO_HOST_IRQ 0x04
71
72 #define ACP_RN_PCI_ID 0x01
73 #define ACP_VANGOGH_PCI_ID 0x50
74 #define ACP_RMB_PCI_ID 0x6F
75 #define ACP63_PCI_ID 0x63
76 #define ACP70_PCI_ID 0x70
77 #define ACP71_PCI_ID 0x71
78 #define ACP72_PCI_ID 0x72
79
80 #define HOST_BRIDGE_CZN 0x1630
81 #define HOST_BRIDGE_VGH 0x1645
82 #define HOST_BRIDGE_RMB 0x14B5
83 #define HOST_BRIDGE_ACP63 0x14E8
84 #define HOST_BRIDGE_ACP70 0x1507
85 #define ACP_SHA_STAT 0x8000
86 #define ACP_PSP_TIMEOUT_US 1000000
87 #define ACP_EXT_INTR_ERROR_STAT 0x20000000
88 #define MP0_C2PMSG_114_REG 0x3810AC8
89 #define MP0_C2PMSG_73_REG 0x3810A24
90 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000
91 #define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000
92 #define MBOX_DELAY_US 1000
93 #define MBOX_READY_MASK 0x80000000
94 #define MBOX_STATUS_MASK 0xFFFF
95 #define MBOX_ISREADY_FLAG 0x40000000
96 #define IRAM_DRAM_FENCE_0 0X0
97 #define IRAM_DRAM_FENCE_1 0X01
98 #define IRAM_DRAM_FENCE_2 0X02
99
100 #define BOX_SIZE_512 0x200
101 #define BOX_SIZE_1024 0x400
102
103 #define EXCEPT_MAX_HDR_SIZE 0x400
104 #define AMD_STACK_DUMP_SIZE 32
105
106 #define SRAM1_SIZE 0x280000
107 #define PROBE_STATUS_BIT BIT(31)
108
109 #define ACP_FIRMWARE_SIGNATURE 0x100
110 #define ACP_ERROR_IRQ_MASK BIT(29)
111 #define ACP_SDW0_IRQ_MASK BIT(21)
112 #define ACP_SDW1_IRQ_MASK BIT(2)
113 #define SDW_ACPI_ADDR_ACP63 5
114 #define SDW_ACPI_ADDR_ACP70 SDW_ACPI_ADDR_ACP63
115 #define ACP_DEFAULT_SRAM_LENGTH 0x00080000
116 #define ACP_SRAM_PAGE_COUNT 128
117 #define ACP6X_SDW_MAX_MANAGER_COUNT 2
118 #define ACP70_SDW_MAX_MANAGER_COUNT ACP6X_SDW_MAX_MANAGER_COUNT
119
120 enum clock_source {
121 ACP_CLOCK_96M = 0,
122 ACP_CLOCK_48M,
123 ACP_CLOCK_24M,
124 ACP_CLOCK_ACLK,
125 ACP_CLOCK_MCLK,
126 };
127
128 struct acp_atu_grp_pte {
129 u32 low;
130 u32 high;
131 };
132
133 union dma_tx_cnt {
134 struct {
135 unsigned int count : 19;
136 unsigned int reserved : 12;
137 unsigned ioc : 1;
138 } bitfields, bits;
139 unsigned int u32_all;
140 signed int i32_all;
141 };
142
143 struct dma_descriptor {
144 unsigned int src_addr;
145 unsigned int dest_addr;
146 union dma_tx_cnt tx_cnt;
147 unsigned int reserved;
148 };
149
150 /* Scratch memory structure for communication b/w host and dsp */
151 struct scratch_ipc_conf {
152 /* Debug memory */
153 u8 sof_debug_box[1024];
154 /* Exception memory*/
155 u8 sof_except_box[1024];
156 /* Stream buffer */
157 u8 sof_stream_box[1024];
158 /* Trace buffer */
159 u8 sof_trace_box[1024];
160 /* Host msg flag */
161 u32 sof_host_msg_write;
162 /* Host ack flag*/
163 u32 sof_host_ack_write;
164 /* DSP msg flag */
165 u32 sof_dsp_msg_write;
166 /* Dsp ack flag */
167 u32 sof_dsp_ack_write;
168 };
169
170 struct scratch_reg_conf {
171 struct scratch_ipc_conf info;
172 struct acp_atu_grp_pte grp1_pte[16];
173 struct acp_atu_grp_pte grp2_pte[16];
174 struct acp_atu_grp_pte grp3_pte[16];
175 struct acp_atu_grp_pte grp4_pte[16];
176 struct acp_atu_grp_pte grp5_pte[16];
177 struct acp_atu_grp_pte grp6_pte[16];
178 struct acp_atu_grp_pte grp7_pte[16];
179 struct acp_atu_grp_pte grp8_pte[16];
180 struct dma_descriptor dma_desc[64];
181 unsigned int reg_offset[8];
182 unsigned int buf_size[8];
183 u8 acp_tx_fifo_buf[256];
184 u8 acp_rx_fifo_buf[256];
185 unsigned int reserve[];
186 };
187
188 struct acp_dsp_stream {
189 struct list_head list;
190 struct snd_sof_dev *sdev;
191 struct snd_pcm_substream *substream;
192 struct snd_dma_buffer *dmab;
193 int num_pages;
194 int stream_tag;
195 int active;
196 unsigned int reg_offset;
197 size_t posn_offset;
198 struct snd_compr_stream *cstream;
199 u64 cstream_posn;
200 };
201
202 struct sof_amd_acp_desc {
203 const char *name;
204 u32 pgfsm_base;
205 u32 ext_intr_enb;
206 u32 ext_intr_cntl;
207 u32 ext_intr_stat;
208 u32 ext_intr_stat1;
209 u32 dsp_intr_base;
210 u32 sram_pte_offset;
211 u32 hw_semaphore_offset;
212 u32 acp_clkmux_sel;
213 u32 fusion_dsp_offset;
214 u32 probe_reg_offset;
215 u32 reg_start_addr;
216 u32 reg_end_addr;
217 u32 acp_error_stat;
218 u32 acp_sw0_i2s_err_reason;
219 u32 sdw_max_link_count;
220 u64 sdw_acpi_dev_addr;
221 };
222
223 struct acp_quirk_entry {
224 bool signed_fw_image;
225 bool skip_iram_dram_size_mod;
226 bool post_fw_run_delay;
227 };
228
229 /* Common device data struct for ACP devices */
230 struct acp_dev_data {
231 struct snd_sof_dev *dev;
232 const struct firmware *fw_dbin;
233 /* DMIC device */
234 struct platform_device *dmic_dev;
235 /* mutex lock to protect ACP common registers access */
236 struct mutex acp_lock;
237 /* ACPI information stored between scan and probe steps */
238 struct sdw_amd_acpi_info info;
239 /* sdw context allocated by SoundWire driver */
240 struct sdw_amd_ctx *sdw;
241 unsigned int fw_bin_size;
242 unsigned int fw_data_bin_size;
243 unsigned int fw_sram_data_bin_size;
244 const char *fw_code_bin;
245 const char *fw_data_bin;
246 const char *fw_sram_data_bin;
247 u32 fw_bin_page_count;
248 u32 fw_data_bin_page_count;
249 u32 addr;
250 u32 reg_range;
251 u32 blk_type;
252 dma_addr_t sha_dma_addr;
253 u8 *bin_buf;
254 dma_addr_t dma_addr;
255 u8 *data_buf;
256 dma_addr_t sram_dma_addr;
257 u8 *sram_data_buf;
258 struct acp_quirk_entry *quirks;
259 struct dma_descriptor dscr_info[ACP_MAX_DESC];
260 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
261 struct acp_dsp_stream *dtrace_stream;
262 struct acp_dsp_stream *probe_stream;
263 bool enable_fw_debug;
264 bool is_dram_in_use;
265 bool is_sram_in_use;
266 bool sdw_en_stat;
267 /* acp70_sdw0_wake_event flag set to true when wake irq asserted for SW0 instance */
268 bool acp70_sdw0_wake_event;
269 /* acp70_sdw1_wake_event flag set to true when wake irq asserted for SW1 instance */
270 bool acp70_sdw1_wake_event;
271 unsigned int pci_rev;
272 };
273
274 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
275 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
276
277 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
278 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
279 unsigned int dest_addr, int dsp_data_size);
280 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
281 unsigned int start_addr, unsigned int dest_addr,
282 unsigned int image_length);
283
284 /* ACP device probe/remove */
285 int amd_sof_acp_probe(struct snd_sof_dev *sdev);
286 void amd_sof_acp_remove(struct snd_sof_dev *sdev);
287
288 /* DSP Loader callbacks */
289 int acp_sof_dsp_run(struct snd_sof_dev *sdev);
290 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
291 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev);
292 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
293
294 /* Block IO callbacks */
295 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
296 u32 offset, void *src, size_t size);
297 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
298 u32 offset, void *dest, size_t size);
299
300 /* IPC callbacks */
301 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
302 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps,
303 void *p, size_t sz);
304 int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
305 struct snd_sof_pcm_stream *sps,
306 size_t posn_offset);
307 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
308 struct snd_sof_ipc_msg *msg);
309 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
310 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
311 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
312 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
313
314 /* ACP - DSP stream callbacks */
315 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
316 int acp_dsp_stream_init(struct snd_sof_dev *sdev);
317 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
318 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
319
320 /*
321 * DSP PCM Operations.
322 */
323 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
324 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
325 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
326 struct snd_pcm_hw_params *params,
327 struct snd_sof_platform_stream_params *platform_params);
328 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev,
329 struct snd_pcm_substream *substream);
330
331 extern const struct snd_sof_dsp_ops sof_acp_common_ops;
332
333 extern struct snd_sof_dsp_ops sof_renoir_ops;
334 int sof_renoir_ops_init(struct snd_sof_dev *sdev);
335 extern struct snd_sof_dsp_ops sof_vangogh_ops;
336 int sof_vangogh_ops_init(struct snd_sof_dev *sdev);
337 extern struct snd_sof_dsp_ops sof_rembrandt_ops;
338 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
339 extern struct snd_sof_dsp_ops sof_acp63_ops;
340 int sof_acp63_ops_init(struct snd_sof_dev *sdev);
341
342 extern struct snd_sof_dsp_ops sof_acp70_ops;
343 int sof_acp70_ops_init(struct snd_sof_dev *sdev);
344
345 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
346 /* Machine configuration */
347 int snd_amd_acp_find_config(struct pci_dev *pci);
348
349 /* Trace */
350 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
351 struct sof_ipc_dma_trace_params_ext *dtrace_params);
352 int acp_sof_trace_release(struct snd_sof_dev *sdev);
353
354 /* PM Callbacks */
355 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
356 int amd_sof_acp_resume(struct snd_sof_dev *sdev);
357
358 void amd_sof_ipc_dump(struct snd_sof_dev *sdev);
359 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags);
360
get_chip_info(struct snd_sof_pdata * pdata)361 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
362 {
363 const struct sof_dev_desc *desc = pdata->desc;
364
365 return desc->chip_info;
366 }
367
368 int acp_probes_register(struct snd_sof_dev *sdev);
369 void acp_probes_unregister(struct snd_sof_dev *sdev);
370
371 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[];
372 extern const struct dmi_system_id acp_sof_quirk_table[];
373 #endif
374