1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_usb_info; 19 struct rtw89_mac_gen_def; 20 struct rtw89_phy_gen_def; 21 struct rtw89_fw_blacklist; 22 struct rtw89_efuse_block_cfg; 23 struct rtw89_h2c_rf_tssi; 24 struct rtw89_fw_txpwr_track_cfg; 25 struct rtw89_phy_rfk_log_fmt; 26 struct rtw89_phy_calc_efuse_gain; 27 struct rtw89_debugfs; 28 struct rtw89_regd_data; 29 struct rtw89_wow_cam_info; 30 31 extern const struct ieee80211_ops rtw89_ops; 32 33 #define MASKBYTE0 0xff 34 #define MASKBYTE1 0xff00 35 #define MASKBYTE2 0xff0000 36 #define MASKBYTE3 0xff000000 37 #define MASKBYTE4 0xff00000000ULL 38 #define MASKHWORD 0xffff0000 39 #define MASKLWORD 0x0000ffff 40 #define MASKDWORD 0xffffffff 41 #define RFREG_MASK 0xfffff 42 #define INV_RF_DATA 0xffffffff 43 #define BYPASS_CR_DATA 0xbabecafe 44 #define RTW89_R32_EA 0xEAEAEAEA 45 #define RTW89_R32_DEAD 0xDEADBEEF 46 47 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 48 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100) 49 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 50 #define RTW89_PS_HANG_MAX_CNT 3 51 #define CFO_TRACK_MAX_USER 64 52 #define MAX_RSSI 110 53 #define RSSI_FACTOR 1 54 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 55 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 56 #define DELTA_SWINGIDX_SIZE 30 57 58 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 59 #define RTW89_RADIOTAP_ROOM_EHT \ 60 (sizeof(struct ieee80211_radiotap_tlv) + \ 61 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 62 sizeof(struct ieee80211_radiotap_tlv) + \ 63 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 64 #define RTW89_RADIOTAP_ROOM \ 65 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 66 67 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 68 #define RTW89_HTC_VARIANT_HE 3 69 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 70 #define RTW89_HTC_VARIANT_HE_CID_OM 1 71 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 72 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 73 74 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 75 enum htc_om_channel_width { 76 HTC_OM_CHANNEL_WIDTH_20 = 0, 77 HTC_OM_CHANNEL_WIDTH_40 = 1, 78 HTC_OM_CHANNEL_WIDTH_80 = 2, 79 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 80 }; 81 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 82 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 83 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 84 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 85 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 86 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 87 88 #define RTW89_TF_PAD GENMASK(11, 0) 89 #define RTW89_TF_BASIC_USER_INFO_SZ 6 90 91 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 92 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 93 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 94 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 95 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 96 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 97 98 enum rtw89_subband { 99 RTW89_CH_2G = 0, 100 RTW89_CH_5G_BAND_1 = 1, 101 /* RTW89_CH_5G_BAND_2 = 2, unused */ 102 RTW89_CH_5G_BAND_3 = 3, 103 RTW89_CH_5G_BAND_4 = 4, 104 105 RTW89_CH_6G_BAND_IDX0, /* Low */ 106 RTW89_CH_6G_BAND_IDX1, /* Low */ 107 RTW89_CH_6G_BAND_IDX2, /* Mid */ 108 RTW89_CH_6G_BAND_IDX3, /* Mid */ 109 RTW89_CH_6G_BAND_IDX4, /* High */ 110 RTW89_CH_6G_BAND_IDX5, /* High */ 111 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 112 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 113 114 RTW89_SUBBAND_NR, 115 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 116 }; 117 118 enum rtw89_tx_comp_band { 119 RTW89_TX_COMP_BAND_2GHZ, 120 RTW89_TX_COMP_BAND_5GHZ_L, 121 RTW89_TX_COMP_BAND_5GHZ_H, 122 RTW89_TX_COMP_BAND_6GHZ_M, 123 RTW89_TX_COMP_BAND_6GHZ_UH, 124 125 RTW89_TX_COMP_BAND_NR, 126 }; 127 128 enum rtw89_gain_offset { 129 RTW89_GAIN_OFFSET_2G_CCK, 130 RTW89_GAIN_OFFSET_2G_OFDM, 131 RTW89_GAIN_OFFSET_5G_LOW, 132 RTW89_GAIN_OFFSET_5G_MID, 133 RTW89_GAIN_OFFSET_5G_HIGH, 134 RTW89_GAIN_OFFSET_6G_L0, 135 RTW89_GAIN_OFFSET_6G_L1, 136 RTW89_GAIN_OFFSET_6G_M0, 137 RTW89_GAIN_OFFSET_6G_M1, 138 RTW89_GAIN_OFFSET_6G_H0, 139 RTW89_GAIN_OFFSET_6G_H1, 140 RTW89_GAIN_OFFSET_6G_UH0, 141 RTW89_GAIN_OFFSET_6G_UH1, 142 143 RTW89_GAIN_OFFSET_NR, 144 }; 145 146 enum rtw89_hci_type { 147 RTW89_HCI_TYPE_PCIE, 148 RTW89_HCI_TYPE_USB, 149 RTW89_HCI_TYPE_SDIO, 150 151 RTW89_HCI_TYPE_NUM, 152 }; 153 154 enum rtw89_hci_dle_type { 155 RTW89_HCI_DLE_TYPE_PCIE, 156 RTW89_HCI_DLE_TYPE_USB2, 157 RTW89_HCI_DLE_TYPE_USB3, 158 RTW89_HCI_DLE_TYPE_SDIO, 159 160 RTW89_HCI_DLE_TYPE_NUM, 161 }; 162 163 enum rtw89_core_chip_id { 164 RTL8852A, 165 RTL8852B, 166 RTL8852BT, 167 RTL8852C, 168 RTL8851B, 169 RTL8922A, 170 RTL8922D, 171 }; 172 173 enum rtw89_core_chip_cid { 174 RTL8922D_CID7025 = 0x74, 175 RTL8922D_CID7090 = 0x79, 176 }; 177 178 enum rtw89_core_chip_aid { 179 RTL8922D_AID1348 = 0x1348, 180 RTL8922D_AID7060 = 0x7060, 181 RTL8922D_AID7102 = 0x7102, 182 }; 183 184 enum rtw89_chip_gen { 185 RTW89_CHIP_AX, 186 RTW89_CHIP_BE, 187 188 RTW89_CHIP_GEN_NUM, 189 }; 190 191 enum rtw89_cv { 192 CHIP_CAV, 193 CHIP_CBV, 194 CHIP_CCV, 195 CHIP_CDV, 196 CHIP_CEV, 197 CHIP_CFV, 198 CHIP_CV_MAX, 199 CHIP_CV_INVALID = CHIP_CV_MAX, 200 }; 201 202 enum rtw89_bacam_ver { 203 RTW89_BACAM_V0, 204 RTW89_BACAM_V1, 205 206 RTW89_BACAM_V0_EXT = 99, 207 }; 208 209 enum rtw89_core_tx_type { 210 RTW89_CORE_TX_TYPE_DATA, 211 RTW89_CORE_TX_TYPE_MGMT, 212 RTW89_CORE_TX_TYPE_FWCMD, 213 }; 214 215 enum rtw89_core_rx_type { 216 RTW89_CORE_RX_TYPE_WIFI = 0, 217 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 218 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 219 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 220 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 221 RTW89_CORE_RX_TYPE_SS2FW = 5, 222 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 223 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 224 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 225 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 226 RTW89_CORE_RX_TYPE_C2H = 10, 227 RTW89_CORE_RX_TYPE_CSI = 11, 228 RTW89_CORE_RX_TYPE_CQI = 12, 229 RTW89_CORE_RX_TYPE_H2C = 13, 230 RTW89_CORE_RX_TYPE_FWDL = 14, 231 }; 232 233 enum rtw89_txq_flags { 234 RTW89_TXQ_F_AMPDU = 0, 235 RTW89_TXQ_F_BLOCK_BA = 1, 236 RTW89_TXQ_F_FORBID_BA = 2, 237 }; 238 239 enum rtw89_net_type { 240 RTW89_NET_TYPE_NO_LINK = 0, 241 RTW89_NET_TYPE_AD_HOC = 1, 242 RTW89_NET_TYPE_INFRA = 2, 243 RTW89_NET_TYPE_AP_MODE = 3, 244 }; 245 246 enum rtw89_wifi_role { 247 RTW89_WIFI_ROLE_NONE, 248 RTW89_WIFI_ROLE_STATION, 249 RTW89_WIFI_ROLE_AP, 250 RTW89_WIFI_ROLE_AP_VLAN, 251 RTW89_WIFI_ROLE_ADHOC, 252 RTW89_WIFI_ROLE_ADHOC_MASTER, 253 RTW89_WIFI_ROLE_MESH_POINT, 254 RTW89_WIFI_ROLE_MONITOR, 255 RTW89_WIFI_ROLE_P2P_DEVICE, 256 RTW89_WIFI_ROLE_P2P_CLIENT, 257 RTW89_WIFI_ROLE_P2P_GO, 258 RTW89_WIFI_ROLE_NAN, 259 RTW89_WIFI_ROLE_MLME_MAX 260 }; 261 262 enum rtw89_upd_mode { 263 RTW89_ROLE_CREATE, 264 RTW89_ROLE_REMOVE, 265 RTW89_ROLE_TYPE_CHANGE, 266 RTW89_ROLE_INFO_CHANGE, 267 RTW89_ROLE_CON_DISCONN, 268 RTW89_ROLE_BAND_SW, 269 RTW89_ROLE_FW_RESTORE, 270 }; 271 272 enum rtw89_self_role { 273 RTW89_SELF_ROLE_CLIENT, 274 RTW89_SELF_ROLE_AP, 275 RTW89_SELF_ROLE_AP_CLIENT 276 }; 277 278 enum rtw89_msk_sO_el { 279 RTW89_NO_MSK, 280 RTW89_SMA, 281 RTW89_TMA, 282 RTW89_BSSID 283 }; 284 285 enum rtw89_sch_tx_sel { 286 RTW89_SCH_TX_SEL_ALL, 287 RTW89_SCH_TX_SEL_HIQ, 288 RTW89_SCH_TX_SEL_MG0, 289 RTW89_SCH_TX_SEL_MACID, 290 }; 291 292 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 293 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 294 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 295 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 296 */ 297 enum rtw89_add_cam_sec_mode { 298 RTW89_ADDR_CAM_SEC_NONE = 0, 299 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 300 RTW89_ADDR_CAM_SEC_NORMAL = 2, 301 RTW89_ADDR_CAM_SEC_4GROUP = 3, 302 }; 303 304 enum rtw89_sec_key_type { 305 RTW89_SEC_KEY_TYPE_NONE = 0, 306 RTW89_SEC_KEY_TYPE_WEP40 = 1, 307 RTW89_SEC_KEY_TYPE_WEP104 = 2, 308 RTW89_SEC_KEY_TYPE_TKIP = 3, 309 RTW89_SEC_KEY_TYPE_WAPI = 4, 310 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 311 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 312 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 313 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 314 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 315 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 316 }; 317 318 enum rtw89_port { 319 RTW89_PORT_0 = 0, 320 RTW89_PORT_1 = 1, 321 RTW89_PORT_2 = 2, 322 RTW89_PORT_3 = 3, 323 RTW89_PORT_4 = 4, 324 RTW89_PORT_NUM 325 }; 326 327 enum rtw89_band { 328 RTW89_BAND_2G = 0, 329 RTW89_BAND_5G = 1, 330 RTW89_BAND_6G = 2, 331 RTW89_BAND_NUM, 332 }; 333 334 enum rtw89_hw_rate { 335 RTW89_HW_RATE_CCK1 = 0x0, 336 RTW89_HW_RATE_CCK2 = 0x1, 337 RTW89_HW_RATE_CCK5_5 = 0x2, 338 RTW89_HW_RATE_CCK11 = 0x3, 339 RTW89_HW_RATE_OFDM6 = 0x4, 340 RTW89_HW_RATE_OFDM9 = 0x5, 341 RTW89_HW_RATE_OFDM12 = 0x6, 342 RTW89_HW_RATE_OFDM18 = 0x7, 343 RTW89_HW_RATE_OFDM24 = 0x8, 344 RTW89_HW_RATE_OFDM36 = 0x9, 345 RTW89_HW_RATE_OFDM48 = 0xA, 346 RTW89_HW_RATE_OFDM54 = 0xB, 347 RTW89_HW_RATE_MCS0 = 0x80, 348 RTW89_HW_RATE_MCS1 = 0x81, 349 RTW89_HW_RATE_MCS2 = 0x82, 350 RTW89_HW_RATE_MCS3 = 0x83, 351 RTW89_HW_RATE_MCS4 = 0x84, 352 RTW89_HW_RATE_MCS5 = 0x85, 353 RTW89_HW_RATE_MCS6 = 0x86, 354 RTW89_HW_RATE_MCS7 = 0x87, 355 RTW89_HW_RATE_MCS8 = 0x88, 356 RTW89_HW_RATE_MCS9 = 0x89, 357 RTW89_HW_RATE_MCS10 = 0x8A, 358 RTW89_HW_RATE_MCS11 = 0x8B, 359 RTW89_HW_RATE_MCS12 = 0x8C, 360 RTW89_HW_RATE_MCS13 = 0x8D, 361 RTW89_HW_RATE_MCS14 = 0x8E, 362 RTW89_HW_RATE_MCS15 = 0x8F, 363 RTW89_HW_RATE_MCS16 = 0x90, 364 RTW89_HW_RATE_MCS17 = 0x91, 365 RTW89_HW_RATE_MCS18 = 0x92, 366 RTW89_HW_RATE_MCS19 = 0x93, 367 RTW89_HW_RATE_MCS20 = 0x94, 368 RTW89_HW_RATE_MCS21 = 0x95, 369 RTW89_HW_RATE_MCS22 = 0x96, 370 RTW89_HW_RATE_MCS23 = 0x97, 371 RTW89_HW_RATE_MCS24 = 0x98, 372 RTW89_HW_RATE_MCS25 = 0x99, 373 RTW89_HW_RATE_MCS26 = 0x9A, 374 RTW89_HW_RATE_MCS27 = 0x9B, 375 RTW89_HW_RATE_MCS28 = 0x9C, 376 RTW89_HW_RATE_MCS29 = 0x9D, 377 RTW89_HW_RATE_MCS30 = 0x9E, 378 RTW89_HW_RATE_MCS31 = 0x9F, 379 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 380 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 381 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 382 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 383 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 384 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 385 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 386 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 387 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 388 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 389 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 390 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 391 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 392 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 393 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 394 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 395 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 396 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 397 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 398 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 399 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 400 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 401 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 402 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 403 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 404 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 405 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 406 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 407 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 408 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 409 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 410 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 411 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 412 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 413 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 414 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 415 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 416 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 417 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 418 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 419 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 420 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 421 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 422 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 423 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 424 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 425 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 426 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 427 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 428 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 429 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 430 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 431 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 432 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 433 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 434 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 435 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 436 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 437 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 438 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 439 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 440 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 441 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 442 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 443 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 444 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 445 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 446 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 447 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 448 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 449 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 450 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 451 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 452 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 453 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 454 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 455 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 456 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 457 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 458 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 459 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 460 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 461 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 462 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 463 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 464 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 465 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 466 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 467 468 RTW89_HW_RATE_V1_MCS0 = 0x100, 469 RTW89_HW_RATE_V1_MCS1 = 0x101, 470 RTW89_HW_RATE_V1_MCS2 = 0x102, 471 RTW89_HW_RATE_V1_MCS3 = 0x103, 472 RTW89_HW_RATE_V1_MCS4 = 0x104, 473 RTW89_HW_RATE_V1_MCS5 = 0x105, 474 RTW89_HW_RATE_V1_MCS6 = 0x106, 475 RTW89_HW_RATE_V1_MCS7 = 0x107, 476 RTW89_HW_RATE_V1_MCS8 = 0x108, 477 RTW89_HW_RATE_V1_MCS9 = 0x109, 478 RTW89_HW_RATE_V1_MCS10 = 0x10A, 479 RTW89_HW_RATE_V1_MCS11 = 0x10B, 480 RTW89_HW_RATE_V1_MCS12 = 0x10C, 481 RTW89_HW_RATE_V1_MCS13 = 0x10D, 482 RTW89_HW_RATE_V1_MCS14 = 0x10E, 483 RTW89_HW_RATE_V1_MCS15 = 0x10F, 484 RTW89_HW_RATE_V1_MCS16 = 0x110, 485 RTW89_HW_RATE_V1_MCS17 = 0x111, 486 RTW89_HW_RATE_V1_MCS18 = 0x112, 487 RTW89_HW_RATE_V1_MCS19 = 0x113, 488 RTW89_HW_RATE_V1_MCS20 = 0x114, 489 RTW89_HW_RATE_V1_MCS21 = 0x115, 490 RTW89_HW_RATE_V1_MCS22 = 0x116, 491 RTW89_HW_RATE_V1_MCS23 = 0x117, 492 RTW89_HW_RATE_V1_MCS24 = 0x118, 493 RTW89_HW_RATE_V1_MCS25 = 0x119, 494 RTW89_HW_RATE_V1_MCS26 = 0x11A, 495 RTW89_HW_RATE_V1_MCS27 = 0x11B, 496 RTW89_HW_RATE_V1_MCS28 = 0x11C, 497 RTW89_HW_RATE_V1_MCS29 = 0x11D, 498 RTW89_HW_RATE_V1_MCS30 = 0x11E, 499 RTW89_HW_RATE_V1_MCS31 = 0x11F, 500 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 501 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 502 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 503 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 504 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 505 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 506 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 507 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 508 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 509 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 510 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 511 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 512 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 513 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 514 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 515 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 516 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 517 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 518 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 519 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 520 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 521 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 522 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 523 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 524 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 525 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 526 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 527 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 528 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 529 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 530 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 531 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 532 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 533 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 534 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 535 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 536 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 537 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 538 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 539 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 540 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 541 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 542 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 543 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 544 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 545 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 546 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 547 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 548 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 549 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 550 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 551 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 552 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 553 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 554 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 555 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 556 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 557 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 558 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 559 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 560 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 561 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 562 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 563 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 564 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 565 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 566 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 567 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 568 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 569 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 570 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 571 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 572 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 573 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 574 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 575 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 576 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 577 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 578 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 579 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 580 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 581 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 582 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 583 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 584 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 585 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 586 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 587 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 588 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 589 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 590 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 591 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 592 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 593 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 594 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 595 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 596 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 597 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 598 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 599 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 600 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 601 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 602 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 603 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 604 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 605 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 606 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 607 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 608 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 609 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 610 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 611 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 612 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 613 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 614 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 615 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 616 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 617 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 618 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 619 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 620 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 621 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 622 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 623 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 624 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 625 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 626 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 627 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 628 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 629 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 630 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 631 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 632 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 633 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 634 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 635 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 636 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 637 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 638 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 639 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 640 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 641 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 642 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 643 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 644 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 645 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 646 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 647 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 648 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 649 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 650 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 651 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 652 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 653 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 654 655 RTW89_HW_RATE_NR, 656 RTW89_HW_RATE_INVAL, 657 658 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 659 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 660 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 661 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 662 }; 663 664 /* 2G channels, 665 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 666 */ 667 #define RTW89_2G_CH_NUM 14 668 669 /* 5G channels, 670 * 36, 38, 40, 42, 44, 46, 48, 50, 671 * 52, 54, 56, 58, 60, 62, 64, 672 * 100, 102, 104, 106, 108, 110, 112, 114, 673 * 116, 118, 120, 122, 124, 126, 128, 130, 674 * 132, 134, 136, 138, 140, 142, 144, 675 * 149, 151, 153, 155, 157, 159, 161, 163, 676 * 165, 167, 169, 171, 173, 175, 177 677 */ 678 #define RTW89_5G_CH_NUM 53 679 680 /* 6G channels, 681 * 1, 3, 5, 7, 9, 11, 13, 15, 682 * 17, 19, 21, 23, 25, 27, 29, 33, 683 * 35, 37, 39, 41, 43, 45, 47, 49, 684 * 51, 53, 55, 57, 59, 61, 65, 67, 685 * 69, 71, 73, 75, 77, 79, 81, 83, 686 * 85, 87, 89, 91, 93, 97, 99, 101, 687 * 103, 105, 107, 109, 111, 113, 115, 117, 688 * 119, 121, 123, 125, 129, 131, 133, 135, 689 * 137, 139, 141, 143, 145, 147, 149, 151, 690 * 153, 155, 157, 161, 163, 165, 167, 169, 691 * 171, 173, 175, 177, 179, 181, 183, 185, 692 * 187, 189, 193, 195, 197, 199, 201, 203, 693 * 205, 207, 209, 211, 213, 215, 217, 219, 694 * 221, 225, 227, 229, 231, 233, 235, 237, 695 * 239, 241, 243, 245, 247, 249, 251, 253, 696 */ 697 #define RTW89_6G_CH_NUM 120 698 699 enum rtw89_rate_section { 700 RTW89_RS_CCK, 701 RTW89_RS_OFDM, 702 RTW89_RS_MCS, /* for HT/VHT/HE */ 703 RTW89_RS_HEDCM, 704 RTW89_RS_OFFSET, 705 RTW89_RS_NUM, 706 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 707 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 708 }; 709 710 enum rtw89_rate_offset_indexes { 711 RTW89_RATE_OFFSET_HE, 712 RTW89_RATE_OFFSET_VHT, 713 RTW89_RATE_OFFSET_HT, 714 RTW89_RATE_OFFSET_OFDM, 715 RTW89_RATE_OFFSET_CCK, 716 RTW89_RATE_OFFSET_DLRU_EHT, 717 RTW89_RATE_OFFSET_DLRU_HE, 718 RTW89_RATE_OFFSET_EHT, 719 __RTW89_RATE_OFFSET_NUM, 720 721 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 722 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 723 }; 724 725 enum rtw89_rate_num { 726 RTW89_RATE_CCK_NUM = 4, 727 RTW89_RATE_OFDM_NUM = 8, 728 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 729 730 RTW89_RATE_MCS_NUM_AX = 12, 731 RTW89_RATE_MCS_NUM_BE = 16, 732 __RTW89_RATE_MCS_NUM = 16, 733 }; 734 735 enum rtw89_nss { 736 RTW89_NSS_1 = 0, 737 RTW89_NSS_2 = 1, 738 /* HE DCM only support 1ss and 2ss */ 739 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 740 RTW89_NSS_3 = 2, 741 RTW89_NSS_4 = 3, 742 RTW89_NSS_NUM, 743 }; 744 745 enum rtw89_ntx { 746 RTW89_1TX = 0, 747 RTW89_2TX = 1, 748 RTW89_NTX_NUM, 749 }; 750 751 enum rtw89_beamforming_type { 752 RTW89_NONBF = 0, 753 RTW89_BF = 1, 754 RTW89_BF_NUM, 755 }; 756 757 enum rtw89_ofdma_type { 758 RTW89_NON_OFDMA = 0, 759 RTW89_OFDMA = 1, 760 RTW89_OFDMA_NUM, 761 }; 762 763 /* neither insert new in the middle, nor change any given definition */ 764 enum rtw89_regulation_type { 765 RTW89_WW = 0, 766 RTW89_ETSI = 1, 767 RTW89_FCC = 2, 768 RTW89_MKK = 3, 769 RTW89_NA = 4, 770 RTW89_IC = 5, 771 RTW89_KCC = 6, 772 RTW89_ACMA = 7, 773 RTW89_NCC = 8, 774 RTW89_MEXICO = 9, 775 RTW89_CHILE = 10, 776 RTW89_UKRAINE = 11, 777 RTW89_CN = 12, 778 RTW89_QATAR = 13, 779 RTW89_UK = 14, 780 RTW89_THAILAND = 15, 781 RTW89_REGD_NUM, 782 }; 783 784 enum rtw89_reg_6ghz_power { 785 RTW89_REG_6GHZ_POWER_VLP = 0, 786 RTW89_REG_6GHZ_POWER_LPI = 1, 787 RTW89_REG_6GHZ_POWER_STD = 2, 788 789 NUM_OF_RTW89_REG_6GHZ_POWER, 790 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 791 }; 792 793 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 794 795 /* calculate based on ieee80211 Transmit Power Envelope */ 796 struct rtw89_reg_6ghz_tpe { 797 bool valid; 798 s8 constraint; /* unit: dBm */ 799 }; 800 801 enum rtw89_fw_pkt_ofld_type { 802 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 803 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 804 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 805 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 806 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 807 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 808 RTW89_PKT_OFLD_TYPE_NDP = 6, 809 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 810 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 811 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 812 RTW89_PKT_OFLD_TYPE_NUM, 813 }; 814 815 struct rtw89_txpwr_byrate { 816 s8 cck[RTW89_RATE_CCK_NUM]; 817 s8 ofdm[RTW89_RATE_OFDM_NUM]; 818 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 819 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 820 s8 offset[__RTW89_RATE_OFFSET_NUM]; 821 s8 trap; 822 }; 823 824 struct rtw89_rate_desc { 825 enum rtw89_nss nss; 826 enum rtw89_rate_section rs; 827 enum rtw89_ofdma_type ofdma; 828 u8 idx; 829 }; 830 831 #define PHY_STS_HDR_LEN 8 832 #define RF_PATH_MAX 4 833 #define RTW89_MAX_PPDU_CNT 8 834 struct rtw89_rx_phy_ppdu { 835 void *buf; 836 u32 len; 837 u8 rssi_avg; 838 u8 rssi[RF_PATH_MAX]; 839 u8 mac_id; 840 u8 chan_idx; 841 u8 phy_idx; 842 u8 ie; 843 u16 rate; 844 u8 rpl_avg; 845 u8 rpl_path[RF_PATH_MAX]; 846 u8 rpl_fd[RF_PATH_MAX]; 847 u8 bw_idx; 848 u8 rx_path_en; 849 struct { 850 bool has; 851 u8 avg_snr; 852 u8 evm_max; 853 u8 evm_min; 854 } ofdm; 855 bool has_data; 856 bool has_bcn; 857 bool ldpc; 858 bool stbc; 859 bool to_self; 860 bool valid; 861 bool hdr_2_en; 862 }; 863 864 enum rtw89_mac_idx { 865 RTW89_MAC_0 = 0, 866 RTW89_MAC_1 = 1, 867 RTW89_MAC_NUM, 868 }; 869 870 enum rtw89_phy_idx { 871 RTW89_PHY_0 = 0, 872 RTW89_PHY_1 = 1, 873 RTW89_PHY_NUM, 874 }; 875 876 enum rtw89_fbtc_bt_index { 877 BTC_BT_1ST = 0x0, 878 BTC_BT_2ND = 0x1, 879 BTC_BT_EXT = 0x2, 880 BTC_ALL_BT = 0x2, 881 BTC_ALL_BT_EZL = 0x3 /* BT0+BT1+Ext-ZB(or Thread, or LTE) */ 882 }; 883 884 #define __RTW89_MLD_MAX_LINK_NUM 2 885 #define RTW89_MLD_NON_STA_LINK_NUM 1 886 887 enum rtw89_chanctx_idx { 888 RTW89_CHANCTX_0 = 0, 889 RTW89_CHANCTX_1 = 1, 890 891 NUM_OF_RTW89_CHANCTX, 892 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 893 }; 894 895 enum rtw89_rf_path { 896 RF_PATH_A = 0, 897 RF_PATH_B = 1, 898 RF_PATH_C = 2, 899 RF_PATH_D = 3, 900 RF_PATH_AB, 901 RF_PATH_AC, 902 RF_PATH_AD, 903 RF_PATH_BC, 904 RF_PATH_BD, 905 RF_PATH_CD, 906 RF_PATH_ABC, 907 RF_PATH_ABD, 908 RF_PATH_ACD, 909 RF_PATH_BCD, 910 RF_PATH_ABCD, 911 }; 912 913 enum rtw89_rf_path_bit { 914 RF_A = BIT(0), 915 RF_B = BIT(1), 916 RF_C = BIT(2), 917 RF_D = BIT(3), 918 919 RF_AB = (RF_A | RF_B), 920 RF_AC = (RF_A | RF_C), 921 RF_AD = (RF_A | RF_D), 922 RF_BC = (RF_B | RF_C), 923 RF_BD = (RF_B | RF_D), 924 RF_CD = (RF_C | RF_D), 925 926 RF_ABC = (RF_A | RF_B | RF_C), 927 RF_ABD = (RF_A | RF_B | RF_D), 928 RF_ACD = (RF_A | RF_C | RF_D), 929 RF_BCD = (RF_B | RF_C | RF_D), 930 931 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 932 }; 933 934 enum rtw89_bandwidth { 935 RTW89_CHANNEL_WIDTH_20 = 0, 936 RTW89_CHANNEL_WIDTH_40 = 1, 937 RTW89_CHANNEL_WIDTH_80 = 2, 938 RTW89_CHANNEL_WIDTH_160 = 3, 939 RTW89_CHANNEL_WIDTH_320 = 4, 940 941 /* keep index order above */ 942 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 943 944 RTW89_CHANNEL_WIDTH_80_80 = 5, 945 RTW89_CHANNEL_WIDTH_5 = 6, 946 RTW89_CHANNEL_WIDTH_10 = 7, 947 }; 948 949 enum rtw89_ps_mode { 950 RTW89_PS_MODE_NONE = 0, 951 RTW89_PS_MODE_RFOFF = 1, 952 RTW89_PS_MODE_CLK_GATED = 2, 953 RTW89_PS_MODE_PWR_GATED = 3, 954 }; 955 956 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 957 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 958 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 959 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 960 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 961 962 enum rtw89_pe_duration { 963 RTW89_PE_DURATION_0 = 0, 964 RTW89_PE_DURATION_8 = 1, 965 RTW89_PE_DURATION_16 = 2, 966 RTW89_PE_DURATION_16_20 = 3, 967 }; 968 969 enum rtw89_ru_bandwidth { 970 RTW89_RU26 = 0, 971 RTW89_RU52 = 1, 972 RTW89_RU106 = 2, 973 RTW89_RU52_26 = 3, 974 RTW89_RU106_26 = 4, 975 RTW89_RU_NUM, 976 }; 977 978 enum rtw89_sc_offset { 979 RTW89_SC_DONT_CARE = 0, 980 RTW89_SC_20_UPPER = 1, 981 RTW89_SC_20_LOWER = 2, 982 RTW89_SC_20_UPMOST = 3, 983 RTW89_SC_20_LOWEST = 4, 984 RTW89_SC_20_UP2X = 5, 985 RTW89_SC_20_LOW2X = 6, 986 RTW89_SC_20_UP3X = 7, 987 RTW89_SC_20_LOW3X = 8, 988 RTW89_SC_40_UPPER = 9, 989 RTW89_SC_40_LOWER = 10, 990 }; 991 992 /* only mgd features can be added to the enum */ 993 enum rtw89_wow_flags { 994 RTW89_WOW_FLAG_EN_MAGIC_PKT, 995 RTW89_WOW_FLAG_EN_REKEY_PKT, 996 RTW89_WOW_FLAG_EN_DISCONNECT, 997 RTW89_WOW_FLAG_EN_PATTERN, 998 RTW89_WOW_FLAG_NUM, 999 }; 1000 1001 struct rtw89_chan { 1002 u8 channel; 1003 u8 primary_channel; 1004 enum rtw89_band band_type; 1005 enum rtw89_bandwidth band_width; 1006 1007 /* The follow-up are derived from the above. We must ensure that it 1008 * is assigned correctly in rtw89_chan_create() if new one is added. 1009 */ 1010 u32 freq; 1011 enum rtw89_subband subband_type; 1012 enum rtw89_tx_comp_band tx_comp_band; 1013 enum rtw89_sc_offset pri_ch_idx; 1014 u8 pri_sb_idx; 1015 }; 1016 1017 struct rtw89_chan_rcd { 1018 u8 prev_primary_channel; 1019 enum rtw89_band prev_band_type; 1020 bool band_changed; 1021 }; 1022 1023 struct rtw89_channel_help_params { 1024 u32 tx_en; 1025 }; 1026 1027 struct rtw89_port_reg { 1028 u32 port_cfg; 1029 u32 tbtt_prohib; 1030 u32 bcn_area; 1031 u32 bcn_early; 1032 u32 tbtt_early; 1033 u32 tbtt_agg; 1034 u32 bcn_space; 1035 u32 bcn_forcetx; 1036 u32 bcn_err_cnt; 1037 u32 bcn_err_flag; 1038 u32 dtim_ctrl; 1039 u32 tbtt_shift; 1040 u32 bcn_cnt_tmr; 1041 u32 tsftr_l; 1042 u32 tsftr_h; 1043 u32 md_tsft; 1044 u32 bss_color; 1045 u32 mbssid; 1046 u32 mbssid_drop; 1047 u32 tsf_sync; 1048 u32 ptcl_dbg; 1049 u32 ptcl_dbg_info; 1050 u32 bcn_drop_all; 1051 u32 bcn_psr_rpt; 1052 u32 hiq_win[RTW89_PORT_NUM]; 1053 }; 1054 1055 struct rtw89_txwd_body { 1056 __le32 dword0; 1057 __le32 dword1; 1058 __le32 dword2; 1059 __le32 dword3; 1060 __le32 dword4; 1061 __le32 dword5; 1062 } __packed; 1063 1064 struct rtw89_txwd_body_v1 { 1065 __le32 dword0; 1066 __le32 dword1; 1067 __le32 dword2; 1068 __le32 dword3; 1069 __le32 dword4; 1070 __le32 dword5; 1071 __le32 dword6; 1072 __le32 dword7; 1073 } __packed; 1074 1075 struct rtw89_txwd_body_v2 { 1076 __le32 dword0; 1077 __le32 dword1; 1078 __le32 dword2; 1079 __le32 dword3; 1080 __le32 dword4; 1081 __le32 dword5; 1082 __le32 dword6; 1083 __le32 dword7; 1084 } __packed; 1085 1086 struct rtw89_txwd_info { 1087 __le32 dword0; 1088 __le32 dword1; 1089 __le32 dword2; 1090 __le32 dword3; 1091 __le32 dword4; 1092 __le32 dword5; 1093 } __packed; 1094 1095 struct rtw89_txwd_info_v2 { 1096 __le32 dword0; 1097 __le32 dword1; 1098 __le32 dword2; 1099 __le32 dword3; 1100 __le32 dword4; 1101 __le32 dword5; 1102 __le32 dword6; 1103 __le32 dword7; 1104 } __packed; 1105 1106 struct rtw89_rx_desc_info { 1107 u16 pkt_size; 1108 u8 pkt_type; 1109 u8 drv_info_size; 1110 u8 phy_rpt_size; 1111 u8 hdr_cnv_size; 1112 u8 shift; 1113 u8 wl_hd_iv_len; 1114 bool long_rxdesc; 1115 bool bb_sel; 1116 bool mac_info_valid; 1117 u16 data_rate; 1118 u8 gi_ltf; 1119 u8 bw; 1120 u32 free_run_cnt; 1121 u8 user_id; 1122 bool sr_en; 1123 u8 ppdu_cnt; 1124 u8 ppdu_type; 1125 bool icv_err; 1126 bool crc32_err; 1127 bool hw_dec; 1128 bool sw_dec; 1129 bool addr1_match; 1130 u8 frag; 1131 u16 seq; 1132 u8 frame_type; 1133 u8 rx_pl_id; 1134 bool addr_cam_valid; 1135 u8 addr_cam_id; 1136 u8 sec_cam_id; 1137 u8 sec_type; 1138 u8 mac_id; 1139 u16 offset; 1140 u16 rxd_len; 1141 bool ready; 1142 u16 rssi; 1143 }; 1144 1145 struct rtw89_rxdesc_short { 1146 __le32 dword0; 1147 __le32 dword1; 1148 __le32 dword2; 1149 __le32 dword3; 1150 } __packed; 1151 1152 struct rtw89_rxdesc_short_v2 { 1153 __le32 dword0; 1154 __le32 dword1; 1155 __le32 dword2; 1156 __le32 dword3; 1157 __le32 dword4; 1158 __le32 dword5; 1159 } __packed; 1160 1161 struct rtw89_rxdesc_short_v3 { 1162 __le32 dword0; 1163 __le32 dword1; 1164 __le32 dword2; 1165 __le32 dword3; 1166 __le32 dword4; 1167 __le32 dword5; 1168 } __packed; 1169 1170 struct rtw89_rxdesc_long { 1171 __le32 dword0; 1172 __le32 dword1; 1173 __le32 dword2; 1174 __le32 dword3; 1175 __le32 dword4; 1176 __le32 dword5; 1177 __le32 dword6; 1178 __le32 dword7; 1179 } __packed; 1180 1181 struct rtw89_rxdesc_long_v2 { 1182 __le32 dword0; 1183 __le32 dword1; 1184 __le32 dword2; 1185 __le32 dword3; 1186 __le32 dword4; 1187 __le32 dword5; 1188 __le32 dword6; 1189 __le32 dword7; 1190 __le32 dword8; 1191 __le32 dword9; 1192 } __packed; 1193 1194 struct rtw89_rxdesc_long_v3 { 1195 __le32 dword0; 1196 __le32 dword1; 1197 __le32 dword2; 1198 __le32 dword3; 1199 __le32 dword4; 1200 __le32 dword5; 1201 __le32 dword6; 1202 __le32 dword7; 1203 __le32 dword8; 1204 __le32 dword9; 1205 } __packed; 1206 1207 struct rtw89_rxdesc_phy_rpt_v2 { 1208 __le32 dword0; 1209 __le32 dword1; 1210 } __packed; 1211 1212 struct rtw89_tx_desc_info { 1213 u16 pkt_size; 1214 u8 wp_offset; 1215 u8 mac_id; 1216 u8 qsel; 1217 u8 ch_dma; 1218 u8 hdr_llc_len; 1219 bool is_bmc; 1220 bool en_wd_info; 1221 bool wd_page; 1222 bool use_rate; 1223 bool dis_data_fb; 1224 bool tid_indicate; 1225 bool agg_en; 1226 bool bk; 1227 u8 ampdu_density; 1228 u8 ampdu_num; 1229 bool sec_en; 1230 bool report; 1231 bool tx_cnt_lmt_en; 1232 u8 sn: 4; 1233 u8 tx_cnt_lmt: 6; 1234 u8 addr_info_nr; 1235 u8 sec_keyid; 1236 u8 sec_type; 1237 u8 sec_cam_idx; 1238 u8 sec_seq[6]; 1239 u16 data_rate; 1240 u16 data_retry_lowest_rate; 1241 u8 data_bw; 1242 u8 gi_ltf; 1243 bool fw_dl; 1244 u16 seq; 1245 bool a_ctrl_bsr; 1246 u8 hw_ssn_sel; 1247 #define RTW89_MGMT_HW_SSN_SEL 1 1248 u8 hw_seq_mode; 1249 #define RTW89_MGMT_HW_SEQ_MODE 1 1250 bool hiq; 1251 u8 port; 1252 bool er_cap; 1253 bool stbc; 1254 bool ldpc; 1255 bool upd_wlan_hdr; 1256 bool mlo; 1257 bool sw_mld; 1258 }; 1259 1260 struct rtw89_core_tx_request { 1261 enum rtw89_core_tx_type tx_type; 1262 1263 struct sk_buff *skb; 1264 struct ieee80211_vif *vif; 1265 struct ieee80211_sta *sta; 1266 struct rtw89_vif_link *rtwvif_link; 1267 struct rtw89_sta_link *rtwsta_link; 1268 struct rtw89_tx_desc_info desc_info; 1269 1270 bool with_wait; 1271 }; 1272 1273 struct rtw89_txq { 1274 struct list_head list; 1275 unsigned long flags; 1276 int wait_cnt; 1277 }; 1278 1279 struct rtw89_mac_ax_gnt { 1280 u8 gnt_bt_sw_en; 1281 u8 gnt_bt; 1282 u8 gnt_wl_sw_en; 1283 u8 gnt_wl; 1284 } __packed; 1285 1286 struct rtw89_mac_ax_wl_act { 1287 u8 wlan_act_en; 1288 u8 wlan_act; 1289 } __packed; 1290 1291 #define RTW89_MAC_AX_COEX_GNT_NR 2 1292 struct rtw89_mac_ax_coex_gnt { 1293 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1294 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1295 }; 1296 1297 enum rtw89_btc_ncnt { 1298 BTC_NCNT_POWER_ON = 0x0, 1299 BTC_NCNT_POWER_OFF, 1300 BTC_NCNT_INIT_COEX, 1301 BTC_NCNT_SCAN_START, 1302 BTC_NCNT_SCAN_FINISH, 1303 BTC_NCNT_SPECIAL_PACKET, 1304 BTC_NCNT_SWITCH_BAND, 1305 BTC_NCNT_RFK_TIMEOUT, 1306 BTC_NCNT_SHOW_COEX_INFO, 1307 BTC_NCNT_ROLE_INFO, 1308 BTC_NCNT_CONTROL, 1309 BTC_NCNT_RADIO_STATE, 1310 BTC_NCNT_CUSTOMERIZE, 1311 BTC_NCNT_WL_RFK, 1312 BTC_NCNT_WL_STA, 1313 BTC_NCNT_WL_STA_LAST, 1314 BTC_NCNT_FWINFO, 1315 BTC_NCNT_TIMER, 1316 BTC_NCNT_SWITCH_CHBW, 1317 BTC_NCNT_RESUME_DL_FW, 1318 BTC_NCNT_COUNTRYCODE, 1319 BTC_NCNT_NUM, 1320 }; 1321 1322 enum rtw89_btc_btinfo { 1323 BTC_BTINFO_L0 = 0, 1324 BTC_BTINFO_L1, 1325 BTC_BTINFO_L2, 1326 BTC_BTINFO_L3, 1327 BTC_BTINFO_H0, 1328 BTC_BTINFO_H1, 1329 BTC_BTINFO_H2, 1330 BTC_BTINFO_H3, 1331 BTC_BTINFO_MAX 1332 }; 1333 1334 enum rtw89_btc_dcnt { 1335 BTC_DCNT_RUN = 0x0, 1336 BTC_DCNT_CX_RUNINFO, 1337 BTC_DCNT_RPT, 1338 BTC_DCNT_RPT_HANG, 1339 BTC_DCNT_CYCLE, 1340 BTC_DCNT_CYCLE_HANG, 1341 BTC_DCNT_W1, 1342 BTC_DCNT_W1_HANG, 1343 BTC_DCNT_B1, 1344 BTC_DCNT_B1_HANG, 1345 BTC_DCNT_TDMA_NONSYNC, 1346 BTC_DCNT_SLOT_NONSYNC, 1347 BTC_DCNT_BTCNT_HANG, 1348 BTC_DCNT_BTTX_HANG, 1349 BTC_DCNT_WL_SLOT_DRIFT, 1350 BTC_DCNT_WL_STA_LAST, 1351 BTC_DCNT_BT_SLOT_DRIFT, 1352 BTC_DCNT_BT_SLOT_FLOOD, 1353 BTC_DCNT_FDDT_TRIG, 1354 BTC_DCNT_E2G, 1355 BTC_DCNT_E2G_HANG, 1356 BTC_DCNT_WL_FW_VER_MATCH, 1357 BTC_DCNT_NULL_TX_FAIL, 1358 BTC_DCNT_WL_STA_NTFY, 1359 BTC_DCNT_NUM, 1360 }; 1361 1362 enum rtw89_btc_wl_state_cnt { 1363 BTC_WCNT_SCANAP = 0x0, 1364 BTC_WCNT_DHCP, 1365 BTC_WCNT_EAPOL, 1366 BTC_WCNT_ARP, 1367 BTC_WCNT_SCBDUPDATE, 1368 BTC_WCNT_RFK_REQ, 1369 BTC_WCNT_RFK_GO, 1370 BTC_WCNT_RFK_REJECT, 1371 BTC_WCNT_RFK_TIMEOUT, 1372 BTC_WCNT_CH_UPDATE, 1373 BTC_WCNT_DBCC_ALL_2G, 1374 BTC_WCNT_DBCC_CHG, 1375 BTC_WCNT_RX_OK_LAST, 1376 BTC_WCNT_RX_OK_LAST2S, 1377 BTC_WCNT_RX_ERR_LAST, 1378 BTC_WCNT_RX_ERR_LAST2S, 1379 BTC_WCNT_RX_LAST, 1380 BTC_WCNT_NUM 1381 }; 1382 1383 enum rtw89_btc_bt_state_cnt { 1384 BTC_BCNT_RETRY = 0x0, 1385 BTC_BCNT_REINIT, 1386 BTC_BCNT_REENABLE, 1387 BTC_BCNT_SCBDREAD, 1388 BTC_BCNT_RELINK, 1389 BTC_BCNT_IGNOWL, 1390 BTC_BCNT_INQPAG, 1391 BTC_BCNT_INQ, 1392 BTC_BCNT_PAGE, 1393 BTC_BCNT_ROLESW, 1394 BTC_BCNT_AFH, 1395 BTC_BCNT_INFOUPDATE, 1396 BTC_BCNT_INFOSAME, 1397 BTC_BCNT_SCBDUPDATE, 1398 BTC_BCNT_HIPRI_TX, 1399 BTC_BCNT_HIPRI_RX, 1400 BTC_BCNT_LOPRI_TX, 1401 BTC_BCNT_LOPRI_RX, 1402 BTC_BCNT_POLUT, 1403 BTC_BCNT_POLUT_NOW, 1404 BTC_BCNT_POLUT_DIFF, 1405 BTC_BCNT_RATECHG, 1406 BTC_BCNT_BTTXPWR_UPDATE, 1407 BTC_BCNT_NUM, 1408 }; 1409 1410 enum rtw89_btc_bt_profile { 1411 BTC_BT_NOPROFILE = 0, 1412 BTC_BT_HFP = BIT(0), 1413 BTC_BT_HID = BIT(1), 1414 BTC_BT_A2DP = BIT(2), 1415 BTC_BT_PAN = BIT(3), 1416 BTC_PROFILE_MAX = 4, 1417 }; 1418 1419 struct rtw89_btc_ant_info { 1420 u8 type; /* shared, dedicated */ 1421 u8 num; 1422 u8 isolation; 1423 1424 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1425 u8 diversity: 1; 1426 u8 btg_pos: 2; 1427 u8 stream_cnt: 4; 1428 }; 1429 1430 struct rtw89_btc_ant_info_v7 { 1431 u8 type; /* shared, dedicated(non-shared) */ 1432 u8 num; /* antenna count */ 1433 u8 isolation; 1434 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1435 1436 u8 diversity; /* only for wifi use 1-antenna */ 1437 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1438 u8 stream_cnt; /* spatial_stream count */ 1439 u8 rsvd; 1440 } __packed; 1441 1442 enum rtw89_tfc_dir { 1443 RTW89_TFC_UL, 1444 RTW89_TFC_DL, 1445 }; 1446 1447 struct rtw89_btc_wl_smap { 1448 u32 busy: 1; 1449 u32 scan: 1; 1450 u32 connecting: 1; 1451 u32 roaming: 1; 1452 u32 dbccing: 1; 1453 u32 _4way: 1; 1454 u32 rf_off: 1; 1455 u32 lps: 2; 1456 u32 ips: 1; 1457 u32 init_ok: 1; 1458 u32 traffic_dir : 2; 1459 u32 rf_off_pre: 1; 1460 u32 lps_pre: 2; 1461 u32 lps_exiting: 1; 1462 u32 emlsr: 1; 1463 }; 1464 1465 enum rtw89_tfc_interval { 1466 RTW89_TFC_INTERVAL_100MS, 1467 RTW89_TFC_INTERVAL_2SEC, 1468 }; 1469 1470 enum rtw89_tfc_lv { 1471 RTW89_TFC_IDLE, 1472 RTW89_TFC_ULTRA_LOW, 1473 RTW89_TFC_LOW, 1474 RTW89_TFC_MID, 1475 RTW89_TFC_HIGH, 1476 }; 1477 1478 DECLARE_EWMA(tp, 10, 2); 1479 1480 struct rtw89_traffic_stats { 1481 /* units in bytes */ 1482 u64 tx_unicast; 1483 u64 rx_unicast; 1484 u32 tx_avg_len; 1485 u32 rx_avg_len; 1486 1487 /* count for packets */ 1488 u64 tx_cnt; 1489 u64 rx_cnt; 1490 1491 /* units in Mbps */ 1492 u32 tx_throughput; 1493 u32 rx_throughput; 1494 u32 tx_throughput_raw; 1495 u32 rx_throughput_raw; 1496 1497 u32 rx_tf_acc; 1498 u32 rx_tf_periodic; 1499 1500 enum rtw89_tfc_lv tx_tfc_lv; 1501 enum rtw89_tfc_lv rx_tfc_lv; 1502 struct ewma_tp tx_ewma_tp; 1503 struct ewma_tp rx_ewma_tp; 1504 1505 u16 tx_rate; 1506 u16 rx_rate; 1507 }; 1508 1509 struct rtw89_btc_chdef { 1510 u8 center_ch; 1511 u8 band; 1512 u8 chan; 1513 enum rtw89_sc_offset offset; 1514 enum rtw89_bandwidth bw; 1515 }; 1516 1517 struct rtw89_btc_statistic { 1518 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1519 struct rtw89_traffic_stats traffic; 1520 }; 1521 1522 #define BTC_WL_RSSI_THMAX 4 1523 1524 struct rtw89_btc_wl_link_info { 1525 struct rtw89_btc_chdef chdef; 1526 struct rtw89_btc_statistic stat; 1527 enum rtw89_tfc_dir dir; 1528 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1529 u8 mac_addr[ETH_ALEN]; 1530 u8 busy; 1531 u8 ch; 1532 u8 bw; 1533 u8 band; 1534 u8 role; 1535 u8 pid; 1536 u8 phy; 1537 u8 dtim_period; 1538 u8 mode; 1539 u8 tx_1ss_limit; 1540 1541 u8 mac_id; 1542 u8 tx_retry; 1543 1544 u32 bcn_period; 1545 u32 busy_t; 1546 u32 tx_time; 1547 u32 client_cnt; 1548 u32 rx_rate_drop_cnt; 1549 u32 noa_duration; 1550 1551 u32 active: 1; 1552 u32 noa: 1; 1553 u32 client_ps: 1; 1554 u32 connected: 2; 1555 }; 1556 1557 union rtw89_btc_wl_state_map { 1558 u32 val; 1559 struct rtw89_btc_wl_smap map; 1560 }; 1561 1562 struct rtw89_btc_bt_hfp_desc { 1563 u32 exist: 1; 1564 u32 type: 2; 1565 u32 rsvd: 29; 1566 }; 1567 1568 struct rtw89_btc_bt_hid_desc { 1569 u32 exist: 1; 1570 u32 slot_info: 2; 1571 u32 pair_cnt: 2; 1572 u32 type: 8; 1573 u32 rsvd: 19; 1574 }; 1575 1576 struct rtw89_btc_bt_a2dp_desc { 1577 u8 exist: 1; 1578 u8 exist_last: 1; 1579 u8 play_latency: 1; 1580 u8 type: 3; 1581 u8 active: 1; 1582 u8 sink: 1; 1583 u32 handle_update: 1; 1584 u32 devinfo_query: 1; 1585 u32 no_empty_streak_2s: 8; 1586 u32 no_empty_streak_max: 8; 1587 u32 rsvd: 6; 1588 1589 u8 bitpool; 1590 u16 vendor_id; 1591 u32 device_name; 1592 u32 flush_time; 1593 }; 1594 1595 struct rtw89_btc_bt_pan_desc { 1596 u32 exist: 1; 1597 u32 type: 1; 1598 u32 active: 1; 1599 u32 rsvd: 29; 1600 }; 1601 1602 struct rtw89_btc_bt_rfk_info { 1603 u32 run: 1; 1604 u32 req: 1; 1605 u32 timeout: 1; 1606 u32 rsvd: 29; 1607 }; 1608 1609 union rtw89_btc_bt_rfk_info_map { 1610 u32 val; 1611 struct rtw89_btc_bt_rfk_info map; 1612 }; 1613 1614 struct rtw89_btc_bt_ver_info { 1615 u32 fw_coex; /* match with which coex_ver */ 1616 u32 fw; 1617 }; 1618 1619 struct rtw89_btc_bool_sta_chg { 1620 u32 now: 1; 1621 u32 last: 1; 1622 u32 remain: 1; 1623 u32 srvd: 29; 1624 }; 1625 1626 struct rtw89_btc_u8_sta_chg { 1627 u8 now; 1628 u8 last; 1629 u8 remain; 1630 u8 rsvd; 1631 }; 1632 1633 struct rtw89_btc_wl_scan_info { 1634 u8 band[RTW89_PHY_NUM]; 1635 u8 phy_map; 1636 u8 rsvd; 1637 }; 1638 1639 struct rtw89_btc_wl_dbcc_info { 1640 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1641 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1642 u8 real_band[RTW89_PHY_NUM]; 1643 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1644 }; 1645 1646 struct rtw89_btc_wl_mlo_info { 1647 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1648 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1649 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1650 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1651 1652 u8 wtype; /* enum phl_mr_wtype */ 1653 u8 mrcx_mode; 1654 u8 mrcx_act_hwb_map; 1655 u8 mrcx_bt_slot_rsp; 1656 1657 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1658 u8 mlo_en; /* MLO enable */ 1659 u8 mlo_adie; /* a-die count */ 1660 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1661 1662 u32 link_status; /* enum mlo_dbcc_mode_type */ 1663 }; 1664 1665 struct rtw89_btc_wl_active_role { 1666 u8 connected: 1; 1667 u8 pid: 3; 1668 u8 phy: 1; 1669 u8 noa: 1; 1670 u8 band: 2; 1671 1672 u8 client_ps: 1; 1673 u8 bw: 7; 1674 1675 u8 role; 1676 u8 ch; 1677 1678 u16 tx_lvl; 1679 u16 rx_lvl; 1680 u16 tx_rate; 1681 u16 rx_rate; 1682 }; 1683 1684 struct rtw89_btc_wl_active_role_v1 { 1685 u8 connected: 1; 1686 u8 pid: 3; 1687 u8 phy: 1; 1688 u8 noa: 1; 1689 u8 band: 2; 1690 1691 u8 client_ps: 1; 1692 u8 bw: 7; 1693 1694 u8 role; 1695 u8 ch; 1696 1697 u16 tx_lvl; 1698 u16 rx_lvl; 1699 u16 tx_rate; 1700 u16 rx_rate; 1701 1702 u32 noa_duration; /* ms */ 1703 }; 1704 1705 struct rtw89_btc_wl_active_role_v2 { 1706 u8 connected: 1; 1707 u8 pid: 3; 1708 u8 phy: 1; 1709 u8 noa: 1; 1710 u8 band: 2; 1711 1712 u8 client_ps: 1; 1713 u8 bw: 7; 1714 1715 u8 role; 1716 u8 ch; 1717 1718 u32 noa_duration; /* ms */ 1719 }; 1720 1721 struct rtw89_btc_wl_active_role_v7 { 1722 u8 connected; 1723 u8 pid; 1724 u8 phy; 1725 u8 noa; 1726 1727 u8 band; 1728 u8 client_ps; 1729 u8 bw; 1730 u8 role; 1731 1732 u8 ch; 1733 u8 noa_dur; 1734 u8 client_cnt; 1735 u8 rsvd2; 1736 } __packed; 1737 1738 struct rtw89_btc_wl_role_info_bpos { 1739 u16 none: 1; 1740 u16 station: 1; 1741 u16 ap: 1; 1742 u16 vap: 1; 1743 u16 adhoc: 1; 1744 u16 adhoc_master: 1; 1745 u16 mesh: 1; 1746 u16 moniter: 1; 1747 u16 p2p_device: 1; 1748 u16 p2p_gc: 1; 1749 u16 p2p_go: 1; 1750 u16 nan: 1; 1751 }; 1752 1753 struct rtw89_btc_wl_scc_ctrl { 1754 u8 null_role1; 1755 u8 null_role2; 1756 u8 ebt_null; /* if tx null at EBT slot */ 1757 }; 1758 1759 union rtw89_btc_wl_role_info_map { 1760 u16 val; 1761 struct rtw89_btc_wl_role_info_bpos role; 1762 }; 1763 1764 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1765 u8 connect_cnt; 1766 u8 link_mode; 1767 union rtw89_btc_wl_role_info_map role_map; 1768 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1769 }; 1770 1771 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1772 u8 connect_cnt; 1773 u8 link_mode; 1774 union rtw89_btc_wl_role_info_map role_map; 1775 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1776 u32 mrole_type; /* btc_wl_mrole_type */ 1777 u32 mrole_noa_duration; /* ms */ 1778 1779 u32 dbcc_en: 1; 1780 u32 dbcc_chg: 1; 1781 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1782 u32 link_mode_chg: 1; 1783 u32 rsvd: 27; 1784 }; 1785 1786 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1787 u8 connect_cnt; 1788 u8 link_mode; 1789 union rtw89_btc_wl_role_info_map role_map; 1790 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1791 u32 mrole_type; /* btc_wl_mrole_type */ 1792 u32 mrole_noa_duration; /* ms */ 1793 1794 u32 dbcc_en: 1; 1795 u32 dbcc_chg: 1; 1796 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1797 u32 link_mode_chg: 1; 1798 u32 rsvd: 27; 1799 }; 1800 1801 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1802 u8 connected; 1803 u8 pid; 1804 u8 phy; 1805 u8 noa; 1806 1807 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1808 u8 active; /* 0:rlink is under doze */ 1809 u8 bw; /* enum channel_width */ 1810 u8 role; /*enum role_type */ 1811 1812 u8 ch; 1813 u8 noa_dur; /* ms */ 1814 u8 client_cnt; /* for Role = P2P-Go/AP */ 1815 u8 mode; /* wifi protocol */ 1816 } __packed; 1817 1818 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1819 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1820 u8 connect_cnt; 1821 u8 link_mode; 1822 u8 link_mode_chg; 1823 u8 p2p_2g; 1824 1825 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1826 1827 u32 role_map; 1828 u32 mrole_type; /* btc_wl_mrole_type */ 1829 u32 mrole_noa_duration; /* ms */ 1830 u32 dbcc_en; 1831 u32 dbcc_chg; 1832 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1833 } __packed; 1834 1835 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1836 u8 connect_cnt; 1837 u8 link_mode; 1838 u8 link_mode_chg; 1839 u8 p2p_2g; 1840 1841 u8 pta_req_band; 1842 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1843 u8 dbcc_chg; 1844 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1845 1846 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1847 1848 u32 role_map; 1849 u32 mrole_type; /* btc_wl_mrole_type */ 1850 u32 mrole_noa_duration; /* ms */ 1851 } __packed; 1852 1853 struct rtw89_btc_wl_ver_info { 1854 u32 fw_coex; /* match with which coex_ver */ 1855 u32 fw; 1856 u32 mac; 1857 u32 bb; 1858 u32 rf; 1859 }; 1860 1861 struct rtw89_btc_wl_afh_info { 1862 u8 en; 1863 u8 ch; 1864 u8 bw; 1865 u8 rsvd; 1866 } __packed; 1867 1868 struct rtw89_btc_wl_rfk_info { 1869 u32 state: 2; 1870 u32 path_map: 4; 1871 u32 phy_map: 2; 1872 u32 band: 2; 1873 u32 type: 8; 1874 u32 con_rfk: 1; 1875 u32 rsvd: 13; 1876 1877 u32 start_time; 1878 u32 proc_time; 1879 }; 1880 1881 struct rtw89_btc_bt_smap { 1882 u32 connect: 1; 1883 u32 ble_connect: 1; 1884 u32 acl_busy: 1; 1885 u32 sco_busy: 1; 1886 u32 mesh_busy: 1; 1887 u32 inq_pag: 1; 1888 }; 1889 1890 union rtw89_btc_bt_state_map { 1891 u32 val; 1892 struct rtw89_btc_bt_smap map; 1893 }; 1894 1895 #define BTC_BT_RSSI_THMAX 4 1896 #define BTC_BT_AFH_GROUP 12 1897 #define BTC_BT_AFH_LE_GROUP 5 1898 1899 struct rtw89_btc_bt_txpwr_desc { 1900 s8 br_dbm; 1901 s8 le_dbm; 1902 u8 br_gain_index; 1903 u8 le_gain_index; 1904 }; 1905 1906 struct rtw89_btc_bt_link_info { 1907 struct rtw89_btc_u8_sta_chg profile_cnt; 1908 struct rtw89_btc_bool_sta_chg multi_link; 1909 struct rtw89_btc_bool_sta_chg relink; 1910 struct rtw89_btc_bt_hfp_desc hfp_desc; 1911 struct rtw89_btc_bt_hid_desc hid_desc; 1912 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1913 struct rtw89_btc_bt_pan_desc pan_desc; 1914 union rtw89_btc_bt_state_map status; 1915 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 1916 1917 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1918 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1919 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1920 u8 afh_map[BTC_BT_AFH_GROUP]; 1921 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1922 1923 u32 role_sw: 1; 1924 u32 slave_role: 1; 1925 u32 afh_update: 1; 1926 u32 cqddr: 1; 1927 u32 rssi: 8; 1928 u32 tx_3m: 1; 1929 u32 rsvd: 19; 1930 }; 1931 1932 struct rtw89_btc_3rdcx_info { 1933 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1934 u8 hw_coex; 1935 u16 rsvd; 1936 }; 1937 1938 struct rtw89_btc_dm_emap { 1939 u32 init: 1; 1940 u32 pta_owner: 1; 1941 u32 wl_rfk_timeout: 1; 1942 u32 bt_rfk_timeout: 1; 1943 u32 wl_fw_hang: 1; 1944 u32 cycle_hang: 1; 1945 u32 w1_hang: 1; 1946 u32 b1_hang: 1; 1947 u32 tdma_no_sync: 1; 1948 u32 slot_no_sync: 1; 1949 u32 wl_slot_drift: 1; 1950 u32 bt_slot_drift: 1; 1951 u32 role_num_mismatch: 1; 1952 u32 null1_tx_late: 1; 1953 u32 bt_afh_conflict: 1; 1954 u32 bt_leafh_conflict: 1; 1955 u32 bt_slot_flood: 1; 1956 u32 wl_e2g_hang: 1; 1957 u32 wl_ver_mismatch: 1; 1958 u32 bt_ver_mismatch: 1; 1959 u32 rfe_type0: 1; 1960 u32 h2c_buffer_over: 1; 1961 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1962 u32 wl_no_sta_ntfy: 1; 1963 1964 u32 h2c_bmap_mismatch: 1; 1965 u32 c2h_bmap_mismatch: 1; 1966 u32 h2c_struct_invalid: 1; 1967 u32 c2h_struct_invalid: 1; 1968 u32 h2c_c2h_buffer_mismatch: 1; 1969 }; 1970 1971 union rtw89_btc_dm_error_map { 1972 u32 val; 1973 struct rtw89_btc_dm_emap map; 1974 }; 1975 1976 struct rtw89_btc_rf_para { 1977 u32 tx_pwr_freerun; 1978 u32 rx_gain_freerun; 1979 u32 tx_pwr_perpkt; 1980 u32 rx_gain_perpkt; 1981 }; 1982 1983 struct rtw89_btc_wl_nhm { 1984 u8 instant_wl_nhm_dbm; 1985 u8 instant_wl_nhm_per_mhz; 1986 u16 valid_record_times; 1987 s8 record_pwr[16]; 1988 u8 record_ratio[16]; 1989 s8 pwr; /* dbm_per_MHz */ 1990 u8 ratio; 1991 u8 current_status; 1992 u8 refresh; 1993 bool start_flag; 1994 s8 pwr_max; 1995 s8 pwr_min; 1996 }; 1997 1998 struct rtw89_btc_wl_info { 1999 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 2000 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2001 struct rtw89_btc_wl_rfk_info rfk_info; 2002 struct rtw89_btc_wl_ver_info ver_info; 2003 struct rtw89_btc_wl_afh_info afh_info; 2004 struct rtw89_btc_wl_role_info role_info; 2005 struct rtw89_btc_wl_role_info_v1 role_info_v1; 2006 struct rtw89_btc_wl_role_info_v2 role_info_v2; 2007 struct rtw89_btc_wl_role_info_v7 role_info_v7; 2008 struct rtw89_btc_wl_role_info_v8 role_info_v8; 2009 struct rtw89_btc_wl_scan_info scan_info; 2010 struct rtw89_btc_wl_dbcc_info dbcc_info; 2011 struct rtw89_btc_wl_mlo_info mlo_info; 2012 struct rtw89_btc_rf_para rf_para; 2013 struct rtw89_btc_wl_nhm nhm; 2014 union rtw89_btc_wl_state_map status; 2015 2016 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 2017 u8 rssi_level; 2018 u8 cn_report; 2019 u8 coex_mode; 2020 u8 pta_req_mac; 2021 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 2022 2023 bool is_5g_hi_channel; 2024 bool go_client_exist; 2025 bool noa_exist; 2026 bool pta_reg_mac_chg; 2027 bool bg_mode; 2028 bool he_mode; 2029 bool scbd_change; 2030 bool fw_ver_mismatch; 2031 bool client_cnt_inc_2g; 2032 bool link_mode_chg; 2033 bool dbcc_chg; 2034 u32 scbd; 2035 }; 2036 2037 struct rtw89_btc_module { 2038 struct rtw89_btc_ant_info ant; 2039 u8 rfe_type; 2040 u8 cv; 2041 2042 u8 bt_solo: 1; 2043 u8 bt_pos: 1; 2044 u8 switch_type: 1; 2045 u8 wa_type: 3; 2046 2047 u8 kt_ver_adie; 2048 }; 2049 2050 struct rtw89_btc_module_v7 { 2051 u8 rfe_type; 2052 u8 kt_ver; 2053 u8 bt_solo; 2054 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2055 2056 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 2057 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 2058 u8 kt_ver_adie; 2059 u8 rsvd; 2060 2061 struct rtw89_btc_ant_info_v7 ant; 2062 } __packed; 2063 2064 union rtw89_btc_module_info { 2065 struct rtw89_btc_module md; 2066 struct rtw89_btc_module_v7 md_v7; 2067 }; 2068 2069 #define RTW89_BTC_DM_MAXSTEP 30 2070 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 2071 2072 struct rtw89_btc_dm_step { 2073 u16 step[RTW89_BTC_DM_MAXSTEP]; 2074 u8 step_pos; 2075 bool step_ov; 2076 }; 2077 2078 struct rtw89_btc_init_info { 2079 struct rtw89_btc_module module; 2080 u8 wl_guard_ch; 2081 2082 u8 wl_only: 1; 2083 u8 wl_init_ok: 1; 2084 u8 dbcc_en: 1; 2085 u8 cx_other: 1; 2086 u8 bt_only: 1; 2087 2088 u16 rsvd; 2089 }; 2090 2091 struct rtw89_btc_init_info_v7 { 2092 u8 wl_guard_ch; 2093 u8 wl_only; 2094 u8 wl_init_ok; 2095 u8 rsvd3; 2096 2097 u8 cx_other; 2098 u8 bt_only; 2099 u8 pta_mode; 2100 u8 pta_direction; 2101 2102 struct rtw89_btc_module_v7 module; 2103 } __packed; 2104 2105 union rtw89_btc_init_info_u { 2106 struct rtw89_btc_init_info init; 2107 struct rtw89_btc_init_info_v7 init_v7; 2108 }; 2109 2110 struct rtw89_btc_wl_tx_limit_para { 2111 u16 enable; 2112 u32 tx_time; /* unit: us */ 2113 u16 tx_retry; 2114 }; 2115 2116 enum rtw89_btc_bt_scan_type { 2117 BTC_SCAN_INQ = 0, 2118 BTC_SCAN_PAGE, 2119 BTC_SCAN_BLE, 2120 BTC_SCAN_INIT, 2121 BTC_SCAN_TV, 2122 BTC_SCAN_ADV, 2123 BTC_SCAN_MAX1, 2124 }; 2125 2126 enum rtw89_btc_ble_scan_type { 2127 CXSCAN_BG = 0, 2128 CXSCAN_INIT, 2129 CXSCAN_LE, 2130 CXSCAN_MAX 2131 }; 2132 2133 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2134 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2135 2136 struct rtw89_btc_bt_scan_info_v1 { 2137 __le16 win; 2138 __le16 intvl; 2139 __le32 flags; 2140 } __packed; 2141 2142 struct rtw89_btc_bt_scan_info_v2 { 2143 __le16 win; 2144 __le16 intvl; 2145 } __packed; 2146 2147 struct rtw89_btc_fbtc_btscan_v1 { 2148 u8 fver; /* btc_ver::fcxbtscan */ 2149 u8 rsvd; 2150 __le16 rsvd2; 2151 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2152 } __packed; 2153 2154 struct rtw89_btc_fbtc_btscan_v2 { 2155 u8 fver; /* btc_ver::fcxbtscan */ 2156 u8 type; 2157 __le16 rsvd2; 2158 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2159 } __packed; 2160 2161 struct rtw89_btc_fbtc_btscan_v7 { 2162 u8 fver; /* btc_ver::fcxbtscan */ 2163 u8 type; 2164 u8 rsvd0; 2165 u8 rsvd1; 2166 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2167 } __packed; 2168 2169 union rtw89_btc_fbtc_btscan { 2170 struct rtw89_btc_fbtc_btscan_v1 v1; 2171 struct rtw89_btc_fbtc_btscan_v2 v2; 2172 struct rtw89_btc_fbtc_btscan_v7 v7; 2173 }; 2174 2175 struct rtw89_btc_bt_info { 2176 struct rtw89_btc_bt_link_info link_info; 2177 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2178 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2179 struct rtw89_btc_bt_ver_info ver_info; 2180 struct rtw89_btc_bool_sta_chg enable; 2181 struct rtw89_btc_bool_sta_chg inq_pag; 2182 struct rtw89_btc_rf_para rf_para; 2183 union rtw89_btc_bt_rfk_info_map rfk_info; 2184 2185 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2186 u8 txpwr_info[BTC_BTINFO_MAX]; 2187 u8 rssi_level; 2188 2189 u32 scbd; 2190 u32 feature; 2191 2192 u32 mbx_avl: 1; 2193 u32 whql_test: 1; 2194 u32 igno_wl: 1; 2195 u32 reinit: 1; 2196 u32 ble_scan_en: 1; 2197 u32 btg_type: 1; 2198 u32 inq: 1; 2199 u32 pag: 1; 2200 u32 run_patch_code: 1; 2201 u32 hi_lna_rx: 1; 2202 u32 scan_rx_low_pri: 1; 2203 u32 scan_info_update: 1; 2204 u32 lna_constrain: 3; 2205 u32 rsvd: 17; 2206 }; 2207 2208 struct rtw89_btc_rf_trx_para_v9 { 2209 u32 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 1's complement -5->0x85 */ 2210 u32 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */ 2211 u32 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */ 2212 u32 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */ 2213 u32 zb_tx_power[BTC_ALL_BT]; /* 15.4 devrease Tx power (dB) */ 2214 u32 zb_rx_gain[BTC_ALL_BT]; /* 15.4 constrain level */ 2215 }; 2216 2217 struct rtw89_btc_cx { 2218 struct rtw89_btc_wl_info wl; 2219 struct rtw89_btc_bt_info bt; 2220 struct rtw89_btc_3rdcx_info other; 2221 u32 state_map; 2222 u32 cnt_bt[BTC_BCNT_NUM]; 2223 u32 cnt_wl[BTC_WCNT_NUM]; 2224 }; 2225 2226 struct rtw89_btc_fbtc_tdma { 2227 u8 type; /* btc_ver::fcxtdma */ 2228 u8 rxflctrl; 2229 u8 txpause; 2230 u8 wtgle_n; 2231 u8 leak_n; 2232 u8 ext_ctrl; 2233 u8 rxflctrl_role; 2234 u8 option_ctrl; 2235 } __packed; 2236 2237 struct rtw89_btc_fbtc_tdma_v3 { 2238 u8 fver; /* btc_ver::fcxtdma */ 2239 u8 rsvd; 2240 __le16 rsvd1; 2241 struct rtw89_btc_fbtc_tdma tdma; 2242 } __packed; 2243 2244 union rtw89_btc_fbtc_tdma_le32 { 2245 struct rtw89_btc_fbtc_tdma v1; 2246 struct rtw89_btc_fbtc_tdma_v3 v3; 2247 }; 2248 2249 #define CXMREG_MAX 30 2250 #define CXMREG_MAX_V2 20 2251 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2252 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2253 2254 enum rtw89_btc_bt_sta_counter { 2255 BTC_BCNT_RFK_REQ = 0, 2256 BTC_BCNT_RFK_GO = 1, 2257 BTC_BCNT_RFK_REJECT = 2, 2258 BTC_BCNT_RFK_FAIL = 3, 2259 BTC_BCNT_RFK_TIMEOUT = 4, 2260 BTC_BCNT_HI_TX = 5, 2261 BTC_BCNT_HI_RX = 6, 2262 BTC_BCNT_LO_TX = 7, 2263 BTC_BCNT_LO_RX = 8, 2264 BTC_BCNT_POLLUTED = 9, 2265 BTC_BCNT_STA_MAX 2266 }; 2267 2268 enum rtw89_btc_bt_sta_counter_v105 { 2269 BTC_BCNT_RFK_REQ_V105 = 0, 2270 BTC_BCNT_HI_TX_V105 = 1, 2271 BTC_BCNT_HI_RX_V105 = 2, 2272 BTC_BCNT_LO_TX_V105 = 3, 2273 BTC_BCNT_LO_RX_V105 = 4, 2274 BTC_BCNT_POLLUTED_V105 = 5, 2275 BTC_BCNT_STA_MAX_V105 2276 }; 2277 2278 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2279 u16 fver; /* btc_ver::fcxbtcrpt */ 2280 u16 rpt_cnt; /* tmr counters */ 2281 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2282 u32 wl_fw_cx_offload; 2283 u32 wl_fw_ver; 2284 u32 rpt_enable; 2285 u32 rpt_para; /* ms */ 2286 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2287 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2288 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2289 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2290 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2291 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2292 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2293 u32 c2h_cnt; /* fw send c2h counter */ 2294 u32 h2c_cnt; /* fw recv h2c counter */ 2295 } __packed; 2296 2297 struct rtw89_btc_fbtc_rpt_ctrl_info { 2298 __le32 cnt; /* fw report counter */ 2299 __le32 en; /* report map */ 2300 __le32 para; /* not used */ 2301 2302 __le32 cnt_c2h; /* fw send c2h counter */ 2303 __le32 cnt_h2c; /* fw recv h2c counter */ 2304 __le32 len_c2h; /* The total length of the last C2H */ 2305 2306 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2307 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2308 } __packed; 2309 2310 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2311 __le32 cx_ver; /* match which driver's coex version */ 2312 __le32 fw_ver; 2313 __le32 en; /* report map */ 2314 2315 __le16 cnt; /* fw report counter */ 2316 __le16 cnt_c2h; /* fw send c2h counter */ 2317 __le16 cnt_h2c; /* fw recv h2c counter */ 2318 __le16 len_c2h; /* The total length of the last C2H */ 2319 2320 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2321 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2322 } __packed; 2323 2324 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2325 __le16 cnt; /* fw report counter */ 2326 __le16 cnt_c2h; /* fw send c2h counter */ 2327 __le16 cnt_h2c; /* fw recv h2c counter */ 2328 __le16 len_c2h; /* The total length of the last C2H */ 2329 2330 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2331 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2332 2333 __le32 cx_ver; /* match which driver's coex version */ 2334 __le32 fw_ver; 2335 __le32 en; /* report map */ 2336 } __packed; 2337 2338 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2339 __le32 cx_ver; /* match which driver's coex version */ 2340 __le32 cx_offload; 2341 __le32 fw_ver; 2342 } __packed; 2343 2344 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2345 __le32 cnt_empty; /* a2dp empty count */ 2346 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2347 __le32 cnt_tx; 2348 __le32 cnt_ack; 2349 __le32 cnt_nack; 2350 } __packed; 2351 2352 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2353 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2354 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2355 __le32 cnt_recv; /* fw recv mailbox counter */ 2356 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2357 } __packed; 2358 2359 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2360 u8 fver; 2361 u8 rsvd; 2362 __le16 rsvd1; 2363 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2364 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2365 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2366 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2367 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2368 } __packed; 2369 2370 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2371 u8 fver; 2372 u8 rsvd; 2373 __le16 rsvd1; 2374 2375 u8 gnt_val[RTW89_PHY_NUM][4]; 2376 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2377 2378 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2379 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2380 } __packed; 2381 2382 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2383 u8 fver; 2384 u8 rsvd; 2385 __le16 rsvd1; 2386 2387 u8 gnt_val[RTW89_PHY_NUM][4]; 2388 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2389 2390 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2391 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2392 } __packed; 2393 2394 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2395 u8 fver; 2396 u8 rsvd0; 2397 u8 rsvd1; 2398 u8 rsvd2; 2399 2400 u8 gnt_val[RTW89_PHY_NUM][4]; 2401 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2402 2403 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2404 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2405 } __packed; 2406 2407 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2408 u8 fver; 2409 u8 rsvd0; 2410 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2411 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2412 2413 u8 gnt_val[RTW89_PHY_NUM][4]; 2414 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2415 2416 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2417 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2418 } __packed; 2419 2420 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2421 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2422 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2423 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2424 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2425 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2426 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2427 }; 2428 2429 enum rtw89_fbtc_ext_ctrl_type { 2430 CXECTL_OFF = 0x0, /* tdma off */ 2431 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2432 CXECTL_EXT = 0x2, 2433 CXECTL_MAX 2434 }; 2435 2436 union rtw89_btc_fbtc_rxflct { 2437 u8 val; 2438 u8 type: 3; 2439 u8 tgln_n: 5; 2440 }; 2441 2442 enum rtw89_btc_cxst_state { 2443 CXST_OFF = 0x0, 2444 CXST_B2W = 0x1, 2445 CXST_W1 = 0x2, 2446 CXST_W2 = 0x3, 2447 CXST_W2B = 0x4, 2448 CXST_B1 = 0x5, 2449 CXST_B2 = 0x6, 2450 CXST_B3 = 0x7, 2451 CXST_B4 = 0x8, 2452 CXST_LK = 0x9, 2453 CXST_BLK = 0xa, 2454 CXST_E2G = 0xb, 2455 CXST_E5G = 0xc, 2456 CXST_EBT = 0xd, 2457 CXST_ENULL = 0xe, 2458 CXST_WLK = 0xf, 2459 CXST_W1FDD = 0x10, 2460 CXST_B1FDD = 0x11, 2461 CXST_MAX = 0x12, 2462 }; 2463 2464 enum rtw89_btc_cxevnt { 2465 CXEVNT_TDMA_ENTRY = 0x0, 2466 CXEVNT_WL_TMR, 2467 CXEVNT_B1_TMR, 2468 CXEVNT_B2_TMR, 2469 CXEVNT_B3_TMR, 2470 CXEVNT_B4_TMR, 2471 CXEVNT_W2B_TMR, 2472 CXEVNT_B2W_TMR, 2473 CXEVNT_BCN_EARLY, 2474 CXEVNT_A2DP_EMPTY, 2475 CXEVNT_LK_END, 2476 CXEVNT_RX_ISR, 2477 CXEVNT_RX_FC0, 2478 CXEVNT_RX_FC1, 2479 CXEVNT_BT_RELINK, 2480 CXEVNT_BT_RETRY, 2481 CXEVNT_E2G, 2482 CXEVNT_E5G, 2483 CXEVNT_EBT, 2484 CXEVNT_ENULL, 2485 CXEVNT_DRV_WLK, 2486 CXEVNT_BCN_OK, 2487 CXEVNT_BT_CHANGE, 2488 CXEVNT_EBT_EXTEND, 2489 CXEVNT_E2G_NULL1, 2490 CXEVNT_B1FDD_TMR, 2491 CXEVNT_MAX 2492 }; 2493 2494 enum { 2495 CXBCN_ALL = 0x0, 2496 CXBCN_ALL_OK, 2497 CXBCN_BT_SLOT, 2498 CXBCN_BT_OK, 2499 CXBCN_MAX 2500 }; 2501 2502 enum btc_slot_type { 2503 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2504 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2505 CXSTYPE_NUM, 2506 }; 2507 2508 enum { /* TIME */ 2509 CXT_BT = 0x0, 2510 CXT_WL = 0x1, 2511 CXT_MAX 2512 }; 2513 2514 enum { /* TIME-A2DP */ 2515 CXT_FLCTRL_OFF = 0x0, 2516 CXT_FLCTRL_ON = 0x1, 2517 CXT_FLCTRL_MAX 2518 }; 2519 2520 enum { /* STEP TYPE */ 2521 CXSTEP_NONE = 0x0, 2522 CXSTEP_EVNT = 0x1, 2523 CXSTEP_SLOT = 0x2, 2524 CXSTEP_MAX, 2525 }; 2526 2527 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2528 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2529 RPT_BT_AFH_SEQ_LE = 0x20 2530 }; 2531 2532 #define BTC_DBG_MAX1 32 2533 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2534 u8 fver; /* btc_ver::fcxgpiodbg */ 2535 u8 rsvd; 2536 __le16 rsvd2; 2537 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2538 __le32 pre_state; /* the debug signal is 1 or 0 */ 2539 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2540 } __packed; 2541 2542 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2543 u8 fver; 2544 u8 rsvd0; 2545 u8 rsvd1; 2546 u8 rsvd2; 2547 2548 u8 gpio_map[BTC_DBG_MAX1]; 2549 2550 __le32 en_map; 2551 __le32 pre_state; 2552 } __packed; 2553 2554 union rtw89_btc_fbtc_gpio_dbg { 2555 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2556 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2557 }; 2558 2559 struct rtw89_btc_fbtc_mreg_val_v1 { 2560 u8 fver; /* btc_ver::fcxmreg */ 2561 u8 reg_num; 2562 __le16 rsvd; 2563 __le32 mreg_val[CXMREG_MAX]; 2564 } __packed; 2565 2566 struct rtw89_btc_fbtc_mreg_val_v2 { 2567 u8 fver; /* btc_ver::fcxmreg */ 2568 u8 reg_num; 2569 __le16 rsvd; 2570 __le32 mreg_val[CXMREG_MAX_V2]; 2571 } __packed; 2572 2573 struct rtw89_btc_fbtc_mreg_val_v7 { 2574 u8 fver; 2575 u8 reg_num; 2576 u8 rsvd0; 2577 u8 rsvd1; 2578 __le32 mreg_val[CXMREG_MAX_V2]; 2579 } __packed; 2580 2581 union rtw89_btc_fbtc_mreg_val { 2582 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2583 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2584 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2585 }; 2586 2587 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2588 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2589 .offset = cpu_to_le32(__offset), } 2590 2591 struct rtw89_btc_fbtc_mreg { 2592 __le16 type; 2593 __le16 bytes; 2594 __le32 offset; 2595 } __packed; 2596 2597 struct rtw89_btc_fbtc_slot { 2598 __le16 dur; 2599 __le32 cxtbl; 2600 __le16 cxtype; 2601 } __packed; 2602 2603 struct rtw89_btc_fbtc_slots { 2604 u8 fver; /* btc_ver::fcxslots */ 2605 u8 tbl_num; 2606 __le16 rsvd; 2607 __le32 update_map; 2608 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2609 } __packed; 2610 2611 struct rtw89_btc_fbtc_slot_v7 { 2612 __le16 dur; /* slot duration */ 2613 __le16 cxtype; 2614 __le32 cxtbl; 2615 } __packed; 2616 2617 struct rtw89_btc_fbtc_slot_u16 { 2618 __le16 dur; /* slot duration */ 2619 __le16 cxtype; 2620 __le16 cxtbl_l16; /* coex table [15:0] */ 2621 __le16 cxtbl_h16; /* coex table [31:16] */ 2622 } __packed; 2623 2624 struct rtw89_btc_fbtc_1slot_v7 { 2625 u8 fver; 2626 u8 sid; /* slot id */ 2627 __le16 rsvd; 2628 struct rtw89_btc_fbtc_slot_v7 slot; 2629 } __packed; 2630 2631 struct rtw89_btc_fbtc_slots_v7 { 2632 u8 fver; 2633 u8 slot_cnt; 2634 u8 rsvd0; 2635 u8 rsvd1; 2636 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2637 __le32 update_map; 2638 } __packed; 2639 2640 union rtw89_btc_fbtc_slots_info { 2641 struct rtw89_btc_fbtc_slots v1; 2642 struct rtw89_btc_fbtc_slots_v7 v7; 2643 } __packed; 2644 2645 struct rtw89_btc_fbtc_step { 2646 u8 type; 2647 u8 val; 2648 __le16 difft; 2649 } __packed; 2650 2651 struct rtw89_btc_fbtc_steps_v2 { 2652 u8 fver; /* btc_ver::fcxstep */ 2653 u8 rsvd; 2654 __le16 cnt; 2655 __le16 pos_old; 2656 __le16 pos_new; 2657 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2658 } __packed; 2659 2660 struct rtw89_btc_fbtc_steps_v3 { 2661 u8 fver; 2662 u8 en; 2663 __le16 rsvd; 2664 __le32 cnt; 2665 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2666 } __packed; 2667 2668 union rtw89_btc_fbtc_steps_info { 2669 struct rtw89_btc_fbtc_steps_v2 v2; 2670 struct rtw89_btc_fbtc_steps_v3 v3; 2671 }; 2672 2673 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2674 u8 fver; /* btc_ver::fcxcysta */ 2675 u8 rsvd; 2676 __le16 cycles; /* total cycle number */ 2677 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2678 __le16 a2dpept; /* a2dp empty cnt */ 2679 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2680 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2681 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2682 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2683 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2684 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2685 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2686 __le16 tmax_a2dpept; /* max a2dp empty time */ 2687 __le16 tavg_lk; /* avg leak-slot time */ 2688 __le16 tmax_lk; /* max leak-slot time */ 2689 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2690 __le32 bcn_cnt[CXBCN_MAX]; 2691 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2692 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2693 __le32 skip_cnt; 2694 __le32 exception; 2695 __le32 except_cnt; 2696 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2697 } __packed; 2698 2699 struct rtw89_btc_fbtc_fdd_try_info { 2700 __le16 cycles[CXT_FLCTRL_MAX]; 2701 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2702 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2703 } __packed; 2704 2705 struct rtw89_btc_fbtc_cycle_time_info { 2706 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2707 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2708 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2709 } __packed; 2710 2711 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2712 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2713 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2714 } __packed; 2715 2716 struct rtw89_btc_fbtc_a2dp_trx_stat { 2717 u8 empty_cnt; 2718 u8 retry_cnt; 2719 u8 tx_rate; 2720 u8 tx_cnt; 2721 u8 ack_cnt; 2722 u8 nack_cnt; 2723 u8 rsvd1; 2724 u8 rsvd2; 2725 } __packed; 2726 2727 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2728 u8 empty_cnt; 2729 u8 retry_cnt; 2730 u8 tx_rate; 2731 u8 tx_cnt; 2732 u8 ack_cnt; 2733 u8 nack_cnt; 2734 u8 no_empty_cnt; 2735 u8 rsvd; 2736 } __packed; 2737 2738 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2739 __le16 cnt; /* a2dp empty cnt */ 2740 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2741 __le16 tavg; /* avg a2dp empty time */ 2742 __le16 tmax; /* max a2dp empty time */ 2743 } __packed; 2744 2745 struct rtw89_btc_fbtc_cycle_leak_info { 2746 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2747 __le16 tavg; /* avg leak-slot time */ 2748 __le16 tmax; /* max leak-slot time */ 2749 } __packed; 2750 2751 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2752 __le16 tavg; 2753 __le16 tamx; 2754 __le32 cnt_rximr; 2755 } __packed; 2756 2757 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2758 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2759 2760 struct rtw89_btc_fbtc_cycle_fddt_info { 2761 __le16 train_cycle; 2762 __le16 tp; 2763 2764 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2765 s8 bt_tx_power; /* decrease Tx power (dB) */ 2766 s8 bt_rx_gain; /* LNA constrain level */ 2767 u8 no_empty_cnt; 2768 2769 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2770 u8 cn; /* condition_num */ 2771 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2772 u8 train_result; /* refer to enum btc_fddt_check_map */ 2773 } __packed; 2774 2775 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2776 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2777 2778 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2779 __le16 train_cycle; 2780 __le16 tp; 2781 2782 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2783 s8 bt_tx_power; /* decrease Tx power (dB) */ 2784 s8 bt_rx_gain; /* LNA constrain level */ 2785 u8 no_empty_cnt; 2786 2787 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2788 u8 cn; /* condition_num */ 2789 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2790 u8 train_result; /* refer to enum btc_fddt_check_map */ 2791 } __packed; 2792 2793 struct rtw89_btc_fbtc_fddt_cell_status { 2794 s8 wl_tx_pwr; 2795 s8 bt_tx_pwr; 2796 s8 bt_rx_gain; 2797 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2798 } __packed; 2799 2800 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2801 u8 fver; 2802 u8 rsvd; 2803 __le16 cycles; /* total cycle number */ 2804 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2805 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2806 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2807 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2808 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2809 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2810 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2811 __le32 bcn_cnt[CXBCN_MAX]; 2812 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2813 __le32 skip_cnt; 2814 __le32 except_cnt; 2815 __le32 except_map; 2816 } __packed; 2817 2818 #define FDD_TRAIN_WL_DIRECTION 2 2819 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2820 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2821 2822 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2823 u8 fver; 2824 u8 rsvd; 2825 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2826 u8 except_cnt; 2827 2828 __le16 skip_cnt; 2829 __le16 cycles; /* total cycle number */ 2830 2831 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2832 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2833 __le16 bcn_cnt[CXBCN_MAX]; 2834 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2835 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2836 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2837 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2838 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2839 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2840 [FDD_TRAIN_WL_RSSI_LEVEL] 2841 [FDD_TRAIN_BT_RSSI_LEVEL]; 2842 __le32 except_map; 2843 } __packed; 2844 2845 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2846 u8 fver; 2847 u8 rsvd; 2848 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2849 u8 except_cnt; 2850 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2851 2852 __le16 skip_cnt; 2853 __le16 cycles; /* total cycle number */ 2854 2855 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2856 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2857 __le16 bcn_cnt[CXBCN_MAX]; 2858 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2859 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2860 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2861 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2862 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2863 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2864 [FDD_TRAIN_WL_RSSI_LEVEL] 2865 [FDD_TRAIN_BT_RSSI_LEVEL]; 2866 __le32 except_map; 2867 } __packed; 2868 2869 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2870 u8 fver; 2871 u8 rsvd; 2872 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2873 u8 except_cnt; 2874 2875 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2876 2877 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2878 2879 __le16 skip_cnt; 2880 __le16 cycles; /* total cycle number */ 2881 2882 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2883 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2884 __le16 bcn_cnt[CXBCN_MAX]; 2885 2886 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2887 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2888 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2889 2890 __le32 except_map; 2891 } __packed; 2892 2893 union rtw89_btc_fbtc_cysta_info { 2894 struct rtw89_btc_fbtc_cysta_v2 v2; 2895 struct rtw89_btc_fbtc_cysta_v3 v3; 2896 struct rtw89_btc_fbtc_cysta_v4 v4; 2897 struct rtw89_btc_fbtc_cysta_v5 v5; 2898 struct rtw89_btc_fbtc_cysta_v7 v7; 2899 }; 2900 2901 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2902 u8 fver; /* btc_ver::fcxnullsta */ 2903 u8 rsvd; 2904 __le16 rsvd2; 2905 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2906 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2907 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2908 } __packed; 2909 2910 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2911 u8 fver; /* btc_ver::fcxnullsta */ 2912 u8 rsvd; 2913 __le16 rsvd2; 2914 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2915 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2916 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2917 } __packed; 2918 2919 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2920 u8 fver; 2921 u8 rsvd0; 2922 u8 rsvd1; 2923 u8 rsvd2; 2924 2925 __le32 tmax[2]; 2926 __le32 tavg[2]; 2927 __le32 result[2][5]; 2928 } __packed; 2929 2930 union rtw89_btc_fbtc_cynullsta_info { 2931 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2932 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2933 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2934 }; 2935 2936 struct rtw89_btc_fbtc_btver_v1 { 2937 u8 fver; /* btc_ver::fcxbtver */ 2938 u8 rsvd; 2939 __le16 rsvd2; 2940 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2941 __le32 fw_ver; 2942 __le32 feature; 2943 } __packed; 2944 2945 struct rtw89_btc_fbtc_btver_v7 { 2946 u8 fver; 2947 u8 rsvd0; 2948 u8 rsvd1; 2949 u8 rsvd2; 2950 2951 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2952 __le32 fw_ver; 2953 __le32 feature; 2954 } __packed; 2955 2956 union rtw89_btc_fbtc_btver { 2957 struct rtw89_btc_fbtc_btver_v1 v1; 2958 struct rtw89_btc_fbtc_btver_v7 v7; 2959 } __packed; 2960 2961 struct rtw89_btc_fbtc_btafh { 2962 u8 fver; /* btc_ver::fcxbtafh */ 2963 u8 rsvd; 2964 __le16 rsvd2; 2965 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2966 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2967 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2968 } __packed; 2969 2970 struct rtw89_btc_fbtc_btafh_v2 { 2971 u8 fver; /* btc_ver::fcxbtafh */ 2972 u8 rsvd; 2973 u8 rsvd2; 2974 u8 map_type; 2975 u8 afh_l[4]; 2976 u8 afh_m[4]; 2977 u8 afh_h[4]; 2978 u8 afh_le_a[4]; 2979 u8 afh_le_b[4]; 2980 } __packed; 2981 2982 struct rtw89_btc_fbtc_btafh_v7 { 2983 u8 fver; 2984 u8 map_type; 2985 u8 rsvd0; 2986 u8 rsvd1; 2987 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2988 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2989 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2990 u8 afh_le_a[4]; 2991 u8 afh_le_b[4]; 2992 } __packed; 2993 2994 struct rtw89_btc_fbtc_btdevinfo { 2995 u8 fver; /* btc_ver::fcxbtdevinfo */ 2996 u8 rsvd; 2997 __le16 vendor_id; 2998 __le32 dev_name; /* only 24 bits valid */ 2999 __le32 flush_time; 3000 } __packed; 3001 3002 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 3003 struct rtw89_btc_rf_trx_para { 3004 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3005 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 3006 u8 bt_tx_power; /* decrease Tx power (dB) */ 3007 u8 bt_rx_gain; /* LNA constrain level */ 3008 }; 3009 3010 struct rtw89_btc_trx_info { 3011 u8 tx_lvl; 3012 u8 rx_lvl; 3013 u8 wl_rssi; 3014 u8 bt_rssi; 3015 3016 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3017 s8 rx_gain; /* rx gain table index (TBD.) */ 3018 s8 bt_tx_power; /* decrease Tx power (dB) */ 3019 s8 bt_rx_gain; /* LNA constrain level */ 3020 3021 u8 cn; /* condition_num */ 3022 s8 nhm; 3023 u8 bt_profile; 3024 u8 rsvd2; 3025 3026 u16 tx_rate; 3027 u16 rx_rate; 3028 3029 u32 tx_tp; 3030 u32 rx_tp; 3031 u32 rx_err_ratio; 3032 }; 3033 3034 enum btc_rf_path { 3035 BTC_RF_S0 = 0, 3036 BTC_RF_S1 = 1, 3037 BTC_RF_NUM, 3038 }; 3039 3040 struct rtw89_btc_fbtc_outsrc_set_info { 3041 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */ 3042 u8 btg_rx[BTC_RF_NUM]; 3043 u8 nbtg_tx[BTC_RF_NUM]; 3044 3045 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 3046 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */ 3047 3048 u8 pta_req_hw_band; 3049 u8 rf_gbt_source; 3050 } __packed; 3051 3052 union rtw89_btc_fbtc_slot_u { 3053 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 3054 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 3055 }; 3056 3057 struct rtw89_btc_dm { 3058 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 3059 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 3060 union rtw89_btc_fbtc_slot_u slot; 3061 union rtw89_btc_fbtc_slot_u slot_now; 3062 struct rtw89_btc_fbtc_tdma tdma; 3063 struct rtw89_btc_fbtc_tdma tdma_now; 3064 struct rtw89_mac_ax_coex_gnt gnt; 3065 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 3066 struct rtw89_btc_rf_trx_para rf_trx_para; 3067 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 3068 struct rtw89_btc_dm_step dm_step; 3069 struct rtw89_btc_wl_scc_ctrl wl_scc; 3070 struct rtw89_btc_trx_info trx_info; 3071 union rtw89_btc_dm_error_map error; 3072 u32 cnt_dm[BTC_DCNT_NUM]; 3073 u32 cnt_notify[BTC_NCNT_NUM]; 3074 3075 u32 update_slot_map; 3076 u32 set_ant_path; 3077 u32 e2g_slot_limit; 3078 u32 e2g_slot_nulltx_time; 3079 3080 u32 wl_only: 1; 3081 u32 wl_fw_cx_offload: 1; 3082 u32 freerun: 1; 3083 u32 fddt_train: 1; 3084 u32 wl_ps_ctrl: 2; 3085 u32 wl_mimo_ps: 1; 3086 u32 leak_ap: 1; 3087 u32 noisy_level: 3; 3088 u32 coex_info_map: 8; 3089 u32 bt_only: 1; 3090 u32 wl_btg_rx: 2; 3091 u32 trx_para_level: 8; 3092 u32 wl_stb_chg: 1; 3093 u32 pta_owner: 1; 3094 3095 u32 tdma_instant_excute: 1; 3096 u32 wl_btg_rx_rb: 2; 3097 3098 u16 slot_dur[CXST_MAX]; 3099 u16 bt_slot_flood; 3100 3101 u8 run_reason; 3102 u8 run_action; 3103 3104 u8 wl_pre_agc: 2; 3105 u8 wl_lna2: 1; 3106 u8 freerun_chk: 1; 3107 u8 wl_pre_agc_rb: 2; 3108 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 3109 u8 slot_req_more: 1; 3110 }; 3111 3112 struct rtw89_btc_ctrl { 3113 u32 manual: 1; 3114 u32 igno_bt: 1; 3115 u32 always_freerun: 1; 3116 u32 trace_step: 16; 3117 u32 rsvd: 12; 3118 }; 3119 3120 struct rtw89_btc_ctrl_v7 { 3121 u8 manual; 3122 u8 igno_bt; 3123 u8 always_freerun; 3124 u8 rsvd; 3125 } __packed; 3126 3127 union rtw89_btc_ctrl_list { 3128 struct rtw89_btc_ctrl ctrl; 3129 struct rtw89_btc_ctrl_v7 ctrl_v7; 3130 }; 3131 3132 struct rtw89_btc_dbg { 3133 /* cmd "rb" */ 3134 bool rb_done; 3135 u32 rb_val; 3136 }; 3137 3138 enum rtw89_btc_btf_fw_event { 3139 BTF_EVNT_RPT = 0, 3140 BTF_EVNT_BT_INFO = 1, 3141 BTF_EVNT_BT_SCBD = 2, 3142 BTF_EVNT_BT_REG = 3, 3143 BTF_EVNT_CX_RUNINFO = 4, 3144 BTF_EVNT_BT_PSD = 5, 3145 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 3146 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 3147 BTF_EVNT_BUF_OVERFLOW, 3148 BTF_EVNT_C2H_LOOPBACK, 3149 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 3150 BTF_EVNT_MAX, 3151 }; 3152 3153 enum btf_fw_event_report { 3154 BTC_RPT_TYPE_CTRL = 0x0, 3155 BTC_RPT_TYPE_TDMA, 3156 BTC_RPT_TYPE_SLOT, 3157 BTC_RPT_TYPE_CYSTA, 3158 BTC_RPT_TYPE_STEP, 3159 BTC_RPT_TYPE_NULLSTA, 3160 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3161 BTC_RPT_TYPE_MREG, 3162 BTC_RPT_TYPE_GPIO_DBG, 3163 BTC_RPT_TYPE_BT_VER, 3164 BTC_RPT_TYPE_BT_SCAN, 3165 BTC_RPT_TYPE_BT_AFH, 3166 BTC_RPT_TYPE_BT_DEVICE, 3167 BTC_RPT_TYPE_TEST, 3168 BTC_RPT_TYPE_MAX = 31, 3169 3170 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3171 __BTC_RPT_TYPE_V0_MAX = 12, 3172 }; 3173 3174 enum rtw_btc_btf_reg_type { 3175 REG_MAC = 0x0, 3176 REG_BB = 0x1, 3177 REG_RF = 0x2, 3178 REG_BT_RF = 0x3, 3179 REG_BT_MODEM = 0x4, 3180 REG_BT_BLUEWIZE = 0x5, 3181 REG_BT_VENDOR = 0x6, 3182 REG_BT_LE = 0x7, 3183 REG_MAX_TYPE, 3184 }; 3185 3186 struct rtw89_btc_rpt_cmn_info { 3187 u32 rx_cnt; 3188 u32 rx_len; 3189 u32 req_len; /* expected rsp len */ 3190 u8 req_fver; /* expected rsp fver */ 3191 u8 rsp_fver; /* fver from fw */ 3192 u8 valid; 3193 } __packed; 3194 3195 union rtw89_btc_fbtc_btafh_info { 3196 struct rtw89_btc_fbtc_btafh v1; 3197 struct rtw89_btc_fbtc_btafh_v2 v2; 3198 struct rtw89_btc_fbtc_btafh_v7 v7; 3199 }; 3200 3201 struct rtw89_btc_report_ctrl_state { 3202 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3203 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3204 }; 3205 3206 struct rtw89_btc_rpt_fbtc_tdma { 3207 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3208 union rtw89_btc_fbtc_tdma_le32 finfo; 3209 }; 3210 3211 struct rtw89_btc_rpt_fbtc_slots { 3212 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3213 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3214 }; 3215 3216 struct rtw89_btc_rpt_fbtc_cysta { 3217 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3218 union rtw89_btc_fbtc_cysta_info finfo; 3219 }; 3220 3221 struct rtw89_btc_rpt_fbtc_step { 3222 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3223 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3224 }; 3225 3226 struct rtw89_btc_rpt_fbtc_nullsta { 3227 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3228 union rtw89_btc_fbtc_cynullsta_info finfo; 3229 }; 3230 3231 struct rtw89_btc_rpt_fbtc_mreg { 3232 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3233 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3234 }; 3235 3236 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3237 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3238 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3239 }; 3240 3241 struct rtw89_btc_rpt_fbtc_btver { 3242 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3243 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3244 }; 3245 3246 struct rtw89_btc_rpt_fbtc_btscan { 3247 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3248 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3249 }; 3250 3251 struct rtw89_btc_rpt_fbtc_btafh { 3252 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3253 union rtw89_btc_fbtc_btafh_info finfo; 3254 }; 3255 3256 struct rtw89_btc_rpt_fbtc_btdev { 3257 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3258 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3259 }; 3260 3261 enum rtw89_btc_btfre_type { 3262 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3263 BTFRE_UNDEF_TYPE, 3264 BTFRE_EXCEPTION, 3265 BTFRE_MAX, 3266 }; 3267 3268 struct rtw89_btc_ver { 3269 enum rtw89_core_chip_id chip_id; 3270 u32 fw_ver_code; 3271 3272 u8 fcxbtcrpt; 3273 u8 fcxtdma; 3274 u8 fcxslots; 3275 u8 fcxcysta; 3276 u8 fcxstep; 3277 u8 fcxnullsta; 3278 u8 fcxmreg; 3279 u8 fcxgpiodbg; 3280 u8 fcxbtver; 3281 u8 fcxbtscan; 3282 u8 fcxbtafh; 3283 u8 fcxbtdevinfo; 3284 u8 fwlrole; 3285 u8 frptmap; 3286 u8 fcxctrl; 3287 u8 fcxinit; 3288 3289 u8 fwevntrptl; 3290 u8 fwc2hfunc; 3291 u8 drvinfo_type; 3292 u16 info_buf; 3293 u8 max_role_num; 3294 u8 fcxosi; 3295 u8 fcxmlo; 3296 u8 bt_desired; 3297 }; 3298 3299 struct rtw89_btc_btf_fwinfo { 3300 u32 cnt_c2h; 3301 u32 cnt_h2c; 3302 u32 cnt_h2c_fail; 3303 u32 event[BTF_EVNT_MAX]; 3304 3305 u32 err[BTFRE_MAX]; 3306 u32 len_mismch; 3307 u32 fver_mismch; 3308 u32 rpt_en_map; 3309 3310 struct rtw89_btc_ver fw_subver; 3311 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3312 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3313 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3314 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3315 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3316 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3317 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3318 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3319 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3320 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3321 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3322 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3323 }; 3324 3325 #define RTW89_BTC_POLICY_MAXLEN 512 3326 3327 struct rtw89_btc { 3328 const struct rtw89_btc_ver *ver; 3329 3330 struct rtw89_btc_cx cx; 3331 struct rtw89_btc_dm dm; 3332 union rtw89_btc_ctrl_list ctrl; 3333 union rtw89_btc_module_info mdinfo; 3334 struct rtw89_btc_btf_fwinfo fwinfo; 3335 struct rtw89_btc_dbg dbg; 3336 3337 struct wiphy_work eapol_notify_work; 3338 struct wiphy_work arp_notify_work; 3339 struct wiphy_work dhcp_notify_work; 3340 struct wiphy_work icmp_notify_work; 3341 3342 u32 bt_req_len; 3343 3344 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3345 u8 ant_type; 3346 u8 btg_pos; 3347 u16 policy_len; 3348 u16 policy_type; 3349 u32 hubmsg_cnt; 3350 bool bt_req_en; 3351 bool update_policy_force; 3352 bool lps; 3353 bool manual_ctrl; 3354 }; 3355 3356 enum rtw89_btc_hmsg { 3357 RTW89_BTC_HMSG_TMR_EN = 0x0, 3358 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3359 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3360 RTW89_BTC_HMSG_FW_EV = 0x3, 3361 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3362 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3363 3364 NUM_OF_RTW89_BTC_HMSG, 3365 }; 3366 3367 enum rtw89_ra_mode { 3368 RTW89_RA_MODE_CCK = BIT(0), 3369 RTW89_RA_MODE_OFDM = BIT(1), 3370 RTW89_RA_MODE_HT = BIT(2), 3371 RTW89_RA_MODE_VHT = BIT(3), 3372 RTW89_RA_MODE_HE = BIT(4), 3373 RTW89_RA_MODE_EHT = BIT(5), 3374 }; 3375 3376 enum rtw89_ra_report_mode { 3377 RTW89_RA_RPT_MODE_LEGACY, 3378 RTW89_RA_RPT_MODE_HT, 3379 RTW89_RA_RPT_MODE_VHT, 3380 RTW89_RA_RPT_MODE_HE, 3381 RTW89_RA_RPT_MODE_EHT, 3382 }; 3383 3384 enum rtw89_dig_noisy_level { 3385 RTW89_DIG_NOISY_LEVEL0 = -1, 3386 RTW89_DIG_NOISY_LEVEL1 = 0, 3387 RTW89_DIG_NOISY_LEVEL2 = 1, 3388 RTW89_DIG_NOISY_LEVEL3 = 2, 3389 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3390 }; 3391 3392 enum rtw89_gi_ltf { 3393 RTW89_GILTF_LGI_4XHE32 = 0, 3394 RTW89_GILTF_SGI_4XHE08 = 1, 3395 RTW89_GILTF_2XHE16 = 2, 3396 RTW89_GILTF_2XHE08 = 3, 3397 RTW89_GILTF_1XHE16 = 4, 3398 RTW89_GILTF_1XHE08 = 5, 3399 RTW89_GILTF_MAX 3400 }; 3401 3402 enum rtw89_rx_frame_type { 3403 RTW89_RX_TYPE_MGNT = 0, 3404 RTW89_RX_TYPE_CTRL = 1, 3405 RTW89_RX_TYPE_DATA = 2, 3406 RTW89_RX_TYPE_RSVD = 3, 3407 }; 3408 3409 enum rtw89_efuse_block { 3410 RTW89_EFUSE_BLOCK_SYS = 0, 3411 RTW89_EFUSE_BLOCK_RF = 1, 3412 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3413 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3414 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3415 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3416 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3417 RTW89_EFUSE_BLOCK_ADIE = 7, 3418 3419 RTW89_EFUSE_BLOCK_NUM, 3420 RTW89_EFUSE_BLOCK_IGNORE, 3421 }; 3422 3423 struct rtw89_ra_info { 3424 u8 is_dis_ra:1; 3425 /* Bit0 : CCK 3426 * Bit1 : OFDM 3427 * Bit2 : HT 3428 * Bit3 : VHT 3429 * Bit4 : HE 3430 * Bit5 : EHT 3431 */ 3432 u8 mode_ctrl:6; 3433 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3434 u8 macid; 3435 u8 dcm_cap:1; 3436 u8 er_cap:1; 3437 u8 init_rate_lv:2; 3438 u8 upd_all:1; 3439 u8 en_sgi:1; 3440 u8 ldpc_cap:1; 3441 u8 stbc_cap:1; 3442 u8 ss_num:3; 3443 u8 giltf:3; 3444 u8 upd_bw_nss_mask:1; 3445 u8 upd_mask:1; 3446 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3447 /* BFee CSI */ 3448 u8 band_num; 3449 u8 ra_csi_rate_en:1; 3450 u8 fixed_csi_rate_en:1; 3451 u8 cr_tbl_sel:1; 3452 u8 fix_giltf_en:1; 3453 u8 fix_giltf:3; 3454 u8 partial_bw_er:1; 3455 u8 csi_mcs_ss_idx; 3456 u8 csi_mode:2; 3457 u8 csi_gi_ltf:3; 3458 u8 csi_bw:3; 3459 /* after v1 */ 3460 u8 is_noisy:1; 3461 u8 psra_en:1; 3462 u8 rsvd0:1; 3463 u8 macid_msb:2; 3464 u8 band:2; /* enum rtw89_band */ 3465 u8 is_new_dbgreg:1; 3466 }; 3467 3468 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3469 #define RTW89_PPDU_MAC_INFO_SIZE 8 3470 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3471 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3472 3473 struct rtw89_ampdu_params { 3474 u16 agg_num; 3475 bool amsdu; 3476 }; 3477 3478 struct rtw89_ra_report { 3479 struct rate_info txrate; 3480 u32 bit_rate; 3481 u16 hw_rate; 3482 bool might_fallback_legacy; 3483 }; 3484 3485 DECLARE_EWMA(rssi, 10, 16); 3486 DECLARE_EWMA(evm, 10, 16); 3487 DECLARE_EWMA(snr, 10, 16); 3488 3489 struct rtw89_ba_cam_entry { 3490 struct list_head list; 3491 u8 tid; 3492 }; 3493 3494 #define RTW89_MAX_ADDR_CAM_NUM 128 3495 #define RTW89_MAX_BSSID_CAM_NUM 20 3496 #define RTW89_MAX_SEC_CAM_NUM 128 3497 #define RTW89_MAX_BA_CAM_NUM 24 3498 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3499 3500 struct rtw89_addr_cam_entry { 3501 u8 addr_cam_idx; 3502 u8 offset; 3503 u8 len; 3504 u8 valid : 1; 3505 u8 addr_mask : 6; 3506 u8 wapi : 1; 3507 u8 mask_sel : 2; 3508 u8 bssid_cam_idx: 6; 3509 3510 u8 sec_ent_mode; 3511 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3512 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3513 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3514 }; 3515 3516 struct rtw89_bssid_cam_entry { 3517 u8 bssid[ETH_ALEN]; 3518 u8 phy_idx; 3519 u8 bssid_cam_idx; 3520 u8 offset; 3521 u8 len; 3522 u8 valid : 1; 3523 u8 num; 3524 }; 3525 3526 struct rtw89_sec_cam_entry { 3527 u8 sec_cam_idx; 3528 u8 offset; 3529 u8 len; 3530 u8 type : 4; 3531 u8 ext_key : 1; 3532 u8 spp_mode : 1; 3533 /* 256 bits */ 3534 u8 key[32]; 3535 3536 struct ieee80211_key_conf *key_conf; 3537 }; 3538 3539 struct rtw89_sta_link { 3540 struct rtw89_sta *rtwsta; 3541 struct list_head dlink_schd; 3542 unsigned int link_id; 3543 3544 u8 mac_id; 3545 u8 tx_retry; 3546 bool er_cap; 3547 struct rtw89_vif_link *rtwvif_link; 3548 struct rtw89_ra_info ra; 3549 struct rtw89_ra_report ra_report; 3550 int max_agg_wait; 3551 u8 prev_rssi; 3552 struct ewma_rssi avg_rssi; 3553 struct ewma_rssi rssi[RF_PATH_MAX]; 3554 struct ewma_snr avg_snr; 3555 struct ewma_evm evm_1ss; 3556 struct ewma_evm evm_min[RF_PATH_MAX]; 3557 struct ewma_evm evm_max[RF_PATH_MAX]; 3558 struct ieee80211_rx_status rx_status; 3559 u16 rx_hw_rate; 3560 __le32 htc_template; 3561 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3562 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3563 struct list_head ba_cam_list; 3564 3565 bool use_cfg_mask; 3566 struct cfg80211_bitrate_mask mask; 3567 3568 bool cctl_tx_time; 3569 u32 ampdu_max_time:4; 3570 bool cctl_tx_retry_limit; 3571 u32 data_tx_cnt_lmt:6; 3572 }; 3573 3574 struct rtw89_efuse { 3575 bool valid; 3576 bool power_k_valid; 3577 u8 xtal_cap; 3578 u8 addr[ETH_ALEN]; 3579 u8 rfe_type; 3580 char country_code[2]; 3581 u8 adc_td; 3582 u8 bt_setting_2; 3583 u8 bt_setting_3; 3584 }; 3585 3586 struct rtw89_phy_rate_pattern { 3587 u64 ra_mask; 3588 u16 rate; 3589 u8 ra_mode; 3590 bool enable; 3591 }; 3592 3593 #define RTW89_TX_DONE 0x0 3594 #define RTW89_TX_RETRY_LIMIT 0x1 3595 #define RTW89_TX_LIFE_TIME 0x2 3596 #define RTW89_TX_MACID_DROP 0x3 3597 3598 #define RTW89_MAX_TX_RPTS 16 3599 #define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1) 3600 struct rtw89_tx_rpt { 3601 struct sk_buff *skbs[RTW89_MAX_TX_RPTS]; 3602 /* protect skbs array access/modification */ 3603 spinlock_t skb_lock; 3604 atomic_t sn; 3605 }; 3606 3607 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500) 3608 struct rtw89_tx_wait_info { 3609 struct rcu_head rcu_head; 3610 struct list_head list; 3611 struct completion completion; 3612 struct sk_buff *skb; 3613 bool tx_done; 3614 }; 3615 3616 struct rtw89_tx_skb_data { 3617 struct rtw89_tx_wait_info __rcu *wait; 3618 u8 tx_rpt_sn; 3619 u8 tx_pkt_cnt_lmt; 3620 u8 hci_priv[]; 3621 }; 3622 3623 #define RTW89_SCAN_NULL_TIMEOUT 30 3624 3625 #define RTW89_ROC_IDLE_TIMEOUT 500 3626 #define RTW89_ROC_TX_TIMEOUT 30 3627 enum rtw89_roc_state { 3628 RTW89_ROC_IDLE, 3629 RTW89_ROC_NORMAL, 3630 RTW89_ROC_MGMT, 3631 }; 3632 3633 struct rtw89_roc { 3634 struct ieee80211_channel chan; 3635 struct wiphy_delayed_work roc_work; 3636 enum ieee80211_roc_type type; 3637 enum rtw89_roc_state state; 3638 int duration; 3639 unsigned int link_id; 3640 }; 3641 3642 #define RTW89_P2P_MAX_NOA_NUM 2 3643 3644 struct rtw89_p2p_ie_head { 3645 u8 eid; 3646 u8 ie_len; 3647 u8 oui[3]; 3648 u8 oui_type; 3649 } __packed; 3650 3651 struct rtw89_noa_attr_head { 3652 u8 attr_type; 3653 __le16 attr_len; 3654 u8 index; 3655 u8 oppps_ctwindow; 3656 } __packed; 3657 3658 struct rtw89_p2p_noa_ie { 3659 struct rtw89_p2p_ie_head p2p_head; 3660 struct rtw89_noa_attr_head noa_head; 3661 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3662 } __packed; 3663 3664 struct rtw89_p2p_noa_setter { 3665 struct rtw89_p2p_noa_ie ie; 3666 u8 noa_count; 3667 u8 noa_index; 3668 }; 3669 3670 struct rtw89_ps_noa_once_handler { 3671 bool in_duration; 3672 u64 tsf_begin; 3673 u64 tsf_end; 3674 struct wiphy_delayed_work set_work; 3675 struct wiphy_delayed_work clr_work; 3676 }; 3677 3678 struct rtw89_vif_link { 3679 struct rtw89_vif *rtwvif; 3680 struct list_head dlink_schd; 3681 unsigned int link_id; 3682 3683 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3684 enum rtw89_chanctx_idx chanctx_idx; 3685 enum rtw89_reg_6ghz_power reg_6ghz_power; 3686 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3687 3688 u8 mac_id; 3689 u8 port; 3690 u8 mac_addr[ETH_ALEN]; 3691 u8 bssid[ETH_ALEN]; 3692 u8 phy_idx; 3693 u8 mac_idx; 3694 u8 net_type; 3695 u8 wifi_role; 3696 u8 self_role; 3697 u8 wmm; 3698 u8 bcn_hit_cond; 3699 u8 bcn_bw_idx; 3700 u8 hit_rule; 3701 u8 last_noa_nr; 3702 u64 sync_bcn_tsf; 3703 u64 last_sync_bcn_tsf; 3704 bool rand_tsf_done; 3705 bool trigger; 3706 bool lsig_txop; 3707 u8 tgt_ind; 3708 u8 frm_tgt_ind; 3709 bool wowlan_pattern; 3710 bool wowlan_uc; 3711 bool wowlan_magic; 3712 bool is_hesta; 3713 bool last_a_ctrl; 3714 bool dyn_tb_bedge_en; 3715 bool pre_pwr_diff_en; 3716 bool pwr_diff_en; 3717 u8 def_tri_idx; 3718 struct wiphy_work update_beacon_work; 3719 struct wiphy_delayed_work csa_beacon_work; 3720 struct rtw89_addr_cam_entry addr_cam; 3721 struct rtw89_bssid_cam_entry bssid_cam; 3722 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3723 struct rtw89_phy_rate_pattern rate_pattern; 3724 struct list_head general_pkt_list; 3725 struct rtw89_p2p_noa_setter p2p_noa; 3726 struct rtw89_ps_noa_once_handler noa_once; 3727 struct wiphy_delayed_work mcc_gc_detect_beacon_work; 3728 u8 detect_bcn_count; 3729 }; 3730 3731 enum rtw89_lv1_rcvy_step { 3732 RTW89_LV1_RCVY_STEP_1, 3733 RTW89_LV1_RCVY_STEP_2, 3734 }; 3735 3736 struct rtw89_hci_ops { 3737 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3738 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3739 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3740 void (*reset)(struct rtw89_dev *rtwdev); 3741 int (*start)(struct rtw89_dev *rtwdev); 3742 void (*stop)(struct rtw89_dev *rtwdev); 3743 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3744 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3745 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3746 3747 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3748 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3749 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3750 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3751 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3752 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3753 3754 u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr); 3755 3756 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3757 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3758 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3759 int (*deinit)(struct rtw89_dev *rtwdev); 3760 3761 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3762 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3763 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3764 int (*napi_poll)(struct napi_struct *napi, int budget); 3765 3766 /* Deal with locks inside recovery_start and recovery_complete callbacks 3767 * by hci instance, and handle things which need to consider under SER. 3768 * e.g. turn on/off interrupts except for the one for halt notification. 3769 */ 3770 void (*recovery_start)(struct rtw89_dev *rtwdev); 3771 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3772 3773 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3774 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3775 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3776 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3777 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3778 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3779 void (*disable_intr)(struct rtw89_dev *rtwdev); 3780 void (*enable_intr)(struct rtw89_dev *rtwdev); 3781 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3782 }; 3783 3784 struct rtw89_hci_info { 3785 const struct rtw89_hci_ops *ops; 3786 enum rtw89_hci_type type; 3787 enum rtw89_hci_dle_type dle_type; 3788 u32 rpwm_addr; 3789 u32 cpwm_addr; 3790 bool paused; 3791 bool tx_rpt_enabled; 3792 }; 3793 3794 struct rtw89_chip_ops { 3795 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3796 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3797 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3798 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3799 void (*bb_reset)(struct rtw89_dev *rtwdev, 3800 enum rtw89_phy_idx phy_idx); 3801 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3802 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3803 u32 addr, u32 mask); 3804 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3805 u32 addr, u32 mask, u32 data); 3806 void (*set_channel)(struct rtw89_dev *rtwdev, 3807 const struct rtw89_chan *chan, 3808 enum rtw89_mac_idx mac_idx, 3809 enum rtw89_phy_idx phy_idx); 3810 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3811 struct rtw89_channel_help_params *p, 3812 const struct rtw89_chan *chan, 3813 enum rtw89_mac_idx mac_idx, 3814 enum rtw89_phy_idx phy_idx); 3815 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3816 enum rtw89_efuse_block block); 3817 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3818 void (*fem_setup)(struct rtw89_dev *rtwdev); 3819 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3820 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3821 void (*rfk_init)(struct rtw89_dev *rtwdev); 3822 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3823 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3824 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3825 enum rtw89_phy_idx phy_idx, 3826 const struct rtw89_chan *chan); 3827 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3828 bool start); 3829 void (*rfk_track)(struct rtw89_dev *rtwdev); 3830 void (*power_trim)(struct rtw89_dev *rtwdev); 3831 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3832 const struct rtw89_chan *chan, 3833 enum rtw89_phy_idx phy_idx); 3834 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3835 enum rtw89_phy_idx phy_idx); 3836 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3837 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3838 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 3839 const struct rtw89_chan *chan); 3840 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3841 enum rtw89_phy_idx phy_idx); 3842 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3843 struct rtw89_rx_phy_ppdu *phy_ppdu, 3844 struct ieee80211_rx_status *status); 3845 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3846 struct rtw89_rx_phy_ppdu *phy_ppdu); 3847 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3848 struct rtw89_rx_desc_info *desc_info, 3849 struct ieee80211_rx_status *rx_status); 3850 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3851 enum rtw89_phy_idx phy_idx); 3852 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3853 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3854 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3855 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3856 enum rtw89_phy_idx phy_idx); 3857 void (*calc_rx_gain_normal)(struct rtw89_dev *rtwdev, 3858 const struct rtw89_chan *chan, 3859 enum rtw89_rf_path path, 3860 enum rtw89_phy_idx phy_idx, 3861 struct rtw89_phy_calc_efuse_gain *calc); 3862 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3863 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3864 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3865 struct rtw89_rx_desc_info *desc_info, 3866 u8 *data, u32 data_offset); 3867 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3868 struct rtw89_tx_desc_info *desc_info, 3869 void *txdesc); 3870 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3871 struct rtw89_tx_desc_info *desc_info, 3872 void *txdesc); 3873 u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel); 3874 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3875 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3876 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3877 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3878 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3879 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3880 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3881 struct rtw89_vif_link *rtwvif_link, 3882 struct rtw89_sta_link *rtwsta_link); 3883 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3884 struct rtw89_vif_link *rtwvif_link, 3885 struct rtw89_sta_link *rtwsta_link); 3886 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3887 struct rtw89_vif_link *rtwvif_link, 3888 struct rtw89_sta_link *rtwsta_link); 3889 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3890 struct rtw89_vif_link *rtwvif_link, 3891 struct rtw89_sta_link *rtwsta_link); 3892 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3893 struct rtw89_sta_link *rtwsta_link); 3894 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev, 3895 struct rtw89_vif_link *rtwvif_link, 3896 u16 punctured); 3897 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3898 struct rtw89_vif_link *rtwvif_link, 3899 struct rtw89_sta_link *rtwsta_link); 3900 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3901 struct rtw89_vif_link *rtwvif_link); 3902 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3903 struct rtw89_vif_link *rtwvif_link, 3904 struct rtw89_sta_link *rtwsta_link, 3905 bool valid, struct ieee80211_ampdu_params *params); 3906 int (*h2c_wow_cam_update)(struct rtw89_dev *rtwdev, 3907 struct rtw89_wow_cam_info *cam_info); 3908 3909 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3910 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3911 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3912 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3913 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3914 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3915 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3916 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3917 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3918 }; 3919 3920 enum rtw89_dma_ch { 3921 RTW89_DMA_ACH0 = 0, 3922 RTW89_DMA_ACH1 = 1, 3923 RTW89_DMA_ACH2 = 2, 3924 RTW89_DMA_ACH3 = 3, 3925 RTW89_DMA_ACH4 = 4, 3926 RTW89_DMA_ACH5 = 5, 3927 RTW89_DMA_ACH6 = 6, 3928 RTW89_DMA_ACH7 = 7, 3929 RTW89_DMA_B0MG = 8, 3930 RTW89_DMA_B0HI = 9, 3931 RTW89_DMA_B1MG = 10, 3932 RTW89_DMA_B1HI = 11, 3933 RTW89_DMA_H2C = 12, 3934 RTW89_DMA_CH_NUM = 13 3935 }; 3936 3937 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3938 3939 enum rtw89_mlo_dbcc_mode { 3940 MLO_DBCC_NOT_SUPPORT = 1, 3941 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3942 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3943 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3944 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3945 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3946 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3947 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3948 DBCC_LEGACY = 0xffffffff, 3949 }; 3950 3951 enum rtw89_scan_be_operation { 3952 RTW89_SCAN_OP_STOP, 3953 RTW89_SCAN_OP_START, 3954 RTW89_SCAN_OP_SETPARM, 3955 RTW89_SCAN_OP_GETRPT, 3956 RTW89_SCAN_OP_NUM 3957 }; 3958 3959 enum rtw89_scan_be_mode { 3960 RTW89_SCAN_MODE_SA, 3961 RTW89_SCAN_MODE_MACC, 3962 RTW89_SCAN_MODE_NUM 3963 }; 3964 3965 enum rtw89_scan_be_opmode { 3966 RTW89_SCAN_OPMODE_NONE, 3967 RTW89_SCAN_OPMODE_TBTT, 3968 RTW89_SCAN_OPMODE_INTV, 3969 RTW89_SCAN_OPMODE_CNT, 3970 RTW89_SCAN_OPMODE_NUM, 3971 }; 3972 3973 struct rtw89_scan_option { 3974 bool enable; 3975 bool target_ch_mode; 3976 u8 num_macc_role; 3977 u8 num_opch; 3978 u8 repeat; 3979 u16 norm_pd; 3980 u16 slow_pd; 3981 u16 norm_cy; 3982 u8 opch_end; 3983 u16 delay; /* in unit of ms */ 3984 u64 prohib_chan; 3985 enum rtw89_phy_idx band; 3986 enum rtw89_scan_be_operation operation; 3987 enum rtw89_scan_be_mode scan_mode; 3988 enum rtw89_mlo_dbcc_mode mlo_mode; 3989 }; 3990 3991 enum rtw89_qta_mode { 3992 RTW89_QTA_SCC, 3993 RTW89_QTA_DBCC, 3994 RTW89_QTA_DLFW, 3995 RTW89_QTA_WOW, 3996 3997 /* keep last */ 3998 RTW89_QTA_INVALID, 3999 }; 4000 4001 struct rtw89_hfc_ch_cfg { 4002 u16 min; 4003 u16 max; 4004 #define grp_0 0 4005 #define grp_1 1 4006 #define grp_num 2 4007 u8 grp; 4008 }; 4009 4010 struct rtw89_hfc_ch_info { 4011 u16 aval; 4012 u16 used; 4013 }; 4014 4015 struct rtw89_hfc_pub_cfg { 4016 u16 grp0; 4017 u16 grp1; 4018 u16 pub_max; 4019 u16 wp_thrd; 4020 }; 4021 4022 struct rtw89_hfc_pub_info { 4023 u16 g0_used; 4024 u16 g1_used; 4025 u16 g0_aval; 4026 u16 g1_aval; 4027 u16 pub_aval; 4028 u16 wp_aval; 4029 }; 4030 4031 struct rtw89_hfc_prec_cfg { 4032 u16 ch011_prec; 4033 u16 h2c_prec; 4034 u16 wp_ch07_prec; 4035 u16 wp_ch811_prec; 4036 u8 ch011_full_cond; 4037 u8 h2c_full_cond; 4038 u8 wp_ch07_full_cond; 4039 u8 wp_ch811_full_cond; 4040 /* for WiFi 7 chips after 8922D */ 4041 u16 ch011_full_page; 4042 u16 h2c_full_page; 4043 u16 wp_ch07_full_page; 4044 u16 wp_ch811_full_page; 4045 }; 4046 4047 struct rtw89_hfc_param { 4048 bool en; 4049 bool h2c_en; 4050 u8 mode; 4051 const struct rtw89_hfc_ch_cfg *ch_cfg; 4052 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 4053 struct rtw89_hfc_pub_cfg pub_cfg; 4054 struct rtw89_hfc_pub_info pub_info; 4055 struct rtw89_hfc_prec_cfg prec_cfg; 4056 }; 4057 4058 struct rtw89_hfc_param_ini { 4059 const struct rtw89_hfc_ch_cfg *ch_cfg; 4060 const struct rtw89_hfc_pub_cfg *pub_cfg; 4061 const struct rtw89_hfc_prec_cfg *prec_cfg; 4062 u8 mode; 4063 }; 4064 4065 struct rtw89_dle_size { 4066 u16 pge_size; 4067 u16 lnk_pge_num; 4068 u16 unlnk_pge_num; 4069 /* for WiFi 7 chips below (suffix v1) */ 4070 u32 srt_ofst; 4071 }; 4072 4073 struct rtw89_wde_quota { 4074 u16 hif; 4075 u16 wcpu; 4076 /* unused dcpu isn't listed */ 4077 u16 pkt_in; 4078 u16 cpu_io; 4079 }; 4080 4081 struct rtw89_ple_quota { 4082 u16 cma0_tx; 4083 u16 cma1_tx; 4084 u16 c2h; 4085 u16 h2c; 4086 u16 wcpu; 4087 u16 mpdu_proc; 4088 u16 cma0_dma; 4089 u16 cma1_dma; 4090 u16 bb_rpt; 4091 u16 wd_rel; 4092 u16 cpu_io; 4093 u16 tx_rpt; 4094 /* for WiFi 7 chips below (suffix v1) */ 4095 u16 h2d; 4096 /* for WiFi 7 chips after 8922D (suffix v2) */ 4097 u16 snrpt; 4098 }; 4099 4100 struct rtw89_rsvd_quota { 4101 u16 mpdu_info_tbl; 4102 u16 b0_csi; 4103 u16 b1_csi; 4104 u16 b0_lmr; 4105 u16 b1_lmr; 4106 u16 b0_ftm; 4107 u16 b1_ftm; 4108 u16 b0_smr; 4109 u16 b1_smr; 4110 u16 others; 4111 }; 4112 4113 struct rtw89_dle_rsvd_size { 4114 u32 srt_ofst; 4115 u32 size; 4116 }; 4117 4118 struct rtw89_dle_input { 4119 u32 tx_ampdu_num_b0; 4120 u32 tx_ampdu_num_b1; 4121 u32 tx_amsdu_size; /* unit: KB */ 4122 u32 h2c_max_size; 4123 u32 rx_amsdu_size; /* unit: KB */ 4124 u32 c2h_max_size; 4125 u32 mpdu_info_tbl_b0; 4126 u32 mpdu_info_tbl_b1; 4127 }; 4128 4129 struct rtw89_dle_mem { 4130 enum rtw89_qta_mode mode; 4131 const struct rtw89_dle_size *wde_size; 4132 const struct rtw89_dle_size *ple_size; 4133 const struct rtw89_wde_quota *wde_min_qt; 4134 const struct rtw89_wde_quota *wde_max_qt; 4135 const struct rtw89_ple_quota *ple_min_qt; 4136 const struct rtw89_ple_quota *ple_max_qt; 4137 /* for WiFi 7 chips below */ 4138 const struct rtw89_rsvd_quota *rsvd_qt; 4139 const struct rtw89_dle_rsvd_size *rsvd0_size; 4140 const struct rtw89_dle_rsvd_size *rsvd1_size; 4141 /* for WiFi 7 chips after 8922D */ 4142 const struct rtw89_dle_input *dle_input; 4143 }; 4144 4145 struct rtw89_reg_def { 4146 u32 addr; 4147 u32 mask; 4148 }; 4149 4150 struct rtw89_reg2_def { 4151 u32 addr; 4152 u32 data; 4153 }; 4154 4155 struct rtw89_reg3_def { 4156 u32 addr; 4157 u32 mask; 4158 u32 data; 4159 }; 4160 4161 struct rtw89_reg5_def { 4162 u8 flag; /* recognized by parsers */ 4163 u8 path; 4164 u32 addr; 4165 u32 mask; 4166 u32 data; 4167 }; 4168 4169 struct rtw89_reg_imr { 4170 u32 addr; 4171 u32 clr; 4172 u32 set; 4173 }; 4174 4175 #define RTW89_MODULE_FWNAME_PLACEHOLDER_0 0, 4176 #define __RTW89_GEN_MODULE_FWNAME_FMT(placeholder_or_ignored, strfmt) \ 4177 __take_second_arg(placeholder_or_ignored, strfmt) 4178 #define RTW89_GEN_MODULE_FWNAME_FMT(maxfmt) \ 4179 __RTW89_GEN_MODULE_FWNAME_FMT(RTW89_MODULE_FWNAME_PLACEHOLDER_ ## maxfmt, \ 4180 "-" __stringify(maxfmt)) 4181 #define RTW89_GEN_MODULE_FWNAME(basename, maxformat) \ 4182 basename RTW89_GEN_MODULE_FWNAME_FMT(maxformat) ".bin" 4183 4184 struct rtw89_fw_def { 4185 const char *fw_basename; 4186 u8 fw_format_max; 4187 u16 fw_b_aid; 4188 }; 4189 4190 struct rtw89_phy_table { 4191 const struct rtw89_reg2_def *regs; 4192 u32 n_regs; 4193 enum rtw89_rf_path rf_path; 4194 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 4195 enum rtw89_rf_path rf_path, void *data); 4196 }; 4197 4198 struct rtw89_txpwr_table { 4199 const void *data; 4200 u32 size; 4201 void (*load)(struct rtw89_dev *rtwdev, 4202 const struct rtw89_txpwr_table *tbl); 4203 }; 4204 4205 struct rtw89_txpwr_rule_2ghz { 4206 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4207 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4208 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4209 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4210 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4211 }; 4212 4213 struct rtw89_txpwr_rule_5ghz { 4214 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4215 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4216 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4217 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4218 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4219 }; 4220 4221 struct rtw89_txpwr_rule_6ghz { 4222 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4223 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4224 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4225 [RTW89_6G_CH_NUM]; 4226 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4227 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4228 [RTW89_6G_CH_NUM]; 4229 }; 4230 4231 struct rtw89_tx_shape { 4232 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4233 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4234 }; 4235 4236 struct rtw89_rfe_parms { 4237 const struct rtw89_txpwr_table *byr_tbl; 4238 struct rtw89_txpwr_rule_2ghz rule_2ghz; 4239 struct rtw89_txpwr_rule_5ghz rule_5ghz; 4240 struct rtw89_txpwr_rule_6ghz rule_6ghz; 4241 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 4242 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 4243 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 4244 struct rtw89_tx_shape tx_shape; 4245 bool has_da; 4246 }; 4247 4248 struct rtw89_rfe_parms_conf { 4249 const struct rtw89_rfe_parms *rfe_parms; 4250 u8 rfe_type; 4251 }; 4252 4253 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 4254 4255 struct rtw89_txpwr_conf { 4256 u8 rfe_type; 4257 u8 ent_sz; 4258 u32 num_ents; 4259 const void *data; 4260 }; 4261 4262 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4263 const struct rtw89_txpwr_conf *conf) 4264 { 4265 u8 valid_size = min(size, conf->ent_sz); 4266 4267 memcpy(entry, cursor, valid_size); 4268 return true; 4269 } 4270 4271 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4272 4273 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4274 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4275 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4276 (cursor) += (conf)->ent_sz) \ 4277 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4278 4279 struct rtw89_txpwr_byrate_data { 4280 struct rtw89_txpwr_conf conf; 4281 struct rtw89_txpwr_table tbl; 4282 }; 4283 4284 struct rtw89_txpwr_lmt_2ghz_data { 4285 struct rtw89_txpwr_conf conf; 4286 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4287 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4288 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4289 }; 4290 4291 struct rtw89_txpwr_lmt_5ghz_data { 4292 struct rtw89_txpwr_conf conf; 4293 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4294 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4295 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4296 }; 4297 4298 struct rtw89_txpwr_lmt_6ghz_data { 4299 struct rtw89_txpwr_conf conf; 4300 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4301 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4302 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4303 [RTW89_6G_CH_NUM]; 4304 }; 4305 4306 struct rtw89_txpwr_lmt_ru_2ghz_data { 4307 struct rtw89_txpwr_conf conf; 4308 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4309 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4310 }; 4311 4312 struct rtw89_txpwr_lmt_ru_5ghz_data { 4313 struct rtw89_txpwr_conf conf; 4314 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4315 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4316 }; 4317 4318 struct rtw89_txpwr_lmt_ru_6ghz_data { 4319 struct rtw89_txpwr_conf conf; 4320 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4321 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4322 [RTW89_6G_CH_NUM]; 4323 }; 4324 4325 struct rtw89_tx_shape_lmt_data { 4326 struct rtw89_txpwr_conf conf; 4327 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4328 }; 4329 4330 struct rtw89_tx_shape_lmt_ru_data { 4331 struct rtw89_txpwr_conf conf; 4332 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4333 }; 4334 4335 struct rtw89_rfe_data { 4336 struct rtw89_txpwr_byrate_data byrate; 4337 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4338 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4339 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4340 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 4341 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 4342 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 4343 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4344 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4345 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4346 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 4347 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 4348 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 4349 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4350 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4351 struct rtw89_rfe_parms rfe_parms; 4352 }; 4353 4354 struct rtw89_page_regs { 4355 u32 hci_fc_ctrl; 4356 u32 ch_page_ctrl; 4357 u32 ach_page_ctrl; 4358 u32 ach_page_info; 4359 u32 pub_page_info3; 4360 u32 pub_page_ctrl1; 4361 u32 pub_page_ctrl2; 4362 u32 pub_page_info1; 4363 u32 pub_page_info2; 4364 u32 wp_page_ctrl1; 4365 u32 wp_page_ctrl2; 4366 u32 wp_page_info1; 4367 }; 4368 4369 struct rtw89_imr_info { 4370 u32 wdrls_imr_set; 4371 u32 wsec_imr_reg; 4372 u32 wsec_imr_set; 4373 u32 mpdu_tx_imr_set; 4374 u32 mpdu_rx_imr_set; 4375 u32 sta_sch_imr_set; 4376 u32 txpktctl_imr_b0_reg; 4377 u32 txpktctl_imr_b0_clr; 4378 u32 txpktctl_imr_b0_set; 4379 u32 txpktctl_imr_b1_reg; 4380 u32 txpktctl_imr_b1_clr; 4381 u32 txpktctl_imr_b1_set; 4382 u32 wde_imr_clr; 4383 u32 wde_imr_set; 4384 u32 ple_imr_clr; 4385 u32 ple_imr_set; 4386 u32 host_disp_imr_clr; 4387 u32 host_disp_imr_set; 4388 u32 cpu_disp_imr_clr; 4389 u32 cpu_disp_imr_set; 4390 u32 other_disp_imr_clr; 4391 u32 other_disp_imr_set; 4392 u32 bbrpt_com_err_imr_reg; 4393 u32 bbrpt_chinfo_err_imr_reg; 4394 u32 bbrpt_err_imr_set; 4395 u32 bbrpt_dfs_err_imr_reg; 4396 u32 ptcl_imr_clr; 4397 u32 ptcl_imr_set; 4398 u32 cdma_imr_0_reg; 4399 u32 cdma_imr_0_clr; 4400 u32 cdma_imr_0_set; 4401 u32 cdma_imr_1_reg; 4402 u32 cdma_imr_1_clr; 4403 u32 cdma_imr_1_set; 4404 u32 phy_intf_imr_reg; 4405 u32 phy_intf_imr_clr; 4406 u32 phy_intf_imr_set; 4407 u32 rmac_imr_reg; 4408 u32 rmac_imr_clr; 4409 u32 rmac_imr_set; 4410 u32 tmac_imr_reg; 4411 u32 tmac_imr_clr; 4412 u32 tmac_imr_set; 4413 }; 4414 4415 struct rtw89_imr_table { 4416 const struct rtw89_reg_imr *regs; 4417 u32 n_regs; 4418 }; 4419 4420 struct rtw89_xtal_info { 4421 u32 xcap_reg; 4422 u32 sc_xo_mask; 4423 u32 sc_xi_mask; 4424 }; 4425 4426 struct rtw89_rrsr_cfgs { 4427 struct rtw89_reg3_def ref_rate; 4428 struct rtw89_reg3_def rsc; 4429 }; 4430 4431 struct rtw89_rfkill_regs { 4432 struct rtw89_reg3_def pinmux; 4433 struct rtw89_reg3_def mode; 4434 }; 4435 4436 struct rtw89_sb_regs { 4437 struct { 4438 u32 cfg; 4439 u32 get; 4440 } n[2]; 4441 }; 4442 4443 struct rtw89_dig_regs { 4444 u32 seg0_pd_reg; 4445 u32 pd_lower_bound_mask; 4446 u32 pd_spatial_reuse_en; 4447 u32 bmode_pd_reg; 4448 u32 bmode_cca_rssi_limit_en; 4449 u32 bmode_pd_lower_bound_reg; 4450 u32 bmode_rssi_nocca_low_th_mask; 4451 struct rtw89_reg_def p0_lna_init; 4452 struct rtw89_reg_def p1_lna_init; 4453 struct rtw89_reg_def p0_tia_init; 4454 struct rtw89_reg_def p1_tia_init; 4455 struct rtw89_reg_def p0_rxb_init; 4456 struct rtw89_reg_def p1_rxb_init; 4457 struct rtw89_reg_def p0_p20_pagcugc_en; 4458 struct rtw89_reg_def p0_s20_pagcugc_en; 4459 struct rtw89_reg_def p1_p20_pagcugc_en; 4460 struct rtw89_reg_def p1_s20_pagcugc_en; 4461 }; 4462 4463 struct rtw89_edcca_regs { 4464 u32 edcca_level; 4465 u32 edcca_mask; 4466 u32 edcca_p_mask; 4467 u32 ppdu_level; 4468 u32 ppdu_mask; 4469 struct rtw89_edcca_p_regs { 4470 u32 rpt_a; 4471 u32 rpt_b; 4472 u32 rpt_sel; 4473 u32 rpt_sel_mask; 4474 } p[RTW89_PHY_NUM]; 4475 u32 rpt_sel_be; 4476 u32 rpt_sel_be_mask; 4477 u32 tx_collision_t2r_st; 4478 u32 tx_collision_t2r_st_mask; 4479 }; 4480 4481 struct rtw89_phy_ul_tb_info { 4482 bool dyn_tb_tri_en; 4483 u8 def_if_bandedge; 4484 }; 4485 4486 struct rtw89_antdiv_stats { 4487 struct ewma_rssi cck_rssi_avg; 4488 struct ewma_rssi ofdm_rssi_avg; 4489 struct ewma_rssi non_legacy_rssi_avg; 4490 u16 pkt_cnt_cck; 4491 u16 pkt_cnt_ofdm; 4492 u16 pkt_cnt_non_legacy; 4493 u32 evm; 4494 }; 4495 4496 struct rtw89_antdiv_info { 4497 struct rtw89_antdiv_stats target_stats; 4498 struct rtw89_antdiv_stats main_stats; 4499 struct rtw89_antdiv_stats aux_stats; 4500 u8 training_count; 4501 u8 rssi_pre; 4502 bool get_stats; 4503 }; 4504 4505 enum rtw89_chanctx_state { 4506 RTW89_CHANCTX_STATE_MCC_START, 4507 RTW89_CHANCTX_STATE_MCC_STOP, 4508 }; 4509 4510 enum rtw89_chanctx_callbacks { 4511 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4512 RTW89_CHANCTX_CALLBACK_RFK, 4513 RTW89_CHANCTX_CALLBACK_TAS, 4514 4515 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4516 }; 4517 4518 struct rtw89_chanctx_listener { 4519 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4520 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4521 }; 4522 4523 #define RTW89_NHM_TH_NUM 11 4524 #define RTW89_NHM_RPT_NUM 12 4525 4526 struct rtw89_chip_info { 4527 enum rtw89_core_chip_id chip_id; 4528 enum rtw89_chip_gen chip_gen; 4529 const struct rtw89_chip_ops *ops; 4530 const struct rtw89_mac_gen_def *mac_def; 4531 const struct rtw89_phy_gen_def *phy_def; 4532 struct rtw89_fw_def fw_def; 4533 bool try_ce_fw; 4534 u8 bbmcu_nr; 4535 u32 needed_fw_elms; 4536 const struct rtw89_fw_blacklist *fw_blacklist; 4537 u32 fifo_size; 4538 bool small_fifo_size; 4539 u32 dle_scc_rsvd_size; 4540 u16 max_amsdu_limit; 4541 u16 max_vht_mpdu_cap; 4542 u16 max_eht_mpdu_cap; 4543 u16 max_tx_agg_num; 4544 u16 max_rx_agg_num; 4545 bool dis_2g_40m_ul_ofdma; 4546 u32 rsvd_ple_ofst; 4547 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM]; 4548 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM]; 4549 u8 wde_qempty_acq_grpnum; 4550 u8 wde_qempty_mgq_grpsel; 4551 u32 rf_base_addr[2]; 4552 u8 thermal_th[2]; 4553 u8 support_macid_num; 4554 u8 support_link_num; 4555 u8 support_chanctx_num; 4556 u8 support_bands; 4557 u16 support_bandwidths; 4558 bool support_unii4; 4559 bool support_rnr; 4560 bool support_ant_gain; 4561 bool support_tas; 4562 bool support_sar_by_ant; 4563 bool support_noise; 4564 bool ul_tb_waveform_ctrl; 4565 bool ul_tb_pwr_diff; 4566 bool rx_freq_from_ie; 4567 bool hw_sec_hdr; 4568 bool hw_mgmt_tx_encrypt; 4569 bool hw_tkip_crypto; 4570 bool hw_mlo_bmc_crypto; 4571 u8 rf_path_num; 4572 u8 tx_nss; 4573 u8 rx_nss; 4574 u8 acam_num; 4575 u8 bcam_num; 4576 u8 scam_num; 4577 u8 bacam_num; 4578 u8 bacam_dynamic_num; 4579 enum rtw89_bacam_ver bacam_ver; 4580 u8 addrcam_ver; 4581 u8 ppdu_max_usr; 4582 4583 u8 sec_ctrl_efuse_size; 4584 u32 physical_efuse_size; 4585 u32 logical_efuse_size; 4586 u32 limit_efuse_size; 4587 u32 dav_phy_efuse_size; 4588 u32 dav_log_efuse_size; 4589 u32 phycap_addr; 4590 u32 phycap_size; 4591 const struct rtw89_efuse_block_cfg *efuse_blocks; 4592 4593 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4594 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4595 const struct rtw89_phy_table *bb_table; 4596 const struct rtw89_phy_table *bb_gain_table; 4597 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4598 const struct rtw89_phy_table *nctl_table; 4599 const struct rtw89_rfk_tbl *nctl_post_table; 4600 const struct rtw89_phy_dig_gain_table *dig_table; 4601 const struct rtw89_dig_regs *dig_regs; 4602 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4603 4604 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4605 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4606 const struct rtw89_rfe_parms *dflt_parms; 4607 const struct rtw89_chanctx_listener *chanctx_listener; 4608 4609 u8 txpwr_factor_bb; 4610 u8 txpwr_factor_rf; 4611 u8 txpwr_factor_mac; 4612 4613 u32 para_ver; 4614 u32 wlcx_desired; 4615 u8 scbd; 4616 u8 mailbox; 4617 4618 u8 afh_guard_ch; 4619 const u8 *wl_rssi_thres; 4620 const u8 *bt_rssi_thres; 4621 u8 rssi_tol; 4622 4623 u8 mon_reg_num; 4624 const struct rtw89_btc_fbtc_mreg *mon_reg; 4625 u8 rf_para_ulink_num; 4626 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4627 u8 rf_para_dlink_num; 4628 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4629 const struct rtw89_btc_rf_trx_para_v9 *rf_para_ulink_v9; 4630 const struct rtw89_btc_rf_trx_para_v9 *rf_para_dlink_v9; 4631 u8 rf_para_ulink_num_v9; 4632 u8 rf_para_dlink_num_v9; 4633 u8 ps_mode_supported; 4634 u8 low_power_hci_modes; 4635 4636 u32 h2c_cctl_func_id; 4637 u32 hci_func_en_addr; 4638 u32 h2c_desc_size; 4639 u32 txwd_body_size; 4640 u32 txwd_info_size; 4641 u32 h2c_ctrl_reg; 4642 const u32 *h2c_regs; 4643 struct rtw89_reg_def h2c_counter_reg; 4644 u32 c2h_ctrl_reg; 4645 const u32 *c2h_regs; 4646 struct rtw89_reg_def c2h_counter_reg; 4647 const struct rtw89_page_regs *page_regs; 4648 const u32 *wow_reason_reg; 4649 bool cfo_src_fd; 4650 bool cfo_hw_comp; 4651 const struct rtw89_reg_def *dcfo_comp; 4652 u8 dcfo_comp_sft; 4653 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM]; 4654 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM]; 4655 const struct rtw89_imr_info *imr_info; 4656 const struct rtw89_imr_table *imr_dmac_table; 4657 const struct rtw89_imr_table *imr_cmac_table; 4658 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4659 struct rtw89_reg_def bss_clr_vld; 4660 u32 bss_clr_map_reg; 4661 const struct rtw89_rfkill_regs *rfkill_init; 4662 struct rtw89_reg_def rfkill_get; 4663 struct rtw89_sb_regs btc_sb; 4664 u32 dma_ch_mask; 4665 const struct rtw89_edcca_regs *edcca_regs; 4666 const struct wiphy_wowlan_support *wowlan_stub; 4667 const struct rtw89_xtal_info *xtal_info; 4668 unsigned long default_quirks; /* bitmap of rtw89_quirks */ 4669 }; 4670 4671 struct rtw89_chip_variant { 4672 bool no_mcs_12_13: 1; 4673 u32 fw_min_ver_code; 4674 const struct rtw89_fw_def *fw_def_override; 4675 }; 4676 4677 union rtw89_bus_info { 4678 const struct rtw89_pci_info *pci; 4679 const struct rtw89_usb_info *usb; 4680 }; 4681 4682 struct rtw89_driver_info { 4683 const struct rtw89_chip_info *chip; 4684 const struct rtw89_chip_variant *variant; 4685 const struct dmi_system_id *quirks; 4686 union rtw89_bus_info bus; 4687 }; 4688 4689 enum rtw89_hcifc_mode { 4690 RTW89_HCIFC_POH = 0, 4691 RTW89_HCIFC_STF = 1, 4692 RTW89_HCIFC_SDIO = 2, 4693 4694 /* keep last */ 4695 RTW89_HCIFC_MODE_INVALID, 4696 }; 4697 4698 struct rtw89_dle_info { 4699 const struct rtw89_rsvd_quota *rsvd_qt; 4700 const struct rtw89_dle_input *dle_input; 4701 enum rtw89_qta_mode qta_mode; 4702 u16 ple_pg_size; 4703 u16 ple_free_pg; 4704 u16 c0_rx_qta; 4705 u16 c1_rx_qta; 4706 }; 4707 4708 enum rtw89_host_rpr_mode { 4709 RTW89_RPR_MODE_POH = 0, 4710 RTW89_RPR_MODE_STF 4711 }; 4712 4713 #define RTW89_COMPLETION_BUF_SIZE 40 4714 #define RTW89_WAIT_COND_IDLE UINT_MAX 4715 4716 struct rtw89_completion_data { 4717 bool err; 4718 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4719 }; 4720 4721 struct rtw89_wait_response { 4722 struct rcu_head rcu_head; 4723 struct completion completion; 4724 struct rtw89_completion_data data; 4725 }; 4726 4727 struct rtw89_wait_info { 4728 atomic_t cond; 4729 struct rtw89_completion_data data; 4730 struct rtw89_wait_response __rcu *resp; 4731 }; 4732 4733 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4734 4735 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4736 { 4737 rcu_assign_pointer(wait->resp, NULL); 4738 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4739 } 4740 4741 struct rtw89_mac_info { 4742 struct rtw89_dle_info dle_info; 4743 struct rtw89_hfc_param hfc_param; 4744 enum rtw89_qta_mode qta_mode; 4745 u8 rpwm_seq_num; 4746 u8 cpwm_seq_num; 4747 4748 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4749 struct rtw89_wait_info fw_ofld_wait; 4750 /* see RTW89_PS_WAIT_COND series for wait condition */ 4751 struct rtw89_wait_info ps_wait; 4752 }; 4753 4754 enum rtw89_fwdl_check_type { 4755 RTW89_FWDL_CHECK_FREERTOS_DONE, 4756 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4757 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4758 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4759 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4760 }; 4761 4762 enum rtw89_fw_type { 4763 RTW89_FW_NORMAL = 1, 4764 RTW89_FW_WOWLAN = 3, 4765 RTW89_FW_NORMAL_CE = 5, 4766 RTW89_FW_NORMAL_B = 14, 4767 RTW89_FW_WOWLAN_B = 15, 4768 RTW89_FW_BBMCU0 = 64, 4769 RTW89_FW_BBMCU1 = 65, 4770 RTW89_FW_LOGFMT = 255, 4771 }; 4772 4773 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \ 4774 RTW89_FW_FEATURE_##_grp##_MIN, \ 4775 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \ 4776 _features \ 4777 __RTW89_FW_FEATURE_##_grp##_E, \ 4778 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1 4779 4780 enum rtw89_fw_feature { 4781 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4782 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4783 RTW89_FW_FEATURE_TX_WAKE, 4784 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER, 4785 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0, 4786 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1, 4787 ), 4788 RTW89_FW_FEATURE_NO_PACKET_DROP, 4789 RTW89_FW_FEATURE_NO_DEEP_PS, 4790 RTW89_FW_FEATURE_NO_LPS_PG, 4791 RTW89_FW_FEATURE_BEACON_FILTER, 4792 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4793 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4794 RTW89_FW_FEATURE_WOW_REASON_V1, 4795 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, 4796 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4797 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4798 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V2, 4799 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V3, 4800 ), 4801 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC, 4802 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V0, 4803 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V1, 4804 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V2, 4805 ), 4806 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4807 RTW89_FW_FEATURE_RFK_IQK_V0, 4808 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4809 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4810 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4811 RTW89_FW_FEATURE_LPS_CH_INFO, 4812 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4813 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4814 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 4815 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 4816 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 4817 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 4818 RTW89_FW_FEATURE_BEACON_TRACKING, 4819 RTW89_FW_FEATURE_ADDR_CAM_V0, 4820 RTW89_FW_FEATURE_SER_L1_BY_EVENT, 4821 RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C, 4822 RTW89_FW_FEATURE_LPS_ML_INFO_V1, 4823 RTW89_FW_FEATURE_SER_POST_RECOVER_DMAC, 4824 4825 NUM_OF_RTW89_FW_FEATURES, 4826 }; 4827 4828 struct rtw89_fw_suit { 4829 enum rtw89_fw_type type; 4830 const u8 *data; 4831 u32 size; 4832 u8 major_ver; 4833 u8 minor_ver; 4834 u8 sub_ver; 4835 u8 sub_idex; 4836 u16 build_year; 4837 u16 build_mon; 4838 u16 build_date; 4839 u16 build_hour; 4840 u16 build_min; 4841 u8 cmd_ver; 4842 u8 hdr_ver; 4843 u32 commitid; 4844 }; 4845 4846 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4847 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4848 #define RTW89_FW_SUIT_VER_CODE(s) \ 4849 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4850 4851 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4852 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4853 (mfw_hdr)->ver.minor, \ 4854 (mfw_hdr)->ver.sub, \ 4855 (mfw_hdr)->ver.idx) 4856 4857 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4858 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4859 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4860 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4861 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4862 4863 struct rtw89_fw_req_info { 4864 const struct firmware *firmware; 4865 struct completion completion; 4866 }; 4867 4868 struct rtw89_fw_log { 4869 struct rtw89_fw_suit suit; 4870 bool enable; 4871 u32 last_fmt_id; 4872 u32 fmt_count; 4873 const __le32 *fmt_ids; 4874 const char *(*fmts)[]; 4875 }; 4876 4877 struct rtw89_fw_elm_info { 4878 struct rtw89_phy_table *bb_tbl; 4879 struct rtw89_phy_table *bb_gain; 4880 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4881 struct rtw89_phy_table *rf_nctl; 4882 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4883 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4884 const struct rtw89_regd_data *regd; 4885 const struct rtw89_fw_element_hdr *afe; 4886 const struct rtw89_fw_element_hdr *diag_mac; 4887 const struct rtw89_fw_element_hdr *tx_comp; 4888 }; 4889 4890 enum rtw89_fw_mss_dev_type { 4891 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4892 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4893 }; 4894 4895 struct rtw89_fw_secure { 4896 bool secure_boot: 1; 4897 bool can_mss_v1: 1; 4898 bool can_mss_v0: 1; 4899 u32 sb_sel_mgn; 4900 u8 mss_dev_type; 4901 u8 mss_cust_idx; 4902 u8 mss_key_num; 4903 u8 mss_idx; /* v0 */ 4904 }; 4905 4906 struct rtw89_fw_info { 4907 struct rtw89_fw_req_info req; 4908 int fw_format; 4909 u8 h2c_seq; 4910 u8 rec_seq; 4911 u8 h2c_counter; 4912 u8 c2h_counter; 4913 struct rtw89_fw_suit normal; 4914 struct rtw89_fw_suit wowlan; 4915 struct rtw89_fw_suit bbmcu0; 4916 struct rtw89_fw_suit bbmcu1; 4917 struct rtw89_fw_log log; 4918 struct rtw89_fw_elm_info elm_info; 4919 struct rtw89_fw_secure sec; 4920 4921 DECLARE_BITMAP(feature_map, NUM_OF_RTW89_FW_FEATURES); 4922 }; 4923 4924 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4925 test_bit(RTW89_FW_FEATURE_ ## _feat, (_fw)->feature_map) 4926 4927 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \ 4928 ({ \ 4929 unsigned int bit = find_next_bit((_fw)->feature_map, \ 4930 NUM_OF_RTW89_FW_FEATURES, \ 4931 RTW89_FW_FEATURE_ ## _grp ## _MIN); \ 4932 bit <= RTW89_FW_FEATURE_ ## _grp ## _MAX; \ 4933 }) 4934 4935 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4936 set_bit(_fw_feature, (_fw)->feature_map) 4937 4938 #define RTW89_CLR_FW_FEATURE(_fw_feature, _fw) \ 4939 clear_bit(_fw_feature, (_fw)->feature_map) 4940 4941 struct rtw89_cam_info { 4942 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4943 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4944 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4945 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4946 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4947 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4948 }; 4949 4950 enum rtw89_sar_sources { 4951 RTW89_SAR_SOURCE_NONE, 4952 RTW89_SAR_SOURCE_COMMON, 4953 RTW89_SAR_SOURCE_ACPI, 4954 4955 RTW89_SAR_SOURCE_NR, 4956 }; 4957 4958 enum rtw89_sar_subband { 4959 RTW89_SAR_2GHZ_SUBBAND, 4960 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4961 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4962 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4963 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4964 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4965 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4966 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4967 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4968 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4969 4970 RTW89_SAR_SUBBAND_NR, 4971 }; 4972 4973 struct rtw89_sar_cfg_common { 4974 bool set[RTW89_SAR_SUBBAND_NR]; 4975 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4976 }; 4977 4978 enum rtw89_acpi_sar_subband { 4979 RTW89_ACPI_SAR_2GHZ_SUBBAND, 4980 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 4981 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 4982 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4983 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4984 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4985 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4986 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4987 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4988 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4989 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4990 4991 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 4992 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 4993 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 4994 }; 4995 4996 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 4997 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 4998 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 4999 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 5000 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 5001 5002 struct rtw89_sar_entry_from_acpi { 5003 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 5004 }; 5005 5006 struct rtw89_sar_table_from_acpi { 5007 /* If this table is active, must fill all fields according to either 5008 * configuration in BIOS or some default values for SAR to work well. 5009 */ 5010 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 5011 }; 5012 5013 struct rtw89_sar_indicator_from_acpi { 5014 bool enable_sync; 5015 unsigned int fields; 5016 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 5017 5018 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 5019 * Not design with pointers since addresses will be invalid after 5020 * sync content with local container instance. 5021 */ 5022 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 5023 }; 5024 5025 struct rtw89_sar_cfg_acpi { 5026 u8 downgrade_2tx; 5027 unsigned int valid_num; 5028 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 5029 struct rtw89_sar_indicator_from_acpi indicator; 5030 }; 5031 5032 struct rtw89_sar_info { 5033 /* used to decide how to access SAR cfg union */ 5034 enum rtw89_sar_sources src; 5035 5036 /* reserved for different knids of SAR cfg struct. 5037 * supposed that a single cfg struct cannot handle various SAR sources. 5038 */ 5039 union { 5040 struct rtw89_sar_cfg_common cfg_common; 5041 struct rtw89_sar_cfg_acpi cfg_acpi; 5042 }; 5043 }; 5044 5045 enum rtw89_ant_gain_subband { 5046 RTW89_ANT_GAIN_2GHZ_SUBBAND, 5047 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 5048 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 5049 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 5050 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 5051 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 5052 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 5053 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 5054 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 5055 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 5056 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 5057 5058 RTW89_ANT_GAIN_SUBBAND_NR, 5059 }; 5060 5061 enum rtw89_ant_gain_domain_type { 5062 RTW89_ANT_GAIN_ETSI = 0, 5063 5064 RTW89_ANT_GAIN_DOMAIN_NUM, 5065 }; 5066 5067 #define RTW89_ANT_GAIN_CHAIN_NUM 2 5068 struct rtw89_ant_gain_info { 5069 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 5070 u32 regd_enabled; 5071 bool block_country; 5072 }; 5073 5074 struct rtw89_6ghz_span { 5075 enum rtw89_sar_subband sar_subband_low; 5076 enum rtw89_sar_subband sar_subband_high; 5077 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 5078 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 5079 enum rtw89_ant_gain_subband ant_gain_subband_low; 5080 enum rtw89_ant_gain_subband ant_gain_subband_high; 5081 }; 5082 5083 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 5084 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 5085 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 5086 5087 enum rtw89_tas_state { 5088 RTW89_TAS_STATE_DPR_OFF, 5089 RTW89_TAS_STATE_DPR_ON, 5090 RTW89_TAS_STATE_STATIC_SAR, 5091 }; 5092 5093 #define RTW89_TAS_TX_RATIO_WINDOW 6 5094 #define RTW89_TAS_TXPWR_WINDOW 180 5095 struct rtw89_tas_info { 5096 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 5097 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 5098 u8 enabled_countries; 5099 u8 txpwr_head_idx; 5100 u8 txpwr_tail_idx; 5101 u8 tx_ratio_idx; 5102 u16 total_tx_ratio; 5103 u64 total_txpwr; 5104 u64 instant_txpwr; 5105 u32 window_size; 5106 s8 dpr_on_threshold; 5107 s8 dpr_off_threshold; 5108 enum rtw89_tas_state backup_state; 5109 enum rtw89_tas_state state; 5110 bool keep_history; 5111 bool block_regd; 5112 bool enable; 5113 bool pause; 5114 }; 5115 5116 struct rtw89_chanctx_cfg { 5117 enum rtw89_chanctx_idx idx; 5118 int ref_count; 5119 }; 5120 5121 enum rtw89_chanctx_changes { 5122 RTW89_CHANCTX_REMOTE_STA_CHANGE, 5123 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 5124 RTW89_CHANCTX_P2P_PS_CHANGE, 5125 RTW89_CHANCTX_BT_SLOT_CHANGE, 5126 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 5127 5128 NUM_OF_RTW89_CHANCTX_CHANGES, 5129 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 5130 }; 5131 5132 enum rtw89_entity_mode { 5133 RTW89_ENTITY_MODE_SCC_OR_SMLD, 5134 RTW89_ENTITY_MODE_MCC_PREPARE, 5135 RTW89_ENTITY_MODE_MCC, 5136 5137 NUM_OF_RTW89_ENTITY_MODE, 5138 RTW89_ENTITY_MODE_INVALID = -EINVAL, 5139 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 5140 }; 5141 5142 #define RTW89_MAX_INTERFACE_NUM 2 5143 5144 /* only valid when running with chanctx_ops */ 5145 struct rtw89_entity_mgnt { 5146 struct list_head active_list; 5147 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 5148 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 5149 [__RTW89_MLD_MAX_LINK_NUM]; 5150 }; 5151 5152 struct rtw89_chanctx { 5153 struct cfg80211_chan_def chandef; 5154 struct rtw89_chan chan; 5155 struct rtw89_chan_rcd rcd; 5156 5157 /* only assigned when running with chanctx_ops */ 5158 struct rtw89_chanctx_cfg *cfg; 5159 }; 5160 5161 struct rtw89_edcca_bak { 5162 u8 a; 5163 u8 p; 5164 u8 ppdu; 5165 u8 th_old; 5166 }; 5167 5168 enum rtw89_dm_type { 5169 RTW89_DM_DYNAMIC_EDCCA, 5170 RTW89_DM_THERMAL_PROTECT, 5171 RTW89_DM_TAS, 5172 RTW89_DM_MLO, 5173 }; 5174 5175 #define RTW89_THERMAL_PROT_LV_MAX 5 5176 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 5177 5178 struct rtw89_hal { 5179 u32 rx_fltr; 5180 u8 cv; 5181 u8 cid; /* enum rtw89_core_chip_cid */ 5182 u8 acv; 5183 u16 aid; /* enum rtw89_core_chip_aid */ 5184 u32 antenna_tx; 5185 u32 antenna_rx; 5186 u8 tx_nss; 5187 u8 rx_nss; 5188 bool tx_path_diversity; 5189 bool ant_diversity; 5190 bool ant_diversity_fixed; 5191 bool support_cckpd; 5192 bool support_igi; 5193 bool no_mcs_12_13; 5194 bool no_eht; 5195 5196 atomic_t roc_chanctx_idx; 5197 5198 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 5199 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 5200 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 5201 struct cfg80211_chan_def roc_chandef; 5202 5203 bool entity_active[RTW89_PHY_NUM]; 5204 bool entity_pause; 5205 enum rtw89_entity_mode entity_mode; 5206 struct rtw89_entity_mgnt entity_mgnt; 5207 5208 enum rtw89_phy_idx entity_force_hw; 5209 5210 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 5211 5212 u8 thermal_prot_th; 5213 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 5214 }; 5215 5216 #define RTW89_MAX_MAC_ID_NUM 128 5217 #define RTW89_MAX_PKT_OFLD_NUM 255 5218 5219 enum rtw89_flags { 5220 RTW89_FLAG_POWERON, 5221 RTW89_FLAG_DMAC_FUNC, 5222 RTW89_FLAG_CMAC0_FUNC, 5223 RTW89_FLAG_CMAC1_FUNC, 5224 RTW89_FLAG_CMAC0_PWR, 5225 RTW89_FLAG_CMAC1_PWR, 5226 RTW89_FLAG_FW_RDY, 5227 RTW89_FLAG_RUNNING, 5228 RTW89_FLAG_PROBE_DONE, 5229 RTW89_FLAG_BFEE_MON, 5230 RTW89_FLAG_BFEE_EN, 5231 RTW89_FLAG_BFEE_TIMER_KEEP, 5232 RTW89_FLAG_NAPI_RUNNING, 5233 RTW89_FLAG_LEISURE_PS, 5234 RTW89_FLAG_LOW_POWER_MODE, 5235 RTW89_FLAG_INACTIVE_PS, 5236 RTW89_FLAG_CRASH_SIMULATING, 5237 RTW89_FLAG_SER_HANDLING, 5238 RTW89_FLAG_WOWLAN, 5239 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 5240 RTW89_FLAG_CHANGING_INTERFACE, 5241 RTW89_FLAG_HW_RFKILL_STATE, 5242 RTW89_FLAG_UNPLUGGED, 5243 5244 NUM_OF_RTW89_FLAGS, 5245 }; 5246 5247 enum rtw89_quirks { 5248 RTW89_QUIRK_PCI_BER, 5249 RTW89_QUIRK_THERMAL_PROT_120C, 5250 RTW89_QUIRK_THERMAL_PROT_110C, 5251 5252 NUM_OF_RTW89_QUIRKS, 5253 }; 5254 5255 enum rtw89_custid { 5256 RTW89_CUSTID_NONE = 0, 5257 RTW89_CUSTID_HP = 1, 5258 RTW89_CUSTID_ASUS = 2, 5259 RTW89_CUSTID_ACER = 3, 5260 RTW89_CUSTID_LENOVO = 4, 5261 RTW89_CUSTID_NEC = 5, 5262 RTW89_CUSTID_AMD = 6, 5263 RTW89_CUSTID_FUJITSU = 7, 5264 RTW89_CUSTID_DELL = 8, 5265 }; 5266 5267 enum rtw89_pkt_drop_sel { 5268 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5269 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5270 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5271 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5272 RTW89_PKT_DROP_SEL_MACID_ALL, 5273 RTW89_PKT_DROP_SEL_MG0_ONCE, 5274 RTW89_PKT_DROP_SEL_HIQ_ONCE, 5275 RTW89_PKT_DROP_SEL_HIQ_PORT, 5276 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 5277 RTW89_PKT_DROP_SEL_BAND, 5278 RTW89_PKT_DROP_SEL_BAND_ONCE, 5279 RTW89_PKT_DROP_SEL_REL_MACID, 5280 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 5281 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 5282 }; 5283 5284 struct rtw89_pkt_drop_params { 5285 enum rtw89_pkt_drop_sel sel; 5286 enum rtw89_mac_idx mac_band; 5287 u8 macid; 5288 u8 port; 5289 u8 mbssid; 5290 bool tf_trs; 5291 u32 macid_band_sel[4]; 5292 }; 5293 5294 struct rtw89_pkt_stat { 5295 u16 beacon_nr; 5296 u8 beacon_rate; 5297 u32 beacon_len; 5298 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 5299 }; 5300 5301 #define RTW89_BCN_TRACK_STAT_NR 32 5302 #define RTW89_BCN_TRACK_SCALE_FACTOR 10 5303 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6 5304 #define RTW89_BCN_TRACK_BIN_WIDTH 5 5305 #define RTW89_BCN_TRACK_TARGET_BCN 80 5306 5307 struct rtw89_beacon_dist { 5308 u16 min; 5309 u16 max; 5310 u16 outlier_count; 5311 u16 lower_bound; 5312 u16 upper_bound; 5313 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM]; 5314 }; 5315 5316 struct rtw89_beacon_stat { 5317 u8 num; 5318 u8 wp; 5319 u16 tbtt_tu_min; 5320 u16 tbtt_tu_max; 5321 u16 drift[RTW89_BCN_TRACK_STAT_NR]; 5322 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR]; 5323 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR]; 5324 struct rtw89_beacon_dist bcn_dist; 5325 }; 5326 5327 DECLARE_EWMA(thermal, 4, 4); 5328 5329 struct rtw89_phy_stat { 5330 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 5331 u8 last_thermal_max; 5332 struct ewma_rssi bcn_rssi; 5333 struct rtw89_pkt_stat cur_pkt_stat; 5334 struct rtw89_pkt_stat last_pkt_stat; 5335 struct rtw89_beacon_stat bcn_stat; 5336 }; 5337 5338 enum rtw89_rfk_report_state { 5339 RTW89_RFK_STATE_START = 0x0, 5340 RTW89_RFK_STATE_OK = 0x1, 5341 RTW89_RFK_STATE_FAIL = 0x2, 5342 RTW89_RFK_STATE_TIMEOUT = 0x3, 5343 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 5344 }; 5345 5346 struct rtw89_rfk_wait_info { 5347 struct completion completion; 5348 ktime_t start_time; 5349 enum rtw89_rfk_report_state state; 5350 u8 version; 5351 }; 5352 5353 #define RTW89_DACK_PATH_NR 2 5354 #define RTW89_DACK_IDX_NR 2 5355 #define RTW89_DACK_MSBK_NR 16 5356 struct rtw89_dack_info { 5357 bool dack_done; 5358 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 5359 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5360 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5361 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5362 u32 dack_cnt; 5363 bool addck_timeout[RTW89_DACK_PATH_NR]; 5364 bool dadck_timeout[RTW89_DACK_PATH_NR]; 5365 bool msbk_timeout[RTW89_DACK_PATH_NR]; 5366 }; 5367 5368 enum rtw89_rfk_chs_nrs { 5369 __RTW89_RFK_CHS_NR_V0 = 2, 5370 __RTW89_RFK_CHS_NR_V1 = 3, 5371 5372 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 5373 }; 5374 5375 struct rtw89_rfk_mcc_info_data { 5376 u8 ch[RTW89_RFK_CHS_NR]; 5377 u8 band[RTW89_RFK_CHS_NR]; 5378 u8 bw[RTW89_RFK_CHS_NR]; 5379 u32 rf18[RTW89_RFK_CHS_NR]; 5380 u8 table_idx; 5381 }; 5382 5383 struct rtw89_rfk_mcc_info { 5384 struct rtw89_rfk_mcc_info_data data[2]; 5385 }; 5386 5387 #define RTW89_IQK_CHS_NR 2 5388 #define RTW89_IQK_PATH_NR 4 5389 5390 struct rtw89_lck_info { 5391 u8 thermal[RF_PATH_MAX]; 5392 }; 5393 5394 struct rtw89_rx_dck_info { 5395 u8 thermal[RF_PATH_MAX]; 5396 }; 5397 5398 struct rtw89_iqk_info { 5399 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5400 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5401 bool lok_fail[RTW89_IQK_PATH_NR]; 5402 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5403 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5404 u32 iqk_fail_cnt; 5405 bool is_iqk_init; 5406 u32 iqk_channel[RTW89_IQK_CHS_NR]; 5407 u8 iqk_band[RTW89_IQK_PATH_NR]; 5408 u8 iqk_ch[RTW89_IQK_PATH_NR]; 5409 u8 iqk_bw[RTW89_IQK_PATH_NR]; 5410 u8 iqk_times; 5411 u8 version; 5412 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 5413 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 5414 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 5415 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 5416 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 5417 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 5418 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 5419 bool is_nbiqk; 5420 bool iqk_fft_en; 5421 bool iqk_xym_en; 5422 bool iqk_sram_en; 5423 bool iqk_cfir_en; 5424 u32 syn1to2; 5425 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5426 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 5427 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5428 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5429 }; 5430 5431 #define RTW89_DPK_RF_PATH 2 5432 #define RTW89_DPK_AVG_THERMAL_NUM 8 5433 #define RTW89_DPK_BKUP_NUM 2 5434 struct rtw89_dpk_bkup_para { 5435 enum rtw89_band band; 5436 enum rtw89_bandwidth bw; 5437 u8 ch; 5438 u8 path_ok; 5439 u8 mdpd_en; 5440 u8 txagc_dpk; 5441 u8 ther_dpk; 5442 u8 gs; 5443 u16 pwsf; 5444 }; 5445 5446 struct rtw89_dpk_info { 5447 bool is_dpk_enable; 5448 bool is_dpk_reload_en; 5449 u8 dpk_gs[RTW89_PHY_NUM]; 5450 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5451 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5452 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5453 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5454 u8 cur_idx[RTW89_DPK_RF_PATH]; 5455 u8 cur_k_set; 5456 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5457 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5458 u32 dpk_order[RTW89_DPK_RF_PATH]; 5459 }; 5460 5461 struct rtw89_fem_info { 5462 bool elna_2g; 5463 bool elna_5g; 5464 bool epa_2g; 5465 bool epa_5g; 5466 bool epa_6g; 5467 }; 5468 5469 struct rtw89_phy_ch_info { 5470 u8 rssi_min; 5471 u16 rssi_min_macid; 5472 u8 pre_rssi_min; 5473 u8 rssi_max; 5474 u16 rssi_max_macid; 5475 u8 rxsc_160; 5476 u8 rxsc_80; 5477 u8 rxsc_40; 5478 u8 rxsc_20; 5479 u8 rxsc_l; 5480 u8 is_noisy; 5481 }; 5482 5483 struct rtw89_agc_gaincode_set { 5484 u8 lna_idx; 5485 u8 tia_idx; 5486 u8 rxb_idx; 5487 }; 5488 5489 #define IGI_RSSI_TH_NUM 5 5490 #define FA_TH_NUM 4 5491 #define TIA_LNA_OP1DB_NUM 8 5492 #define LNA_GAIN_NUM 7 5493 #define TIA_GAIN_NUM 2 5494 struct rtw89_dig_info { 5495 struct rtw89_agc_gaincode_set cur_gaincode; 5496 bool force_gaincode_idx_en; 5497 struct rtw89_agc_gaincode_set force_gaincode; 5498 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5499 u16 fa_th[FA_TH_NUM]; 5500 u8 igi_rssi; 5501 u8 igi_fa_rssi; 5502 u8 fa_rssi_ofst; 5503 u8 dyn_igi_max; 5504 u8 dyn_igi_min; 5505 bool dyn_pd_th_en; 5506 u8 dyn_pd_th_max; 5507 u8 pd_low_th_ofst; 5508 u8 ib_pbk; 5509 s8 ib_pkpwr; 5510 s8 lna_gain_a[LNA_GAIN_NUM]; 5511 s8 lna_gain_g[LNA_GAIN_NUM]; 5512 s8 *lna_gain; 5513 s8 tia_gain_a[TIA_GAIN_NUM]; 5514 s8 tia_gain_g[TIA_GAIN_NUM]; 5515 s8 *tia_gain; 5516 u32 bak_dig; 5517 bool is_linked_pre; 5518 bool bypass_dig; 5519 bool pause_dig; 5520 }; 5521 5522 enum rtw89_multi_cfo_mode { 5523 RTW89_PKT_BASED_AVG_MODE = 0, 5524 RTW89_ENTRY_BASED_AVG_MODE = 1, 5525 RTW89_TP_BASED_AVG_MODE = 2, 5526 }; 5527 5528 enum rtw89_phy_cfo_status { 5529 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5530 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5531 RTW89_PHY_DCFO_STATE_HOLD = 2, 5532 RTW89_PHY_DCFO_STATE_MAX 5533 }; 5534 5535 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5536 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5537 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5538 }; 5539 5540 struct rtw89_cfo_tracking_info { 5541 u16 cfo_timer_ms; 5542 bool cfo_trig_by_timer_en; 5543 enum rtw89_phy_cfo_status phy_cfo_status; 5544 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5545 u8 phy_cfo_trk_cnt; 5546 bool is_adjust; 5547 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5548 bool apply_compensation; 5549 u8 crystal_cap; 5550 u8 crystal_cap_default; 5551 u8 def_x_cap; 5552 s8 x_cap_ofst; 5553 u32 sta_cfo_tolerance; 5554 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5555 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5556 s32 cfo_avg_pre; 5557 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5558 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5559 s32 dcfo_avg; 5560 s32 dcfo_avg_pre; 5561 u32 packet_count; 5562 u32 packet_count_pre; 5563 s32 residual_cfo_acc; 5564 u8 phy_cfotrk_state; 5565 u8 phy_cfotrk_cnt; 5566 bool divergence_lock_en; 5567 u8 x_cap_lb; 5568 u8 x_cap_ub; 5569 u8 lock_cnt; 5570 }; 5571 5572 enum rtw89_tssi_mode { 5573 RTW89_TSSI_NORMAL = 0, 5574 RTW89_TSSI_SCAN = 1, 5575 }; 5576 5577 enum rtw89_tssi_alimk_band { 5578 TSSI_ALIMK_2G = 0, 5579 TSSI_ALIMK_5GL, 5580 TSSI_ALIMK_5GM, 5581 TSSI_ALIMK_5GH, 5582 TSSI_ALIMK_MAX 5583 }; 5584 5585 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5586 #define TSSI_TRIM_CH_GROUP_NUM 8 5587 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5588 5589 #define TSSI_CCK_CH_GROUP_NUM 6 5590 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5591 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5592 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5593 #define TSSI_MCS_CH_GROUP_NUM \ 5594 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5595 #define TSSI_MAX_CH_NUM 67 5596 #define TSSI_ALIMK_VALUE_NUM 8 5597 5598 struct rtw89_tssi_info { 5599 u8 thermal[RF_PATH_MAX]; 5600 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5601 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5602 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5603 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5604 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5605 s8 extra_ofst[RF_PATH_MAX]; 5606 bool tssi_tracking_check[RF_PATH_MAX]; 5607 u8 default_txagc_offset[RF_PATH_MAX]; 5608 u32 base_thermal[RF_PATH_MAX]; 5609 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5610 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5611 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5612 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5613 u64 tssi_alimk_time; 5614 }; 5615 5616 struct rtw89_power_trim_info { 5617 bool pg_thermal_trim; 5618 bool pg_pa_bias_trim; 5619 bool pg_vco_trim; 5620 u8 thermal_trim[RF_PATH_MAX]; 5621 u8 pa_bias_trim[RF_PATH_MAX]; 5622 u8 pad_bias_trim[RF_PATH_MAX]; 5623 u8 vco_trim[RF_PATH_MAX]; 5624 }; 5625 5626 enum rtw89_regd_func { 5627 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5628 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5629 5630 NUM_OF_RTW89_REGD_FUNC, 5631 }; 5632 5633 struct rtw89_regd { 5634 char alpha2[3]; 5635 u8 txpwr_regd[RTW89_BAND_NUM]; 5636 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5637 }; 5638 5639 struct rtw89_regd_data { 5640 unsigned int nr; 5641 struct rtw89_regd map[] __counted_by(nr); 5642 }; 5643 5644 struct rtw89_regd_ctrl { 5645 unsigned int nr; 5646 const struct rtw89_regd *map; 5647 }; 5648 5649 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5650 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5651 #define RTW89_5GHZ_UNII4_START_INDEX 25 5652 5653 struct rtw89_regulatory_info { 5654 struct rtw89_regd_ctrl ctrl; 5655 const struct rtw89_regd *regd; 5656 bool programmed; 5657 5658 enum rtw89_reg_6ghz_power reg_6ghz_power; 5659 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5660 bool txpwr_uk_follow_etsi; 5661 5662 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5663 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5664 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5665 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM); 5666 }; 5667 5668 enum rtw89_ifs_clm_application { 5669 RTW89_IFS_CLM_INIT = 0, 5670 RTW89_IFS_CLM_BACKGROUND = 1, 5671 RTW89_IFS_CLM_ACS = 2, 5672 RTW89_IFS_CLM_DIG = 3, 5673 RTW89_IFS_CLM_TDMA_DIG = 4, 5674 RTW89_IFS_CLM_DBG = 5, 5675 RTW89_IFS_CLM_DBG_MANUAL = 6 5676 }; 5677 5678 enum rtw89_env_racing_lv { 5679 RTW89_RAC_RELEASE = 0, 5680 RTW89_RAC_LV_1 = 1, 5681 RTW89_RAC_LV_2 = 2, 5682 RTW89_RAC_LV_3 = 3, 5683 RTW89_RAC_LV_4 = 4, 5684 RTW89_RAC_MAX_NUM = 5 5685 }; 5686 5687 struct rtw89_ccx_para_info { 5688 enum rtw89_env_racing_lv rac_lv; 5689 u16 mntr_time; 5690 bool nhm_incld_cca; 5691 u8 nhm_manual_th_ofst; 5692 u8 nhm_manual_th0; 5693 enum rtw89_ifs_clm_application ifs_clm_app; 5694 u32 ifs_clm_manual_th_times; 5695 u32 ifs_clm_manual_th0; 5696 u8 fahm_manual_th_ofst; 5697 u8 fahm_manual_th0; 5698 u8 fahm_numer_opt; 5699 u8 fahm_denom_opt; 5700 }; 5701 5702 enum rtw89_ccx_edcca_opt_sc_idx { 5703 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5704 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5705 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5706 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5707 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5708 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5709 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5710 RTW89_CCX_EDCCA_SEG1_S3 = 7 5711 }; 5712 5713 enum rtw89_ccx_edcca_opt_bw_idx { 5714 RTW89_CCX_EDCCA_BW20_0 = 0, 5715 RTW89_CCX_EDCCA_BW20_1 = 1, 5716 RTW89_CCX_EDCCA_BW20_2 = 2, 5717 RTW89_CCX_EDCCA_BW20_3 = 3, 5718 RTW89_CCX_EDCCA_BW20_4 = 4, 5719 RTW89_CCX_EDCCA_BW20_5 = 5, 5720 RTW89_CCX_EDCCA_BW20_6 = 6, 5721 RTW89_CCX_EDCCA_BW20_7 = 7 5722 }; 5723 5724 struct rtw89_nhm_report { 5725 struct list_head list; 5726 struct ieee80211_channel *channel; 5727 u8 noise; 5728 }; 5729 5730 #define RTW89_FAHM_TH_NUM 11 5731 #define RTW89_FAHM_RPT_NUM 12 5732 #define RTW89_IFS_CLM_NUM 4 5733 struct rtw89_env_monitor_info { 5734 u8 ccx_watchdog_result; 5735 bool ccx_ongoing; 5736 u8 ccx_rac_lv; 5737 bool ccx_manual_ctrl; 5738 u16 ifs_clm_mntr_time; 5739 enum rtw89_ifs_clm_application ifs_clm_app; 5740 u16 ccx_period; 5741 u8 ccx_unit_idx; 5742 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5743 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5744 u16 ifs_clm_tx; 5745 u16 ifs_clm_edcca_excl_cca; 5746 u16 ifs_clm_ofdmfa; 5747 u16 ifs_clm_ofdmcca_excl_fa; 5748 u16 ifs_clm_cckfa; 5749 u16 ifs_clm_cckcca_excl_fa; 5750 u16 ifs_clm_total_ifs; 5751 u16 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5752 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5753 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5754 u8 ifs_clm_tx_ratio; 5755 u8 ifs_clm_edcca_excl_cca_ratio; 5756 u8 ifs_clm_cck_fa_ratio; 5757 u8 ifs_clm_ofdm_fa_ratio; 5758 u8 ifs_clm_cck_cca_excl_fa_ratio; 5759 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5760 u16 ifs_clm_cck_fa_permil; 5761 u16 ifs_clm_ofdm_fa_permil; 5762 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5763 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5764 bool nhm_include_cca; 5765 u32 nhm_sum; 5766 u32 nhm_mntr_time; 5767 u16 nhm_result[RTW89_NHM_RPT_NUM]; 5768 u8 nhm_th[RTW89_NHM_RPT_NUM]; 5769 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM]; 5770 struct list_head nhm_rpt_list; 5771 }; 5772 5773 enum rtw89_ser_rcvy_step { 5774 RTW89_SER_DRV_STOP_TX, 5775 RTW89_SER_DRV_STOP_RX, 5776 RTW89_SER_DRV_STOP_RUN, 5777 RTW89_SER_HAL_STOP_DMA, 5778 RTW89_SER_SUPPRESS_LOG, 5779 RTW89_NUM_OF_SER_FLAGS 5780 }; 5781 5782 struct rtw89_ser_count { 5783 unsigned int l1; 5784 unsigned int l2; 5785 }; 5786 5787 struct rtw89_ser { 5788 u8 state; 5789 u8 alarm_event; 5790 bool prehandle_l1; 5791 5792 struct rtw89_ser_count sw_cnt; 5793 5794 struct work_struct ser_hdl_work; 5795 struct delayed_work ser_alarm_work; 5796 const struct state_ent *st_tbl; 5797 const struct event_ent *ev_tbl; 5798 struct list_head msg_q; 5799 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5800 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5801 }; 5802 5803 enum rtw89_mac_ax_ps_mode { 5804 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5805 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5806 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5807 RTW89_MAC_AX_PS_MODE_MAX = 3, 5808 }; 5809 5810 enum rtw89_last_rpwm_mode { 5811 RTW89_LAST_RPWM_PS = 0x0, 5812 RTW89_LAST_RPWM_ACTIVE = 0x6, 5813 }; 5814 5815 struct rtw89_lps_parm { 5816 u8 macid; 5817 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5818 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5819 }; 5820 5821 struct rtw89_ppdu_sts_info { 5822 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5823 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5824 }; 5825 5826 struct rtw89_early_h2c { 5827 struct list_head list; 5828 u8 *h2c; 5829 u16 h2c_len; 5830 }; 5831 5832 struct rtw89_hw_scan_extra_op { 5833 bool set; 5834 u8 macid; 5835 u8 port; 5836 struct rtw89_chan chan; 5837 struct rtw89_vif_link *rtwvif_link; 5838 }; 5839 5840 struct rtw89_hw_scan_info { 5841 struct rtw89_vif_link *scanning_vif; 5842 struct list_head pkt_list[NUM_NL80211_BANDS]; 5843 struct list_head chan_list; 5844 struct rtw89_chan op_chan; 5845 struct rtw89_hw_scan_extra_op extra_op; 5846 bool connected; 5847 bool abort; 5848 u16 delay; /* in unit of ms */ 5849 u8 seq: 2; 5850 }; 5851 5852 enum rtw89_phy_bb_gain_band { 5853 RTW89_BB_GAIN_BAND_2G = 0, 5854 RTW89_BB_GAIN_BAND_5G_L = 1, 5855 RTW89_BB_GAIN_BAND_5G_M = 2, 5856 RTW89_BB_GAIN_BAND_5G_H = 3, 5857 RTW89_BB_GAIN_BAND_6G_L = 4, 5858 RTW89_BB_GAIN_BAND_6G_M = 5, 5859 RTW89_BB_GAIN_BAND_6G_H = 6, 5860 RTW89_BB_GAIN_BAND_6G_UH = 7, 5861 5862 RTW89_BB_GAIN_BAND_NR, 5863 }; 5864 5865 enum rtw89_phy_gain_band_be { 5866 RTW89_BB_GAIN_BAND_2G_BE = 0, 5867 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5868 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5869 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5870 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5871 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5872 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5873 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5874 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5875 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5876 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5877 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5878 5879 RTW89_BB_GAIN_BAND_NR_BE, 5880 }; 5881 5882 enum rtw89_phy_bb_bw_be { 5883 RTW89_BB_BW_20_40 = 0, 5884 RTW89_BB_BW_80_160_320 = 1, 5885 5886 RTW89_BB_BW_NR_BE, 5887 }; 5888 5889 enum rtw89_bw20_sc { 5890 RTW89_BW20_SC_20M = 1, 5891 RTW89_BW20_SC_40M = 2, 5892 RTW89_BW20_SC_80M = 4, 5893 RTW89_BW20_SC_160M = 8, 5894 RTW89_BW20_SC_320M = 16, 5895 }; 5896 5897 enum rtw89_cmac_table_bw { 5898 RTW89_CMAC_BW_20M = 0, 5899 RTW89_CMAC_BW_40M = 1, 5900 RTW89_CMAC_BW_80M = 2, 5901 RTW89_CMAC_BW_160M = 3, 5902 RTW89_CMAC_BW_320M = 4, 5903 5904 RTW89_CMAC_BW_NR, 5905 }; 5906 5907 enum rtw89_phy_bb_rxsc_num { 5908 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5909 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5910 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5911 }; 5912 5913 struct rtw89_phy_bb_gain_info { 5914 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5915 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5916 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5917 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5918 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5919 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5920 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5921 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5922 [RTW89_BB_RXSC_NUM_40]; 5923 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5924 [RTW89_BB_RXSC_NUM_80]; 5925 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5926 [RTW89_BB_RXSC_NUM_160]; 5927 }; 5928 5929 struct rtw89_phy_bb_gain_info_be { 5930 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5931 [LNA_GAIN_NUM]; 5932 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5933 [TIA_GAIN_NUM]; 5934 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5935 [RF_PATH_MAX][LNA_GAIN_NUM]; 5936 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5937 [RF_PATH_MAX][LNA_GAIN_NUM]; 5938 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5939 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5940 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5941 [RTW89_BW20_SC_20M]; 5942 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5943 [RTW89_BW20_SC_40M]; 5944 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5945 [RTW89_BW20_SC_80M]; 5946 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5947 [RTW89_BW20_SC_160M]; 5948 }; 5949 5950 struct rtw89_phy_efuse_gain { 5951 bool offset_valid; 5952 bool comp_valid; 5953 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5954 s8 offset2[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5955 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5956 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5957 s8 ref_gain_base[RTW89_PHY_NUM]; /* S(8, 2) */ 5958 s8 cck_rpl_base[RTW89_PHY_NUM]; /* S(8, 0) */ 5959 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5960 }; 5961 5962 struct rtw89_phy_calc_efuse_gain { 5963 s8 cck_mean_gain_bias; 5964 s8 cck_rpl_ofst; 5965 s8 rssi_ofst; 5966 }; 5967 5968 #define RTW89_MAX_PATTERN_NUM 18 5969 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5970 #define RTW89_MAX_PATTERN_SIZE 128 5971 5972 struct rtw89_wow_cam_info { 5973 bool r_w; 5974 u8 idx; 5975 __le32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5976 u16 crc; 5977 bool negative_pattern_match; 5978 bool skip_mac_hdr; 5979 bool uc; 5980 bool mc; 5981 bool bc; 5982 bool valid; 5983 }; 5984 5985 struct rtw89_wow_key_info { 5986 u8 ptk_tx_iv[8]; 5987 u8 valid_check; 5988 u8 symbol_check_en; 5989 u8 gtk_keyidx; 5990 u8 rsvd[5]; 5991 u8 ptk_rx_iv[8]; 5992 u8 gtk_rx_iv[4][8]; 5993 } __packed; 5994 5995 struct rtw89_wow_gtk_info { 5996 u8 kck[32]; 5997 u8 kek[32]; 5998 u8 tk1[16]; 5999 u8 rxmickey[8]; 6000 u8 txmickey[8]; 6001 __le32 igtk_keyid; 6002 __le64 ipn; 6003 u8 igtk[2][32]; 6004 u8 psk[32]; 6005 } __packed; 6006 6007 struct rtw89_wow_aoac_report { 6008 u8 rpt_ver; 6009 u8 sec_type; 6010 u8 key_idx; 6011 u8 pattern_idx; 6012 u8 rekey_ok; 6013 u8 ptk_tx_iv[8]; 6014 u8 eapol_key_replay_count[8]; 6015 u8 gtk[32]; 6016 u8 ptk_rx_iv[8]; 6017 u8 gtk_rx_iv[4][8]; 6018 u64 igtk_key_id; 6019 u64 igtk_ipn; 6020 u8 igtk[32]; 6021 u8 csa_pri_ch; 6022 u8 csa_bw; 6023 u8 csa_ch_offset; 6024 u8 csa_chsw_failed; 6025 u8 csa_ch_band; 6026 }; 6027 6028 struct rtw89_wow_param { 6029 struct rtw89_vif_link *rtwvif_link; 6030 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 6031 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 6032 struct rtw89_wow_key_info key_info; 6033 struct rtw89_wow_gtk_info gtk_info; 6034 struct rtw89_wow_aoac_report aoac_rpt; 6035 u8 pattern_cnt; 6036 u8 ptk_alg; 6037 u8 gtk_alg; 6038 u8 ptk_keyidx; 6039 u8 akm; 6040 6041 /* see RTW89_WOW_WAIT_COND series for wait condition */ 6042 struct rtw89_wait_info wait; 6043 6044 bool pno_inited; 6045 struct list_head pno_pkt_list; 6046 struct cfg80211_sched_scan_request *nd_config; 6047 }; 6048 6049 struct rtw89_mcc_limit { 6050 bool enable; 6051 u16 max_tob; /* TU; max time offset behind */ 6052 u16 max_toa; /* TU; max time offset ahead */ 6053 u16 max_dur; /* TU */ 6054 }; 6055 6056 struct rtw89_mcc_policy { 6057 u8 c2h_rpt; 6058 u8 tx_null_early; 6059 u8 dis_tx_null; 6060 u8 in_curr_ch; 6061 u8 dis_sw_retry; 6062 u8 sw_retry_count; 6063 }; 6064 6065 struct rtw89_mcc_role { 6066 struct rtw89_vif_link *rtwvif_link; 6067 struct rtw89_mcc_policy policy; 6068 struct rtw89_mcc_limit limit; 6069 6070 const struct rtw89_mcc_courtesy_cfg *crtz; 6071 6072 /* only valid when running with FW MRC mechanism */ 6073 u8 slot_idx; 6074 6075 /* byte-array in LE order for FW */ 6076 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 6077 u8 probe_count; 6078 6079 u16 duration; /* TU */ 6080 u16 beacon_interval; /* TU */ 6081 bool is_2ghz; 6082 bool is_go; 6083 bool is_gc; 6084 bool ignore_bcn; 6085 }; 6086 6087 struct rtw89_mcc_bt_role { 6088 u16 duration; /* TU */ 6089 }; 6090 6091 struct rtw89_mcc_courtesy_cfg { 6092 u8 slot_num; 6093 u8 macid_tgt; 6094 }; 6095 6096 struct rtw89_mcc_courtesy { 6097 struct rtw89_mcc_courtesy_cfg ref; 6098 struct rtw89_mcc_courtesy_cfg aux; 6099 }; 6100 6101 enum rtw89_mcc_plan { 6102 RTW89_MCC_PLAN_TAIL_BT, 6103 RTW89_MCC_PLAN_MID_BT, 6104 RTW89_MCC_PLAN_NO_BT, 6105 6106 NUM_OF_RTW89_MCC_PLAN, 6107 }; 6108 6109 struct rtw89_mcc_pattern { 6110 s16 tob_ref; /* TU; time offset behind of reference role */ 6111 s16 toa_ref; /* TU; time offset ahead of reference role */ 6112 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 6113 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 6114 6115 enum rtw89_mcc_plan plan; 6116 struct rtw89_mcc_courtesy courtesy; 6117 }; 6118 6119 struct rtw89_mcc_sync { 6120 bool enable; 6121 u16 offset; /* TU */ 6122 u8 macid_src; 6123 u8 band_src; 6124 u8 port_src; 6125 u8 macid_tgt; 6126 u8 band_tgt; 6127 u8 port_tgt; 6128 }; 6129 6130 struct rtw89_mcc_config { 6131 struct rtw89_mcc_pattern pattern; 6132 struct rtw89_mcc_sync sync; 6133 u64 start_tsf; 6134 u64 start_tsf_in_aux_domain; 6135 u64 prepare_delay; 6136 u16 mcc_interval; /* TU */ 6137 u16 beacon_offset; /* TU */ 6138 }; 6139 6140 enum rtw89_mcc_mode { 6141 RTW89_MCC_MODE_GO_STA, 6142 RTW89_MCC_MODE_GC_STA, 6143 }; 6144 6145 struct rtw89_mcc_info { 6146 struct rtw89_wait_info wait; 6147 6148 u8 group; 6149 enum rtw89_mcc_mode mode; 6150 struct rtw89_mcc_role role_ref; /* reference role */ 6151 struct rtw89_mcc_role role_aux; /* auxiliary role */ 6152 struct rtw89_mcc_bt_role bt_role; 6153 struct rtw89_mcc_config config; 6154 }; 6155 6156 enum rtw89_mlo_mode { 6157 RTW89_MLO_MODE_MLSR = 0, 6158 RTW89_MLO_MODE_EMLSR = 1, 6159 6160 NUM_OF_RTW89_MLO_MODE, 6161 }; 6162 6163 struct rtw89_mlo_info { 6164 struct rtw89_wait_info wait; 6165 }; 6166 6167 struct rtw89_beacon_track_info { 6168 bool is_data_ready; 6169 u32 tbtt_offset; /* in unit of microsecond */ 6170 u16 bcn_timeout; /* in unit of millisecond */ 6171 6172 /* The following are constant and set at association. */ 6173 u8 dtim; 6174 u16 beacon_int; 6175 u16 low_bcn_th; 6176 u16 med_bcn_th; 6177 u16 high_bcn_th; 6178 u16 target_bcn_th; 6179 u16 outlier_low_bcn_th; 6180 u16 outlier_high_bcn_th; 6181 u32 close_bcn_intvl_th; 6182 u32 tbtt_diff_th; 6183 }; 6184 6185 struct rtw89_tid_stats { 6186 s64 last_pn; 6187 u16 last_sn; 6188 bool started; 6189 }; 6190 6191 struct rtw89_dev { 6192 struct ieee80211_hw *hw; 6193 struct device *dev; 6194 const struct ieee80211_ops *ops; 6195 6196 bool dbcc_en; 6197 bool support_mlo; 6198 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 6199 struct rtw89_hw_scan_info scan_info; 6200 const struct rtw89_chip_info *chip; 6201 const struct rtw89_chip_variant *variant; 6202 const struct rtw89_pci_info *pci_info; 6203 const struct rtw89_rfe_parms *rfe_parms; 6204 struct rtw89_hal hal; 6205 struct rtw89_beacon_track_info bcn_track; 6206 struct rtw89_mcc_info mcc; 6207 struct rtw89_mlo_info mlo; 6208 struct rtw89_mac_info mac; 6209 struct rtw89_fw_info fw; 6210 struct rtw89_hci_info hci; 6211 struct rtw89_efuse efuse; 6212 struct rtw89_traffic_stats stats; 6213 struct rtw89_rfe_data *rfe_data; 6214 enum rtw89_custid custid; 6215 6216 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 6217 refcount_t refcount_ap_info; 6218 6219 struct list_head rtwvifs_list; 6220 struct workqueue_struct *txq_wq; 6221 struct work_struct txq_work; 6222 struct delayed_work txq_reinvoke_work; 6223 /* used to protect ba_list and forbid_ba_list */ 6224 spinlock_t ba_lock; 6225 /* txqs to setup ba session */ 6226 struct list_head ba_list; 6227 /* txqs to forbid ba session */ 6228 struct list_head forbid_ba_list; 6229 struct work_struct ba_work; 6230 /* used to protect rpwm */ 6231 spinlock_t rpwm_lock; 6232 6233 struct list_head tx_waits; 6234 struct wiphy_delayed_work tx_wait_work; 6235 6236 struct rtw89_tx_rpt tx_rpt; 6237 6238 struct rtw89_cam_info cam_info; 6239 6240 struct sk_buff_head c2h_queue; 6241 struct wiphy_work c2h_work; 6242 struct wiphy_work ips_work; 6243 struct wiphy_work cancel_6ghz_probe_work; 6244 struct work_struct load_firmware_work; 6245 6246 struct list_head early_h2c_list; 6247 6248 struct rtw89_ser ser; 6249 6250 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 6251 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 6252 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 6253 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 6254 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 6255 6256 struct rtw89_phy_stat phystat; 6257 struct rtw89_rfk_wait_info rfk_wait; 6258 struct rtw89_dack_info dack; 6259 struct rtw89_iqk_info iqk; 6260 struct rtw89_dpk_info dpk; 6261 struct rtw89_rfk_mcc_info rfk_mcc; 6262 struct rtw89_lck_info lck; 6263 struct rtw89_rx_dck_info rx_dck; 6264 bool is_tssi_mode[RF_PATH_MAX]; 6265 bool is_bt_iqk_timeout; 6266 6267 struct rtw89_fem_info fem; 6268 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 6269 struct rtw89_tssi_info tssi; 6270 struct rtw89_power_trim_info pwr_trim; 6271 6272 struct rtw89_cfo_tracking_info cfo_tracking; 6273 union { 6274 struct rtw89_phy_bb_gain_info ax; 6275 struct rtw89_phy_bb_gain_info_be be; 6276 } bb_gain; 6277 struct rtw89_phy_efuse_gain efuse_gain; 6278 struct rtw89_phy_ul_tb_info ul_tb_info; 6279 struct rtw89_antdiv_info antdiv; 6280 6281 struct rtw89_bb_ctx { 6282 enum rtw89_phy_idx phy_idx; 6283 struct rtw89_env_monitor_info env_monitor; 6284 struct rtw89_dig_info dig; 6285 struct rtw89_phy_ch_info ch_info; 6286 struct rtw89_edcca_bak edcca_bak; 6287 } bbs[RTW89_PHY_NUM]; 6288 6289 struct wiphy_delayed_work track_work; 6290 struct wiphy_delayed_work track_ps_work; 6291 struct wiphy_delayed_work chanctx_work; 6292 struct wiphy_delayed_work coex_act1_work; 6293 struct wiphy_delayed_work coex_bt_devinfo_work; 6294 struct wiphy_delayed_work coex_rfk_chk_work; 6295 struct wiphy_delayed_work cfo_track_work; 6296 struct wiphy_delayed_work mcc_prepare_done_work; 6297 struct delayed_work forbid_ba_work; 6298 struct wiphy_delayed_work antdiv_work; 6299 struct rtw89_ppdu_sts_info ppdu_sts; 6300 u8 total_sta_assoc; 6301 bool scanning; 6302 6303 struct rtw89_regulatory_info regulatory; 6304 struct rtw89_sar_info sar; 6305 struct rtw89_tas_info tas; 6306 struct rtw89_ant_gain_info ant_gain; 6307 6308 struct rtw89_btc btc; 6309 enum rtw89_ps_mode ps_mode; 6310 bool lps_enabled; 6311 u8 ps_hang_cnt; 6312 6313 struct rtw89_wow_param wow; 6314 6315 /* napi structure */ 6316 struct net_device *netdev; 6317 struct napi_struct napi; 6318 int napi_budget_countdown; 6319 6320 struct rtw89_debugfs *debugfs; 6321 struct rtw89_vif *pure_monitor_mode_vif; 6322 6323 /* HCI related data, keep last */ 6324 u8 priv[] __aligned(sizeof(void *)); 6325 }; 6326 6327 struct rtw89_link_conf_container { 6328 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 6329 }; 6330 6331 struct rtw89_vif_ml_trans { 6332 u16 mediate_links; 6333 u16 links_to_del; 6334 u16 links_to_add; 6335 }; 6336 6337 #define RTW89_VIF_IDLE_LINK_ID 0 6338 6339 struct rtw89_vif { 6340 struct rtw89_dev *rtwdev; 6341 struct list_head list; 6342 struct list_head mgnt_entry; 6343 struct rtw89_link_conf_container __rcu *snap_link_confs; 6344 6345 u8 mac_addr[ETH_ALEN]; 6346 __be32 ip_addr; 6347 6348 struct rtw89_traffic_stats stats; 6349 struct rtw89_traffic_stats stats_ps; 6350 u32 tdls_peer; 6351 6352 struct ieee80211_scan_ies *scan_ies; 6353 struct cfg80211_scan_request *scan_req; 6354 6355 struct rtw89_roc roc; 6356 bool offchan; 6357 6358 enum rtw89_mlo_mode mlo_mode; 6359 struct rtw89_vif_ml_trans ml_trans; 6360 6361 struct list_head dlink_pool; 6362 u8 links_inst_valid_num; 6363 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6364 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6365 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 6366 }; 6367 6368 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 6369 const struct rtw89_vif *rtwvif, 6370 unsigned int link_id) 6371 { 6372 *rtwvif_link = rtwvif->links[link_id]; 6373 return !!*rtwvif_link; 6374 } 6375 6376 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 6377 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6378 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 6379 6380 enum rtw89_sta_flags { 6381 RTW89_REMOTE_STA_IN_PS, 6382 6383 NUM_OF_RTW89_STA_FLAGS, 6384 }; 6385 6386 struct rtw89_sta { 6387 struct rtw89_dev *rtwdev; 6388 struct rtw89_vif *rtwvif; 6389 6390 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 6391 6392 bool disassoc; 6393 6394 struct sk_buff_head roc_queue; 6395 6396 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 6397 struct rtw89_tid_stats tid_rx_stats[IEEE80211_NUM_TIDS]; 6398 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 6399 6400 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6401 6402 struct list_head dlink_pool; 6403 u8 links_inst_valid_num; 6404 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6405 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6406 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 6407 }; 6408 6409 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 6410 const struct rtw89_sta *rtwsta, 6411 unsigned int link_id) 6412 { 6413 *rtwsta_link = rtwsta->links[link_id]; 6414 return !!*rtwsta_link; 6415 } 6416 6417 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 6418 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6419 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 6420 6421 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 6422 { 6423 /* const after init, so no need to check if active first */ 6424 return rtwvif->links_inst[0].mac_id; 6425 } 6426 6427 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 6428 { 6429 /* const after init, so no need to check if active first */ 6430 return rtwvif->links_inst[0].port; 6431 } 6432 6433 static inline struct rtw89_vif_link * 6434 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 6435 { 6436 if (index >= rtwvif->links_inst_valid_num || 6437 !test_bit(index, rtwvif->links_inst_map)) 6438 return NULL; 6439 return &rtwvif->links_inst[index]; 6440 } 6441 6442 static inline 6443 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 6444 { 6445 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6446 6447 return rtwvif_link - rtwvif->links_inst; 6448 } 6449 6450 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 6451 { 6452 /* const after init, so no need to check if active first */ 6453 return rtwsta->links_inst[0].mac_id; 6454 } 6455 6456 static inline struct rtw89_sta_link * 6457 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 6458 { 6459 if (index >= rtwsta->links_inst_valid_num || 6460 !test_bit(index, rtwsta->links_inst_map)) 6461 return NULL; 6462 return &rtwsta->links_inst[index]; 6463 } 6464 6465 static inline 6466 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 6467 { 6468 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6469 6470 return rtwsta_link - rtwsta->links_inst; 6471 } 6472 6473 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 6474 { 6475 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6476 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6477 6478 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6479 rtwsta_link); 6480 } 6481 6482 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 6483 { 6484 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6485 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6486 6487 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6488 NULL); 6489 synchronize_rcu(); 6490 } 6491 6492 static inline struct rtw89_sta_link * 6493 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 6494 { 6495 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 6496 } 6497 6498 #define rtw89_get_designated_link(links_holder) \ 6499 ({ \ 6500 typeof(links_holder) p = links_holder; \ 6501 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6502 }) 6503 6504 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait) 6505 { 6506 dev_kfree_skb_any(wait->skb); 6507 kfree_rcu(wait, rcu_head); 6508 } 6509 6510 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev) 6511 { 6512 struct rtw89_tx_wait_info *wait, *tmp; 6513 6514 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6515 6516 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) { 6517 if (!completion_done(&wait->completion)) 6518 continue; 6519 list_del(&wait->list); 6520 rtw89_tx_wait_release(wait); 6521 } 6522 } 6523 6524 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6525 struct rtw89_core_tx_request *tx_req) 6526 { 6527 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 6528 } 6529 6530 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6531 { 6532 rtwdev->hci.ops->reset(rtwdev); 6533 /* hci.ops->reset must complete all pending TX wait SKBs */ 6534 rtw89_tx_wait_list_clear(rtwdev); 6535 } 6536 6537 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 6538 { 6539 return rtwdev->hci.ops->start(rtwdev); 6540 } 6541 6542 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 6543 { 6544 rtwdev->hci.ops->stop(rtwdev); 6545 } 6546 6547 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 6548 { 6549 return rtwdev->hci.ops->deinit(rtwdev); 6550 } 6551 6552 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 6553 { 6554 rtwdev->hci.ops->pause(rtwdev, pause); 6555 } 6556 6557 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 6558 { 6559 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 6560 } 6561 6562 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 6563 { 6564 rtwdev->hci.ops->recalc_int_mit(rtwdev); 6565 } 6566 6567 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 6568 { 6569 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 6570 } 6571 6572 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 6573 { 6574 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 6575 } 6576 6577 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 6578 { 6579 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 6580 } 6581 6582 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 6583 bool drop) 6584 { 6585 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6586 return; 6587 6588 if (rtwdev->hci.ops->flush_queues) 6589 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6590 } 6591 6592 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6593 { 6594 if (rtwdev->hci.ops->recovery_start) 6595 rtwdev->hci.ops->recovery_start(rtwdev); 6596 } 6597 6598 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6599 { 6600 if (rtwdev->hci.ops->recovery_complete) 6601 rtwdev->hci.ops->recovery_complete(rtwdev); 6602 } 6603 6604 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6605 { 6606 if (rtwdev->hci.ops->enable_intr) 6607 rtwdev->hci.ops->enable_intr(rtwdev); 6608 } 6609 6610 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6611 { 6612 if (rtwdev->hci.ops->disable_intr) 6613 rtwdev->hci.ops->disable_intr(rtwdev); 6614 } 6615 6616 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6617 { 6618 if (rtwdev->hci.ops->ctrl_txdma_ch) 6619 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6620 } 6621 6622 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6623 { 6624 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6625 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6626 } 6627 6628 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6629 { 6630 if (rtwdev->hci.ops->ctrl_trxhci) 6631 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6632 } 6633 6634 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6635 { 6636 int ret = 0; 6637 6638 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6639 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6640 return ret; 6641 } 6642 6643 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6644 { 6645 if (rtwdev->hci.ops->clr_idx_all) 6646 rtwdev->hci.ops->clr_idx_all(rtwdev); 6647 } 6648 6649 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6650 { 6651 int ret = 0; 6652 6653 if (rtwdev->hci.ops->rst_bdram) 6654 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6655 return ret; 6656 } 6657 6658 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6659 { 6660 if (rtwdev->hci.ops->clear) 6661 rtwdev->hci.ops->clear(rtwdev, pdev); 6662 } 6663 6664 static inline 6665 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6666 { 6667 /* 6668 * This should be used by/after rtw89_hci_tx_write() and before doing 6669 * ieee80211_tx_info_clear_status(). 6670 */ 6671 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6672 6673 return (struct rtw89_tx_skb_data *)info->driver_data; 6674 } 6675 6676 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6677 { 6678 return rtwdev->hci.ops->read8(rtwdev, addr); 6679 } 6680 6681 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6682 { 6683 return rtwdev->hci.ops->read16(rtwdev, addr); 6684 } 6685 6686 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6687 { 6688 return rtwdev->hci.ops->read32(rtwdev, addr); 6689 } 6690 6691 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6692 { 6693 rtwdev->hci.ops->write8(rtwdev, addr, data); 6694 } 6695 6696 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6697 { 6698 rtwdev->hci.ops->write16(rtwdev, addr, data); 6699 } 6700 6701 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6702 { 6703 rtwdev->hci.ops->write32(rtwdev, addr, data); 6704 } 6705 6706 static inline void 6707 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6708 { 6709 u8 val; 6710 6711 val = rtw89_read8(rtwdev, addr); 6712 rtw89_write8(rtwdev, addr, val | bit); 6713 } 6714 6715 static inline void 6716 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6717 { 6718 u16 val; 6719 6720 val = rtw89_read16(rtwdev, addr); 6721 rtw89_write16(rtwdev, addr, val | bit); 6722 } 6723 6724 static inline void 6725 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6726 { 6727 u32 val; 6728 6729 val = rtw89_read32(rtwdev, addr); 6730 rtw89_write32(rtwdev, addr, val | bit); 6731 } 6732 6733 static inline void 6734 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6735 { 6736 u8 val; 6737 6738 val = rtw89_read8(rtwdev, addr); 6739 rtw89_write8(rtwdev, addr, val & ~bit); 6740 } 6741 6742 static inline void 6743 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6744 { 6745 u16 val; 6746 6747 val = rtw89_read16(rtwdev, addr); 6748 rtw89_write16(rtwdev, addr, val & ~bit); 6749 } 6750 6751 static inline void 6752 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6753 { 6754 u32 val; 6755 6756 val = rtw89_read32(rtwdev, addr); 6757 rtw89_write32(rtwdev, addr, val & ~bit); 6758 } 6759 6760 static inline u32 6761 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6762 { 6763 u32 shift = __ffs(mask); 6764 u32 orig; 6765 u32 ret; 6766 6767 orig = rtw89_read32(rtwdev, addr); 6768 ret = (orig & mask) >> shift; 6769 6770 return ret; 6771 } 6772 6773 static inline u16 6774 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6775 { 6776 u32 shift = __ffs(mask); 6777 u32 orig; 6778 u32 ret; 6779 6780 orig = rtw89_read16(rtwdev, addr); 6781 ret = (orig & mask) >> shift; 6782 6783 return ret; 6784 } 6785 6786 static inline u8 6787 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6788 { 6789 u32 shift = __ffs(mask); 6790 u32 orig; 6791 u32 ret; 6792 6793 orig = rtw89_read8(rtwdev, addr); 6794 ret = (orig & mask) >> shift; 6795 6796 return ret; 6797 } 6798 6799 static inline void 6800 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6801 { 6802 u32 shift = __ffs(mask); 6803 u32 orig; 6804 u32 set; 6805 6806 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6807 6808 orig = rtw89_read32(rtwdev, addr); 6809 set = (orig & ~mask) | ((data << shift) & mask); 6810 rtw89_write32(rtwdev, addr, set); 6811 } 6812 6813 static inline void 6814 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6815 { 6816 u32 shift; 6817 u16 orig, set; 6818 6819 mask &= 0xffff; 6820 shift = __ffs(mask); 6821 6822 orig = rtw89_read16(rtwdev, addr); 6823 set = (orig & ~mask) | ((data << shift) & mask); 6824 rtw89_write16(rtwdev, addr, set); 6825 } 6826 6827 static inline void 6828 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6829 { 6830 u32 shift; 6831 u8 orig, set; 6832 6833 mask &= 0xff; 6834 shift = __ffs(mask); 6835 6836 orig = rtw89_read8(rtwdev, addr); 6837 set = (orig & ~mask) | ((data << shift) & mask); 6838 rtw89_write8(rtwdev, addr, set); 6839 } 6840 6841 static inline u32 6842 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6843 u32 addr, u32 mask) 6844 { 6845 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6846 6847 return rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6848 } 6849 6850 static inline void 6851 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6852 u32 addr, u32 mask, u32 data) 6853 { 6854 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6855 6856 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6857 } 6858 6859 static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr) 6860 { 6861 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE || 6862 !rtwdev->hci.ops->read32_pci_cfg) 6863 return RTW89_R32_EA; 6864 6865 return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr); 6866 } 6867 6868 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6869 { 6870 void *p = rtwtxq; 6871 6872 return container_of(p, struct ieee80211_txq, drv_priv); 6873 } 6874 6875 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6876 struct ieee80211_txq *txq) 6877 { 6878 struct rtw89_txq *rtwtxq; 6879 6880 if (!txq) 6881 return; 6882 6883 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6884 INIT_LIST_HEAD(&rtwtxq->list); 6885 } 6886 6887 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6888 { 6889 void *p = rtwvif; 6890 6891 return container_of(p, struct ieee80211_vif, drv_priv); 6892 } 6893 6894 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6895 { 6896 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6897 } 6898 6899 static inline 6900 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6901 { 6902 return rtwvif_to_vif(rtwvif_link->rtwvif); 6903 } 6904 6905 static inline 6906 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6907 { 6908 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6909 } 6910 6911 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6912 { 6913 return (struct rtw89_vif *)vif->drv_priv; 6914 } 6915 6916 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6917 { 6918 return vif ? vif_to_rtwvif(vif) : NULL; 6919 } 6920 6921 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6922 { 6923 void *p = rtwsta; 6924 6925 return container_of(p, struct ieee80211_sta, drv_priv); 6926 } 6927 6928 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6929 { 6930 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6931 } 6932 6933 static inline 6934 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6935 { 6936 return rtwsta_to_sta(rtwsta_link->rtwsta); 6937 } 6938 6939 static inline 6940 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6941 { 6942 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6943 } 6944 6945 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6946 { 6947 return (struct rtw89_sta *)sta->drv_priv; 6948 } 6949 6950 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6951 { 6952 return sta ? sta_to_rtwsta(sta) : NULL; 6953 } 6954 6955 static inline struct ieee80211_bss_conf * 6956 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6957 { 6958 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6959 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6960 struct rtw89_link_conf_container *snap; 6961 struct ieee80211_bss_conf *bss_conf; 6962 6963 snap = rcu_dereference(rtwvif->snap_link_confs); 6964 if (snap) { 6965 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6966 goto out; 6967 } 6968 6969 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6970 6971 out: 6972 if (unlikely(!bss_conf)) { 6973 *nolink = true; 6974 return &vif->bss_conf; 6975 } 6976 6977 *nolink = false; 6978 return bss_conf; 6979 } 6980 6981 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6982 ({ \ 6983 typeof(rtwvif_link) p = rtwvif_link; \ 6984 struct ieee80211_bss_conf *bss_conf; \ 6985 bool nolink; \ 6986 \ 6987 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6988 if (unlikely(nolink) && (assert)) \ 6989 rtw89_err(p->rtwvif->rtwdev, \ 6990 "%s: cannot find exact bss_conf for link_id %u\n",\ 6991 __func__, p->link_id); \ 6992 bss_conf; \ 6993 }) 6994 6995 static inline struct ieee80211_link_sta * 6996 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6997 { 6998 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6999 struct ieee80211_link_sta *link_sta; 7000 7001 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 7002 if (unlikely(!link_sta)) { 7003 *nolink = true; 7004 return &sta->deflink; 7005 } 7006 7007 *nolink = false; 7008 return link_sta; 7009 } 7010 7011 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 7012 ({ \ 7013 typeof(rtwsta_link) p = rtwsta_link; \ 7014 struct ieee80211_link_sta *link_sta; \ 7015 bool nolink; \ 7016 \ 7017 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 7018 if (unlikely(nolink) && (assert)) \ 7019 rtw89_err(p->rtwsta->rtwdev, \ 7020 "%s: cannot find exact link_sta for link_id %u\n",\ 7021 __func__, p->link_id); \ 7022 link_sta; \ 7023 }) 7024 7025 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 7026 { 7027 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 7028 return RATE_INFO_BW_160; 7029 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 7030 return RATE_INFO_BW_80; 7031 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 7032 return RATE_INFO_BW_40; 7033 else 7034 return RATE_INFO_BW_20; 7035 } 7036 7037 static inline 7038 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 7039 { 7040 switch (hw_band) { 7041 default: 7042 case RTW89_BAND_2G: 7043 return NL80211_BAND_2GHZ; 7044 case RTW89_BAND_5G: 7045 return NL80211_BAND_5GHZ; 7046 case RTW89_BAND_6G: 7047 return NL80211_BAND_6GHZ; 7048 } 7049 } 7050 7051 static inline 7052 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 7053 { 7054 switch (nl_band) { 7055 default: 7056 case NL80211_BAND_2GHZ: 7057 return RTW89_BAND_2G; 7058 case NL80211_BAND_5GHZ: 7059 return RTW89_BAND_5G; 7060 case NL80211_BAND_6GHZ: 7061 return RTW89_BAND_6G; 7062 } 7063 } 7064 7065 static inline 7066 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 7067 { 7068 switch (width) { 7069 default: 7070 WARN(1, "Not support bandwidth %d\n", width); 7071 fallthrough; 7072 case NL80211_CHAN_WIDTH_20_NOHT: 7073 case NL80211_CHAN_WIDTH_20: 7074 return RTW89_CHANNEL_WIDTH_20; 7075 case NL80211_CHAN_WIDTH_40: 7076 return RTW89_CHANNEL_WIDTH_40; 7077 case NL80211_CHAN_WIDTH_80: 7078 return RTW89_CHANNEL_WIDTH_80; 7079 case NL80211_CHAN_WIDTH_160: 7080 return RTW89_CHANNEL_WIDTH_160; 7081 } 7082 } 7083 7084 static inline 7085 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 7086 { 7087 switch (rua) { 7088 default: 7089 WARN(1, "Invalid RU allocation: %d\n", rua); 7090 fallthrough; 7091 case 0 ... 36: 7092 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 7093 case 37 ... 52: 7094 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 7095 case 53 ... 60: 7096 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 7097 case 61 ... 64: 7098 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 7099 case 65 ... 66: 7100 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 7101 case 67: 7102 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 7103 case 68: 7104 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 7105 } 7106 } 7107 7108 static inline 7109 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 7110 struct rtw89_sta_link *rtwsta_link) 7111 { 7112 if (rtwsta_link) { 7113 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 7114 7115 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 7116 return &rtwsta_link->addr_cam; 7117 } 7118 return &rtwvif_link->addr_cam; 7119 } 7120 7121 static inline 7122 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 7123 struct rtw89_sta_link *rtwsta_link) 7124 { 7125 if (rtwsta_link) { 7126 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 7127 7128 if (sta->tdls) 7129 return &rtwsta_link->bssid_cam; 7130 } 7131 return &rtwvif_link->bssid_cam; 7132 } 7133 7134 static inline 7135 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 7136 struct rtw89_channel_help_params *p, 7137 const struct rtw89_chan *chan, 7138 enum rtw89_mac_idx mac_idx, 7139 enum rtw89_phy_idx phy_idx) 7140 { 7141 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 7142 mac_idx, phy_idx); 7143 } 7144 7145 static inline 7146 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 7147 struct rtw89_channel_help_params *p, 7148 const struct rtw89_chan *chan, 7149 enum rtw89_mac_idx mac_idx, 7150 enum rtw89_phy_idx phy_idx) 7151 { 7152 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 7153 mac_idx, phy_idx); 7154 } 7155 7156 static inline 7157 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 7158 enum rtw89_chanctx_idx idx) 7159 { 7160 struct rtw89_hal *hal = &rtwdev->hal; 7161 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 7162 7163 if (roc_idx == idx) 7164 return &hal->roc_chandef; 7165 7166 return &hal->chanctx[idx].chandef; 7167 } 7168 7169 static inline 7170 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 7171 enum rtw89_chanctx_idx idx) 7172 { 7173 struct rtw89_hal *hal = &rtwdev->hal; 7174 7175 return &hal->chanctx[idx].chan; 7176 } 7177 7178 static inline 7179 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 7180 enum rtw89_chanctx_idx idx) 7181 { 7182 struct rtw89_hal *hal = &rtwdev->hal; 7183 7184 return &hal->chanctx[idx].rcd; 7185 } 7186 7187 static inline 7188 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 7189 { 7190 const struct rtw89_chanctx *chanctx = 7191 container_of_const(chan, struct rtw89_chanctx, chan); 7192 7193 return &chanctx->rcd; 7194 } 7195 7196 static inline 7197 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 7198 { 7199 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 7200 7201 if (rtwvif_link) 7202 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 7203 else 7204 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 7205 } 7206 7207 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 7208 { 7209 const struct rtw89_chip_info *chip = rtwdev->chip; 7210 7211 if (chip->ops->fem_setup) 7212 chip->ops->fem_setup(rtwdev); 7213 } 7214 7215 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 7216 { 7217 const struct rtw89_chip_info *chip = rtwdev->chip; 7218 7219 if (chip->ops->rfe_gpio) 7220 chip->ops->rfe_gpio(rtwdev); 7221 } 7222 7223 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 7224 { 7225 const struct rtw89_chip_info *chip = rtwdev->chip; 7226 7227 if (chip->ops->rfk_hw_init) 7228 chip->ops->rfk_hw_init(rtwdev); 7229 } 7230 7231 static inline 7232 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev) 7233 { 7234 const struct rtw89_chip_info *chip = rtwdev->chip; 7235 7236 if (!chip->ops->bb_preinit) 7237 return; 7238 7239 chip->ops->bb_preinit(rtwdev, RTW89_PHY_0); 7240 7241 if (rtwdev->dbcc_en) 7242 chip->ops->bb_preinit(rtwdev, RTW89_PHY_1); 7243 } 7244 7245 static inline 7246 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 7247 { 7248 const struct rtw89_chip_info *chip = rtwdev->chip; 7249 7250 if (!chip->ops->bb_postinit) 7251 return; 7252 7253 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 7254 7255 if (rtwdev->dbcc_en) 7256 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 7257 } 7258 7259 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 7260 { 7261 const struct rtw89_chip_info *chip = rtwdev->chip; 7262 7263 if (chip->ops->bb_sethw) 7264 chip->ops->bb_sethw(rtwdev); 7265 } 7266 7267 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 7268 { 7269 const struct rtw89_chip_info *chip = rtwdev->chip; 7270 7271 if (chip->ops->rfk_init) 7272 chip->ops->rfk_init(rtwdev); 7273 } 7274 7275 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 7276 { 7277 const struct rtw89_chip_info *chip = rtwdev->chip; 7278 7279 if (chip->ops->rfk_init_late) 7280 chip->ops->rfk_init_late(rtwdev); 7281 } 7282 7283 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 7284 enum rtw89_phy_idx phy_idx, 7285 const struct rtw89_chan *chan) 7286 { 7287 const struct rtw89_chip_info *chip = rtwdev->chip; 7288 7289 if (chip->ops->rfk_band_changed) 7290 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 7291 } 7292 7293 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 7294 struct rtw89_vif_link *rtwvif_link, bool start) 7295 { 7296 const struct rtw89_chip_info *chip = rtwdev->chip; 7297 7298 if (chip->ops->rfk_scan) 7299 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 7300 } 7301 7302 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 7303 { 7304 const struct rtw89_chip_info *chip = rtwdev->chip; 7305 7306 if (chip->ops->rfk_track) 7307 chip->ops->rfk_track(rtwdev); 7308 } 7309 7310 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 7311 { 7312 const struct rtw89_chip_info *chip = rtwdev->chip; 7313 7314 if (!chip->ops->set_txpwr_ctrl) 7315 return; 7316 7317 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 7318 if (rtwdev->dbcc_en) 7319 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 7320 } 7321 7322 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 7323 { 7324 const struct rtw89_chip_info *chip = rtwdev->chip; 7325 7326 if (chip->ops->power_trim) 7327 chip->ops->power_trim(rtwdev); 7328 } 7329 7330 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 7331 enum rtw89_phy_idx phy_idx) 7332 { 7333 const struct rtw89_chip_info *chip = rtwdev->chip; 7334 7335 if (chip->ops->init_txpwr_unit) 7336 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 7337 } 7338 7339 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 7340 { 7341 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 7342 if (rtwdev->dbcc_en) 7343 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 7344 } 7345 7346 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 7347 enum rtw89_rf_path rf_path) 7348 { 7349 const struct rtw89_chip_info *chip = rtwdev->chip; 7350 7351 if (!chip->ops->get_thermal) 7352 return 0x10; 7353 7354 return chip->ops->get_thermal(rtwdev, rf_path); 7355 } 7356 7357 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 7358 const struct rtw89_chan *chan) 7359 { 7360 const struct rtw89_chip_info *chip = rtwdev->chip; 7361 7362 if (!chip->ops->chan_to_rf18_val) 7363 return 0; 7364 7365 return chip->ops->chan_to_rf18_val(rtwdev, chan); 7366 } 7367 7368 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 7369 struct rtw89_rx_phy_ppdu *phy_ppdu, 7370 struct ieee80211_rx_status *status) 7371 { 7372 const struct rtw89_chip_info *chip = rtwdev->chip; 7373 7374 if (chip->ops->query_ppdu) 7375 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 7376 } 7377 7378 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 7379 struct rtw89_rx_phy_ppdu *phy_ppdu) 7380 { 7381 const struct rtw89_chip_info *chip = rtwdev->chip; 7382 7383 if (chip->ops->convert_rpl_to_rssi) 7384 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 7385 } 7386 7387 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 7388 struct rtw89_rx_desc_info *desc_info, 7389 struct ieee80211_rx_status *rx_status) 7390 { 7391 const struct rtw89_chip_info *chip = rtwdev->chip; 7392 7393 if (chip->ops->phy_rpt_to_rssi) 7394 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 7395 } 7396 7397 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 7398 enum rtw89_phy_idx phy_idx) 7399 { 7400 const struct rtw89_chip_info *chip = rtwdev->chip; 7401 7402 if (chip->ops->ctrl_nbtg_bt_tx) 7403 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 7404 } 7405 7406 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 7407 { 7408 const struct rtw89_chip_info *chip = rtwdev->chip; 7409 7410 if (chip->ops->cfg_txrx_path) 7411 chip->ops->cfg_txrx_path(rtwdev); 7412 } 7413 7414 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 7415 enum rtw89_phy_idx phy_idx) 7416 { 7417 const struct rtw89_chip_info *chip = rtwdev->chip; 7418 7419 if (chip->ops->digital_pwr_comp) 7420 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 7421 } 7422 7423 static inline 7424 void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev, 7425 const struct rtw89_chan *chan, 7426 enum rtw89_rf_path path, 7427 enum rtw89_phy_idx phy_idx, 7428 struct rtw89_phy_calc_efuse_gain *calc) 7429 { 7430 const struct rtw89_chip_info *chip = rtwdev->chip; 7431 7432 if (chip->ops->calc_rx_gain_normal) 7433 chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc); 7434 } 7435 7436 static inline const struct rtw89_fw_def * 7437 __rtw89_chip_get_fw_def(const struct rtw89_chip_info *chip, 7438 const struct rtw89_chip_variant *variant) 7439 { 7440 if (variant && variant->fw_def_override) 7441 return variant->fw_def_override; 7442 7443 return &chip->fw_def; 7444 } 7445 7446 static inline 7447 const struct rtw89_fw_def *rtw89_chip_get_fw_def(struct rtw89_dev *rtwdev) 7448 { 7449 return __rtw89_chip_get_fw_def(rtwdev->chip, rtwdev->variant); 7450 } 7451 7452 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 7453 const struct rtw89_txpwr_table *tbl) 7454 { 7455 tbl->load(rtwdev, tbl); 7456 } 7457 7458 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 7459 { 7460 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 7461 const struct rtw89_regd *regd = regulatory->regd; 7462 u8 txpwr_regd = regd->txpwr_regd[band]; 7463 7464 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 7465 return RTW89_ETSI; 7466 7467 return txpwr_regd; 7468 } 7469 7470 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 7471 enum rtw89_phy_idx phy_idx) 7472 { 7473 const struct rtw89_chip_info *chip = rtwdev->chip; 7474 7475 if (chip->ops->ctrl_btg_bt_rx) 7476 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 7477 } 7478 7479 static inline 7480 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 7481 struct rtw89_rx_desc_info *desc_info, 7482 u8 *data, u32 data_offset) 7483 { 7484 const struct rtw89_chip_info *chip = rtwdev->chip; 7485 7486 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 7487 } 7488 7489 static inline 7490 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 7491 struct rtw89_tx_desc_info *desc_info, 7492 void *txdesc) 7493 { 7494 const struct rtw89_chip_info *chip = rtwdev->chip; 7495 7496 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 7497 } 7498 7499 static inline 7500 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 7501 struct rtw89_tx_desc_info *desc_info, 7502 void *txdesc) 7503 { 7504 const struct rtw89_chip_info *chip = rtwdev->chip; 7505 7506 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 7507 } 7508 7509 static inline 7510 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 7511 { 7512 const struct rtw89_chip_info *chip = rtwdev->chip; 7513 7514 return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel); 7515 } 7516 7517 static inline 7518 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 7519 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 7520 { 7521 const struct rtw89_chip_info *chip = rtwdev->chip; 7522 7523 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 7524 } 7525 7526 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 7527 { 7528 const struct rtw89_chip_info *chip = rtwdev->chip; 7529 7530 chip->ops->cfg_ctrl_path(rtwdev, wl); 7531 } 7532 7533 static inline 7534 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 7535 u32 *tx_en, enum rtw89_sch_tx_sel sel) 7536 { 7537 const struct rtw89_chip_info *chip = rtwdev->chip; 7538 7539 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 7540 } 7541 7542 static inline 7543 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 7544 { 7545 const struct rtw89_chip_info *chip = rtwdev->chip; 7546 7547 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 7548 } 7549 7550 static inline 7551 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 7552 struct rtw89_vif_link *rtwvif_link, 7553 struct rtw89_sta_link *rtwsta_link) 7554 { 7555 const struct rtw89_chip_info *chip = rtwdev->chip; 7556 7557 if (!chip->ops->h2c_dctl_sec_cam) 7558 return 0; 7559 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 7560 } 7561 7562 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 7563 { 7564 __le16 fc = hdr->frame_control; 7565 7566 if (ieee80211_has_tods(fc)) 7567 return hdr->addr1; 7568 else if (ieee80211_has_fromds(fc)) 7569 return hdr->addr2; 7570 else 7571 return hdr->addr3; 7572 } 7573 7574 static inline 7575 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 7576 { 7577 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 7578 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 7579 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 7580 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 7581 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 7582 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 7583 return true; 7584 return false; 7585 } 7586 7587 static inline 7588 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 7589 { 7590 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 7591 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 7592 return true; 7593 7594 return false; 7595 } 7596 7597 static inline 7598 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 7599 { 7600 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 7601 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 7602 return true; 7603 7604 return false; 7605 } 7606 7607 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 7608 enum rtw89_fw_type type) 7609 { 7610 struct rtw89_fw_info *fw_info = &rtwdev->fw; 7611 7612 switch (type) { 7613 case RTW89_FW_WOWLAN: 7614 case RTW89_FW_WOWLAN_B: 7615 return &fw_info->wowlan; 7616 case RTW89_FW_LOGFMT: 7617 return &fw_info->log.suit; 7618 case RTW89_FW_BBMCU0: 7619 return &fw_info->bbmcu0; 7620 case RTW89_FW_BBMCU1: 7621 return &fw_info->bbmcu1; 7622 default: 7623 break; 7624 } 7625 7626 return &fw_info->normal; 7627 } 7628 7629 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 7630 unsigned int length) 7631 { 7632 struct sk_buff *skb; 7633 7634 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 7635 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 7636 if (!skb) 7637 return NULL; 7638 7639 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 7640 return skb; 7641 } 7642 7643 return dev_alloc_skb(length); 7644 } 7645 7646 static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev, 7647 struct rtw89_tx_skb_data *skb_data) 7648 { 7649 return rcu_access_pointer(skb_data->wait); 7650 } 7651 7652 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7653 struct rtw89_tx_skb_data *skb_data, 7654 u8 tx_status) 7655 { 7656 struct rtw89_tx_wait_info *wait; 7657 7658 guard(rcu)(); 7659 7660 wait = rcu_dereference(skb_data->wait); 7661 if (!wait) 7662 return false; 7663 7664 wait->tx_done = tx_status == RTW89_TX_DONE; 7665 /* Don't access skb anymore after completion */ 7666 complete_all(&wait->completion); 7667 return true; 7668 } 7669 7670 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7671 { 7672 switch (rtwdev->mlo_dbcc_mode) { 7673 case MLO_1_PLUS_1_1RF: 7674 case MLO_1_PLUS_1_2RF: 7675 case DBCC_LEGACY: 7676 return true; 7677 default: 7678 return false; 7679 } 7680 } 7681 7682 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7683 { 7684 if (!rtwdev->dbcc_en) 7685 return BIT(RTW89_PHY_0); 7686 7687 switch (rtwdev->mlo_dbcc_mode) { 7688 case MLO_0_PLUS_2_1RF: 7689 case MLO_0_PLUS_2_2RF: 7690 return BIT(RTW89_PHY_1); 7691 case MLO_1_PLUS_1_1RF: 7692 case MLO_1_PLUS_1_2RF: 7693 case MLO_2_PLUS_2_2RF: 7694 case DBCC_LEGACY: 7695 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7696 case MLO_2_PLUS_0_1RF: 7697 case MLO_2_PLUS_0_2RF: 7698 default: 7699 return BIT(RTW89_PHY_0); 7700 } 7701 } 7702 7703 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7704 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7705 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7706 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7707 (bb = &rtwdev->bbs[__phy_idx])) 7708 7709 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7710 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7711 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7712 if ((bb = &rtwdev->bbs[__phy_idx])) 7713 7714 static inline 7715 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7716 enum rtw89_phy_idx phy_idx) 7717 { 7718 if (phy_idx >= RTW89_PHY_NUM) 7719 return &rtwdev->bbs[RTW89_PHY_0]; 7720 7721 return &rtwdev->bbs[phy_idx]; 7722 } 7723 7724 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7725 { 7726 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7727 7728 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7729 return true; 7730 7731 return false; 7732 } 7733 7734 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval) 7735 { 7736 switch (interval) { 7737 default: 7738 case RTW89_TFC_INTERVAL_2SEC: 7739 return bytes >> 18; /* bytes/2s --> Mbps */; 7740 case RTW89_TFC_INTERVAL_100MS: 7741 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */ 7742 } 7743 } 7744 7745 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7746 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7747 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7748 struct sk_buff *skb, bool fwdl); 7749 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7750 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7751 struct rtw89_tx_wait_info *wait, int qsel, 7752 unsigned int timeout); 7753 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7754 struct rtw89_tx_desc_info *desc_info, 7755 void *txdesc); 7756 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7757 struct rtw89_tx_desc_info *desc_info, 7758 void *txdesc); 7759 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7760 struct rtw89_tx_desc_info *desc_info, 7761 void *txdesc); 7762 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev, 7763 struct rtw89_tx_desc_info *desc_info, 7764 void *txdesc); 7765 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7766 struct rtw89_tx_desc_info *desc_info, 7767 void *txdesc); 7768 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7769 struct rtw89_tx_desc_info *desc_info, 7770 void *txdesc); 7771 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel); 7772 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel); 7773 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel); 7774 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7775 struct rtw89_rx_desc_info *desc_info, 7776 struct sk_buff *skb); 7777 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7778 struct rtw89_rx_desc_info *desc_info, 7779 u8 *data, u32 data_offset); 7780 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7781 struct rtw89_rx_desc_info *desc_info, 7782 u8 *data, u32 data_offset); 7783 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev, 7784 struct rtw89_rx_desc_info *desc_info, 7785 u8 *data, u32 data_offset); 7786 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7787 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7788 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7789 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7790 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7791 struct rtw89_vif_link *rtwvif_link, 7792 struct rtw89_sta_link *rtwsta_link); 7793 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7794 struct rtw89_vif_link *rtwvif_link, 7795 struct rtw89_sta_link *rtwsta_link); 7796 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7797 struct rtw89_vif_link *rtwvif_link, 7798 struct rtw89_sta_link *rtwsta_link); 7799 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7800 struct rtw89_vif_link *rtwvif_link, 7801 struct rtw89_sta_link *rtwsta_link); 7802 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7803 struct rtw89_vif_link *rtwvif_link, 7804 struct rtw89_sta_link *rtwsta_link); 7805 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7806 struct ieee80211_sta *sta, 7807 struct cfg80211_tid_config *tid_config); 7808 void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 7809 struct ieee80211_ampdu_params *params, bool enable); 7810 void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev); 7811 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7812 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7813 int rtw89_core_init(struct rtw89_dev *rtwdev); 7814 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7815 int rtw89_core_register(struct rtw89_dev *rtwdev); 7816 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7817 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7818 u32 bus_data_size, 7819 const struct rtw89_chip_info *chip, 7820 const struct rtw89_chip_variant *variant); 7821 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7822 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7823 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7824 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7825 u8 mac_id, u8 port); 7826 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7827 struct rtw89_sta *rtwsta, u8 mac_id); 7828 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7829 unsigned int link_id); 7830 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7831 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7832 unsigned int link_id); 7833 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7834 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7835 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 7836 struct rtw89_vif_link *rtwvif_link); 7837 const struct rtw89_6ghz_span * 7838 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7839 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7840 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7841 struct rtw89_chan *chan); 7842 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7843 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7844 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7845 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7846 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7847 struct rtw89_sta_link *rtwsta_link, u8 tid, 7848 u8 *cam_idx); 7849 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7850 struct rtw89_sta_link *rtwsta_link, u8 tid, 7851 u8 *cam_idx); 7852 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7853 struct ieee80211_sta *sta); 7854 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7855 struct ieee80211_sta *sta); 7856 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7857 struct ieee80211_sta *sta); 7858 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7859 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7860 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7861 struct rtw89_vif_link *rtwvif_link); 7862 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate); 7863 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7864 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7865 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7866 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7867 struct rtw89_traffic_stats *stats); 7868 struct rtw89_wait_response * 7869 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 7870 __acquires(rtw89_wait); 7871 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 7872 struct rtw89_wait_response *prep, int err) 7873 __releases(rtw89_wait); 7874 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7875 const struct rtw89_completion_data *data); 7876 int rtw89_core_start(struct rtw89_dev *rtwdev); 7877 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7878 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7879 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7880 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7881 bool qos, bool ps, int timeout); 7882 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7883 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7884 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7885 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7886 const u8 *mac_addr, bool hw_scan); 7887 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7888 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7889 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7890 bool active); 7891 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7892 struct rtw89_vif_link *rtwvif_link, 7893 struct ieee80211_bss_conf *bss_conf); 7894 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7895 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7896 unsigned int link_id); 7897 void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new); 7898 void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type); 7899 void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type); 7900 7901 #endif 7902